JPH0691207B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a semiconductor device including at least a MOS transistor.

[Background of the Invention]

1A and 1B are a plan view and a cross-sectional view of a semiconductor memory device having an N-channel MOS transistor as a memory cell as an example of a conventional semiconductor device.

Reference numeral 100 is a GND (ground) wiring using a diffusion layer 101 is a data line using an Al wiring, 102 is a word line using a Si semiconductor, 103
Is a contact hole 104 for connecting one end electrode of the NMOS transistor constituting the memory cell to the data line 101.
Type substrate, 105 is a P type well region, 106 is an N type Si gate 107
Is a gate oxide film, 108 is an N-type source region connected to the ground potential GND, and 109 is an N-type drain region. In the GND wiring 100 of the memory cell configured by the NMOS transistor, since the data line 101 is normally wired by Al, the GND wiring 100 cannot be wired by contacting the diffusion layer with Al, and the source and drain layers of the NMOS transistor cannot be wired. The diffusion region is used as it is as wiring. When the diffusion region is used as a wiring, particularly in a semiconductor memory device, it is necessary to reduce the wiring resistance because it is necessary to speed up the writing and reading times of information. However, the resistance of the source and drain layers of the MOS transistor tends to increase due to the shallow junction due to the miniaturization. Therefore, as shown in FIG. 2, for resistance resistance of the GND wiring 100, the Al wiring 20 is used as the GND wiring for every data line 201 of the number.
GN using diffusion layer by running 2 in parallel with data line 201
The D wiring 200 is connected by a contact ball 203 to reduce wiring resistance. However, this method causes an increase in the area and the wiring capacitance for the Al wiring 202 serving as the GND wiring.

In the case of a memory cell composed of MOS transistors,
Due to the shallow junction, the junction area of the source and drain is reduced and the junction capacitance is reduced. When the junction capacitance is reduced, and when the source and drain are irradiated with α-rays, recombination of stored charges may occur due to the generated electron-hole pairs, which may change the held information.

[Object of the Invention]

An object of the present invention is to provide a source and / or source of a MOS transistor in a semiconductor device including at least a MOS transistor.
Another object is to provide a semiconductor device in which the resistance of the drain is reduced and the chip area can be reduced.

[Outline of Invention]

The present invention which achieves the above object is characterized in that, in a MOS transistor in which a source region and a drain region of the other conductivity type are provided on the main surface of a semiconductor layer of the one conductivity type, the source region and the drain region 1 or the drain region are provided. The other conductivity type region is deeper than the source region and / or the drain region and has a high impurity concentration so as to overlap the region.

Further, a feature of the present invention is that a MOS transistor in which a source region and a drain region of the other conductivity type are provided on the main surface of a semiconductor layer of one conductivity type, and the source region and / or the drain region are provided on the main surface. In a case where a bipolar transistor having a deep and high impurity concentration one main terminal region of the other conductivity type is mixed, one of the main regions is overlapped with the source region and / or the drain region. The other conductivity type region is provided with substantially the same depth as the terminal region and with substantially the same impurity concentration.

In a preferred embodiment of the present invention, the other conductivity type region is provided so as to overlap the source region and / or the drain region of the plurality of MOS transistors.

Example of Invention

 An embodiment of the present invention will be described below.

3 (a) and 3 (b) are a plan view and a cross-sectional view of one embodiment of the semiconductor device of the present invention.
This is a semiconductor memory device in which S-transistors are mixed and the memory cell portion is composed of NMOS.

The overall structure of a semiconductor memory device in which a bipolar transistor and a MOS transistor are mixed is described in JP-B-43-
19780, JP-B-45-8258, JP-A-55-12999
It is known from the publication No. 4, etc.

In FIGS. 3 (a) and 3 (b), 110 is a P-type buried region, 113 is a P-type substrate, and 111 is a low resistance (≦ 10 Ω / □) diffusion region for extracting the collector electrode of the bipolar transistor. The N-type diffusion region is deep and has substantially the same impurity concentration. The N-type diffusion region 111 is deeper than the source region 108 of the NMOS transistor and has a high impurity concentration. In this structure, the source 108 of the NMOS transistor and the diffusion region 111 are arranged so as to overlap each other, and the GND wiring resistance can be made smaller by superposition than the conventional case where only the source region 108 is used as a wiring.

FIG. 4 shows a manufacturing method of the embodiment of the present invention shown in FIG.

FIG. 4A shows a high concentration N-type buried layer 2 and a P-type buried layer 3 selectively formed on one main surface of the P-type semiconductor substrate 1. In FIG. 4 (b), after the N-type and P-type buried layers 2 and 3 are formed, heat treatment is performed to form an N-type epitaxial layer 1 ', and further the N-type well layer 4 and the P-type well layer 5 are formed. The formed state is shown. FIG. 4C shows a state in which a thin SiO ₂ film is formed on the structure of FIG. 4B, and then a selective oxide film 6 for element isolation is formed by thermal oxidation using the silicon nitride film as a mask. Shows.
In FIG. 4 (d), an S gate 10 serving as a gate of a PMOS transistor and a Si gate 12 serving as a gate of an NMOS transistor are formed by an ordinary CMOS process cell, and the Si gates 10 and 12 are formed into S gates.
After covering with the iO ₂ film 11, the N-type diffusion layer 7 for drawing out the collector electrode of the NPN bipolar transistor is formed and at the same time NM
The N-type diffusion region 8 is formed in a portion where the diffusion layer at one end of the OS transistor is used as a wiring, and then the P-type base region 9 of the bipolar transistor is formed. In FIG. 4 (e), the N-type diffusion layer 7 is heat-treated to form the N-type buried region 2
After contacting the N-type diffusion region with the P-type buried region 3,
The emitter electrode 14 of the bipolar transistor 301 is formed of polysilicon, the polysilicon emitter electrode is doped with an N-type impurity, and the emitter diffusion region 13 is formed by heat treatment to complete the bipolar transistor 301. FIG. 4 (f) shows a P-type source 15, a drain 16, and a P-type Si gate 10 'formed by a normal CMOS process to complete the PMOS transistor 302, and then an N-type source 17, The state where the NMOS transistor 303 is completed by forming the drain 18 and the N-type Si gate 12 ', the passivation film 19 of the device is attached, and the contact hole for drawing out Al is opened is shown. Fig. 4 (g) shows Al
The structure of the present embodiment is completed by attaching the extraction electrode 21.

According to this method, the diffusion resistance at one end of the electrode of the NMOS transistor can be reduced by utilizing the step of forming the N-type diffusion layer 7 for drawing out the collector of the bipolar transistor.

FIG. 5 shows the relationship between the wiring length and the resistance R of the conventional wiring method (diffusion resistance 40 Ω / □) shown in FIG. 1 and the wiring method of this embodiment (diffusion resistance 10 Ω / □) with the wiring width of the diffusion layer being constant. Is shown. According to the method of the present invention, the GND wiring resistance can be improved by 75% as compared with the GND wiring resistance of the conventional MOS process. Particularly in the case of a semiconductor memory device, since the wiring becomes long, a diffusion region for extracting the collector electrode is simultaneously formed in the source region to be the GND wiring of the MOS transistor and the source diffusion regions 108 of the plurality of MOS transistors are formed as in the present embodiment. The resistance of the connected GND wiring can be reduced, and the area required for the Al wiring 202, which is the conventional GND wiring as shown in FIG. 2, can be eliminated.

Also, a process made by mixing bipolar transistors and MOS transistors (hereinafter abbreviated as Bi-CMOS process)
When one end of a plurality of MOS transistors is connected to a power supply and a diffusion layer is used as a wiring, or when one end of a plurality of MOS transistors is connected to a power supply and the other end is connected to a GND and a diffusion layer is used as a wiring, The same effect can be achieved by using a structure in which the diffusion region for leading out the collector electrode and the diffusion region at one end or both ends of the MOS transistor are superposed, and the diffusion electrode of the MOS transistor is made low by the Bi-CMOS process. Even in the case of resistance, the same effect can be achieved and the present invention can be applied.

Another embodiment of the present invention will be described below with reference to FIGS. 6 (a) and 6 (b).

FIG. 6 (a) shows an example of a memory cell of a MOS transistor having a high resistance load R. Reference numeral 400 is a word line, 401 is a data line, and M1, M2, M3, and M4 are NMOS transistors to form a flip-flop type memory cell. The information given to the memory cell is held by the junction capacitance C of the drains of M1 and M3 and M2 and M4. The memory must be able to write and read accurately, but when the memory cell is irradiated with α-rays, the electron-hole pairs generated by the α-ray irradiation generate charges (information ) And the memory content may change due to recombination. In order to reduce the influence of carrier recombination due to α-rays, the junction capacitance C is increased by increasing the junction area of the drain of the MOS transistor.

Generally, MOS transistors are formed on the surface of a wafer, but as miniaturization progresses, the source and drain regions are also formed shallower. For this reason, in order to make a memory cell capable of preventing α rays and having a high degree of integration, an effective means of increasing the junction capacitance for storing memory information and reducing the influence of electron-hole pairs generated by α rays. This is an important issue to consider.

An effective junction capacitance increasing method and an α ray countermeasure method according to this embodiment will be described with reference to FIG. 6 (b).

FIG. 6 (b) shows an example of the M3 and M4 MOS transistors of FIG. 6 (a) which are the constituent elements of the memory cell.

113 is a substrate of the first conductivity type, and 110 is the first conductivity type 11
A buried layer having the same conductivity type as that of 3 and having an impurity concentration higher than 113; 105, layers 108 and 109 having the same conductivity type as 113, 110 and having an impurity concentration serving as a substrate of a MOS transistor, serving as the source and drain of the MOS transistor; 107 is a gate oxide film, and 106 is a gate electrode layer of a MOS transistor. Here, 111 and 112 are layers that are formed at the same time as the diffusion layer for drawing out the collector electrode of the bipolar transistor described above, and are formed by stacking the source 108 and the drain 109, respectively.

As described above, α-rays generate electron-hole pairs when passing through a semiconductor.

The phenomenon that the charge generated by this α-ray destroys the stored charge is pn
Two cases can be considered: charge collection by an electric field in the depletion layer of the junction and charge collection by diffusion outside the depletion layer.

For the former, the method of increasing the junction capacitance is effective, and for the latter, a potential barrier is formed immediately below the depletion layer and the charge is
A method that prevents them from gathering on the pn junction side is effective.

In FIG. 6B, the former can be dealt with by increasing the capacity of the layer 112, and the latter can be dealt with by the buried layer 110.

As shown in FIG. 6B, in the MOS memory cell of the same conductivity type as the substrate and formed on the high-concentration buried layer, the diffusion region for extracting the collector electrode of the bipolar transistor is used as described in the first embodiment. By overlapping 112 with the drain 109, the junction area can be increased and the junction capacitance can be increased, and the influence of α rays from the substrate side can be reduced. Further, as described above, since the source diffusion regions of M3 and M4 are used as the GND wiring, the wiring resistance can be reduced by providing the collector extraction diffusion region 111.
Al required for the GND wiring combined with the conventional Al wiring of the diffusion layer
The wiring area can be reduced.

The present invention is not limited to the above-described embodiments, and various modifications such as reversing the P type and the N type are conceivable.

As described above, according to the embodiment of the present invention, it is possible to reduce the diffusion resistance of the source and drain of the MOS transistor manufactured by the B: C MOS process, and accordingly reduce the wiring area.

In addition, the source and drain of the memory cell are overlaid with a high-concentration layer that can be made at the same time as the bipolar transistor and collector, and are connected to a layer of the opposite conductivity type that contacts the substrate, increasing the junction capacitance and the effect of carriers generated on the substrate. It is possible to reduce α, so that α-ray countermeasures can be taken.

〔The invention's effect〕

According to the present invention, the resistance of the source and / or the drain of the MOS transistor can be reduced and the chip area can be reduced.

[Brief description of drawings]

1 and 2 are views showing a conventional GND wiring method for a memory, FIG. 3 is a view showing an embodiment of the present invention, and FIG. 4 is a view showing a manufacturing process according to the embodiment of the present invention. FIG. 5 is a diagram comparing an embodiment of the present invention with a wiring length and resistance according to a conventional method, and FIG. 6 is a diagram showing another embodiment of the present invention. 108 …… Source area, 109 …… Source area, 8,111,112…
... On the other hand, a conductivity type region.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Yoshiaki Yazawa 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Takahide Ikeda 3-chome, Saiwaicho, Hitachi, Ibaraki No. 1 Hitachi Ltd., Hitachi Research Laboratory (72) Inventor Masanori Odaka 1450, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Computer Development Division Device Development Center (56) Reference JP-A-58-56450 ( JP, A) JP 57-188862 (JP, A)

Claims (1)

[Claims] 1. A semiconductor substrate comprising a memory cell and an NPN-type bipolar transistor, wherein the NPN-type bipolar transistor is directly below the N-type collector region and is in contact with the N-type collector region. An N-type high impurity concentration collector buried region formed inside the semiconductor substrate, and an N-type collector extraction impurity region formed so as to come into contact with the N-type high impurity concentration collector buried region from the surface of the semiconductor substrate. The memory cell has a first drive circuit and a second drive circuit in which the gate and the drain are cross-connected.
A MOS transistor, first and second load elements connected to the drains of the first and second drive MOS transistors, a gate thereof is connected to a word line, and a source / drain path thereof is the first and second A first connected between the drain of the second drive MOS transistor and the pair of data lines;
And a second transfer MOS transistor, wherein the first and second drive MOS transistors of the memory cell overlap the N-type source region and at least a part of the N-type source region. An N-type channel MOS transistor having an N-type high impurity concentration source region formed, an N-type drain region, and an N-type high impurity concentration drain region formed so as to overlap at least a part of the N-type drain region. And the N-type high impurity concentration source region and the N-type high impurity concentration drain region of the first and second drive MOS transistors of the N-type channel of the memory cell are the NPN.
Of the N-type collector transistor, the N-type collector extraction impurity region, the N-type high impurity concentration source region, and the N-type high impurity concentration drain The region is a semiconductor device formed deeper than the N-type source region and the N-type drain region.