JPS62293760A - Static memory - Google Patents

Abstract

PURPOSE:To improve integrity by a method wherein an MOS-FET and a bipolar transistor are formed in series in a same well and a lateral transistor is employed as the bipolar transistor. CONSTITUTION:Surface inversion layers 61 and 62 are induced in the surface of a P-type well 2 directly under respective electrodes by applying positive potential to gate electrodes 41 and 42. 2nd diffused layer 52 is grounded and used as an emitter, the P-type well 2 is used as a base and 1st diffused layer 51 is, together with the inversion layer 62, used as a collector to constitute a bipolar transistor 200. On the other hand, the 1st gate electrode 41, the 1st diffused layer 51 and 3rd diffused layer 53 are used as a gate, a source and a drain respectively to constitute an MOSFET 100. With this constitution, the memory operation can be performed only by two transistors in the same well so that the integrity two times of the integrity of the conventional constitution can be obtained. 1: N-type substrate, 3: gate insulating film, 7: switching transistor, B: word line, 9: bit line, 10: oxide film side wall.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention Field of Industrial Application The present invention relates to a static memory that can retain information without being reproduced as long as power is applied.

Prior art static memories traditionally consisted of two MO3FII:Ts and two load resistors or two n-channel and two p-channel MO3FICTs. Dynamic memory, on the other hand, uses a single capacitor to store data, so
The density of static memory has been one-fourth that of dynamic memory, and the unit per bit has also been high.

Problems to be Solved by the Invention Conventional static memories have a problem of a large number of elements, that is, a low degree of integration.

The present invention seeks to solve this problem.

Means for Solving the Problems In order to improve the degree of integration, a MOSFET and a bipolar transistor are formed in series in the same well, and a lateral type bipolar transistor is used to simplify manufacturing.

Minority carriers generated by weak avalanche near the drain of the working MOSFET are supplied as the base current of the bipolar transistor, so that a current flows between the emitter and the collector, which becomes the drain current of the MOSFET. At this time, if the current amplification factor of the bipolar transistor is hfe and the avalanche multiplication factor of the MOSFET is m, then hfe A sufficiently small first state '0 level is realized. At the '1# level, no current flows, the bipolar side is off, and the MOSFET is on.

The signal is read/written (Read 7/wr1tθ) as the potential at the connection point between the bipolar and MOSFET.

Example An embodiment of the present invention shown in the figures will be described below.

A P-type well 2 having a limited area on one main surface of an N-type silicon semiconductor substrate 1, first and second gate electrodes 41 and 42 installed on the surface of the well with a gate insulating film 3 interposed therebetween, and the well 2. A diagonal-shaped first 2.3 diffusion layer 51. is provided near the end of the gate electrode 41.42 on the surface of the gate electrode 41.42. E52 and E53 are formed. First and third diffusion layers 51.53
has an overlapping portion with the gate electrode 41, but the second diffusion layer 52 is offset from the gate electrode 42. By applying a positive potential to the gate electrodes 41 and 42,
Surface inversion layers 61, 62 are induced on the P-well surface directly beneath each electrode.

The second diffusion layer 52 is grounded and serves as a nimitter, and P
The well 2 serves as a base, and the first diffusion layer 61 including the inversion layer 62 serves as a collector to form a bipolar transistor 200.
Configure. Wb in the figure is therefore the base width of the lateral bipolar transistor. First gate electrode 41. 1st
The diffusion layer 61 and the third diffusion layer 63 serve as a gate, a lease, and a drain, respectively, and constitute the MOSFET 100.

The drain is connected to the positive power supply VDfl.

1st. Second. The third diffusion layers 61, 52, and 53 are
It is formed using oxide sidewalls 10 that are self-aligned to 1.42 mm.

In the vicinity of the drain 63, when a drain current flows, holes are generated due to ionization collision (avalanche) due to the strong electric field. This flows within the P-well toward the emitter 52 and becomes the base current of the bipolar transistor 200. Emi
Electrons are injected from the contactor 52 into the base of width Wb and form the inversion layer 6.
2 and becomes the collector current, but this remains as MO
The current continues to flow as it becomes the drain current of the SFET 100.

The base width Wb can be made 0.2 to 0.3 μm with the current technology, so it is much finer than the conventional base width of 1 μm or more. On the other hand, when the collector potential becomes high, the inversion layer 62 disappears and becomes depleted, so even if the base width is this small, the present bipolar transistor has a high breakdown voltage.

The first diffusion layer 61, which is the collector or source, is a node for writing and reading signals in the memory cell, and is connected to one terminal of the switch transistor 7, which is turned on and off by the word line 8 and connected to the bit line 9. It is connected.

The two states of memory are 'O lebel = bipolar transistor is more on state = current on '1 Lebel = bipolar transistor is off state = current off is stored correspondingly.

As mentioned above, according to the present invention, the storage operation is performed using only two transistors in the same well, so the storage efficiency is 22% compared to the conventional method.
Double the degree of integration can be obtained.

'fife of a lateral bipolar transistor is extremely large (102 to 1o5), so hfe(m-
1):) According to 1, the avalanche multiplication factor m of the MOSFET may be small. This means that the memory operates even at a low power supply voltage (VDD), and therefore the static memory of the present invention is low power.

[Brief explanation of the drawing]

The figure is a sectional view of a static memory according to an embodiment of the present invention. 1...N type substrate, 2...P well, 4
1.42...Gate electrode, 61.62...
...Surface inversion layer, 100...MOSFET,
200...Bipolar transistor.

Claims (1)

[Claims] A two-conductivity type well whose area is limited to one main surface of a one-conductivity type semiconductor substrate, first and second gate electrodes installed on the surface of this well with an insulating film interposed therebetween, and the vicinity of the end of this gate electrode. a first conductivity type provided on the surface of the well;
the first diffusion layer includes the first and second diffusion layers;
It is located between the gate electrodes and has an overlapping portion with each of the gate electrodes,
The second diffusion layer is offset from the other end of the second gate electrode, and the third diffusion layer is located at the other end of the first gate electrode and has an overlapping portion with the first gate electrode. , a MOSFET is formed in the first and third diffusion layers, and a surface inversion layer is formed on the surface of the well directly under the second gate electrode, and the first diffusion layer, second diffusion layer, and the well connected to the surface inversion layer are horizontal type. A static memory comprising a bipolar transistor and configured to store information by supplying minority carriers due to avalanche of the MOSFET as a base current of the bipolar transistor.