JPH0311549B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a memory using a bipolar transistor whose base region is almost pinched off in the main operating region and whose effective base width is sufficiently thin.

[Prior art]

In conventional integrated circuits, bipolar transistors (hereinafter referred to as BPTs) are used in memory sections that require high-speed operation. Although BPTs operate at high speeds, they consume more power and have lower input impedance than MOS field effect transistors (hereinafter referred to as MOSFETs), so they cannot be directly connected to the next stage. It has a fatal drawback in that it cannot be used in semiconductor integrated circuits that require a high degree of integration. Furthermore, the operating speed of BPT is limited by the large capacitance between each electrode and the significant accumulation effect of minority carriers injected into the base. Aside from these drawbacks of BPT, it has high input impedance, can be directly connected to the next stage, has small capacitance between each electrode, and has low exchange conductance.
It is quite close to BPT, is large, has a large driving capacity,
The inventor of this application proposed and developed a static induction transistor as a transistor that can operate at high speed and obtain a large number of fan-outs, and BPT's I ² L
(Integrated Injection Logic), etc., has been successfully applied to integrated circuits (Patent No.
1181984 (Special Publication No. 58-111020) ``Semiconductor integrated circuit'', Patent No. 1208034 (Special Publication No. 58-38938) ``Semiconductor integrated circuit'', September 1st to 3rd, 1978 Proceedings of the International Conference on Solid State Devices pp.53-54).

BPT where the base area is mostly pinched off
As an individual device, it was known by R. Zuleeg and others that it exhibits unsaturated current-voltage characteristics. (U.S. Patent No. 3,409,812).

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit that has a small minority carrier accumulation effect, good frequency characteristics, and high-speed operation by using the BPT in a memory device.

[Summary of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 1a is a plan view of a static RAM memory cell of the present invention, and FIG. 1b is a bird's-eye view of the section taken along line X-X' in FIG. 1a. 3″ is the address column line,
3′′′′, 3′′′′ are row lines for writing and reading,
10,
10' is a wiring for applying a power supply voltage. Figure 1b
The n ⁺ region 1, the p region 5, the n ⁺ regions 3 and 3' are respectively the first transistors _T1 constituting the memory.
The collector, base, and emitter of 6,4′
are a collector extraction region and a base extraction region, and 7 and 8 are an insulating layer and an insulator.
9 and 9' are polysilicon resistors, the collector electrode 6' of the first transistor is connected to the power supply voltage application wiring 10 via the polysilicon resistor 9, and the base electrode 4' is connected via the polysilicon resistor 9'. and is connected to the power supply voltage application wiring 10'. As shown in FIG. 1a, the collector electrode 6' of the first transistor is connected and coupled to the base extraction region of the second transistor _T2 constituting the memory cell,
The collector extraction region 61 of the second transistor T ₂ and the base extraction region 4 of the first transistor T ₁ are connected and coupled to each other via an electrode 4'. 31 and 31' are the emitters of the second transistor _T2 , 42 and 62 are the base extraction regions of the second transistors of the adjacent memory cells, respectively;
This is the collector extraction region of the first transistor. 9'' is the polysilicon resistance of the adjacent memory cell.As shown in Figure 1, a BPT structure where an opposite conductivity type region exists across the channel region of the static induction transistor is inverted. In order to operate almost the same as that using a type static induction transistor, the base region 5 existing between the emitter and collector of the BPT must be almost depleted by the diffusion potential of the n ⁺ p or n ^- p contact. Since the base 5 existing between the emitter and collector is generated by diffusion from the p region 4, its impurity density is naturally lower than the original region 4.
It's lower than that. Therefore, in the structure shown in FIG. 1, the base region 5 is quite thin and has a low impurity density, and becomes almost a depletion layer due only to the diffusion potential generated at the contact with the opposite conductivity type region, resulting in an almost pinch-off state. ing. When the base region is in a pinch-off state, the potential of the base region approaches the potential of the regions of opposite conductivity type existing on both sides, but in this case, the base is not completely pinched off and the potential is almost equal to the potential of the regions of opposite conductivity type on both sides. The base is almost pinched off, and the potential barrier exists and is thin enough to control the amount of carrier injection from the emitter to the base. It is defined as If the thickness and impurity density of the base region are selected to achieve this state, the carriers flowing from the emitter to the collector will be injected into the collector side over the potential barrier, just like in the case of a static induction transistor, and will drift. As in,
Almost the same behavior as multiple carrier injection, BPT
The effect of minority carrier accumulation in the base region due to minority carrier injection does not appear. In addition, due to the presence of the p-base layer, the distance between the source and drain (between the emitter and collector) is smaller than that of a static induction transistor.
Even if the channel length of is shortened, it is easy to make the normally-off type, which is advantageous for shortening the channel, shortens the carrier travel time between the emitter and the collector, and increases the conversion conductance g _n . At the same time, the base
The capacitance between the emitter and the base and collector is reduced and the operating speed is increased. Since the BPT used in integrated circuits is very small in size,
The base resistor that controls the operating speed of the BPT is the first
If the impurity density in region 4 in the figure is increased, there will be little problem. That is, the potential barrier of the base is basically controlled by the base extraction region 4 in a capacitive coupling manner, and control by a very small amount of holes injected into the base is superimposed on this. As shown in Figure 1, the current-voltage characteristics of a BPT formed so that the base region is almost pinched off and a thin potential barrier layer remains between the emitter and collector are normal.
It is known that BPT exhibits a saturated characteristic in which the collector current is almost constant above a certain collector voltage, whereas it exhibits an unsaturated characteristic in which the collector current gradually increases as the collector voltage increases. The thickness of the potential barrier layer is determined by the value of the current flowing through the load when it is in a conductive state, and if a sufficiently large current is to flow through the load, it must be sufficiently thin and set close to the emitter region. . Although FIG. 1 shows the case where the n ^- high resistance region exists on the collector side, it is of course possible for the n ⁺ region to be in direct contact with the base.

FIG. 2 is a circuit representation of FIG. 1, showing an example of a static RAM memory cell configured with the BPT. Address lines and data read/write lines are all connected to the emitter.

The circuit shown in FIG. 2 has a small interelectrode capacitance, little minority carrier accumulation effect, exhibits current-voltage characteristics that deviate from the saturated type, has a higher input impedance than the conventional BPT, and has a faster operating speed. By appropriately combining these circuits according to design conditions, all desired operations can be performed. Furthermore, the BPT used in the present invention has excellent high frequency characteristics, and it goes without saying that it can be applied to various analog signal processing devices and applications.

[Embodiments of the invention]

Another example of a BPT structure in which the base region is almost pinched off leaving a thin potential barrier layer is shown in FIG.

The n ⁺ region 21 is an emitter, the p region 22 is a base,
p ⁺ area 23 is the base extraction area, n ⁺ area 25
is the collector, 25' is the collector extraction area, 2
1' is doped polysilicon, 26 is SiO ₂ ,
An insulating layer of Si ₃ N ₄ , AI ₂ O ₃ , P ₂ O ₅ , B ₂ O ₃ or a combination thereof, 27 is polysilicon or insulating resin for BPT insulation, 28, 29, 30 are metal electrodes . The impurity density of n ⁺ region 21 is 10 ¹⁸
~10 ²¹ cm ^-3 , 22 is 10 ¹² ~10 ¹⁶ cm ^-3 , 2
4 is about 10 ¹⁴ to 10 ¹⁷ cm ^-3 , 23 is about 10 ¹⁶ to 10 ²¹ cm ^-3 , and 25 is about 10 ¹⁷ to 10 ²⁰ cm ^-3 . Area 22
The thickness and impurity density of the layer are set so that the layer is almost or completely pinched off only by the diffusion potential with the regions of opposite conductivity type existing on both sides.

Of course, the BPT explained so far is not limited to these structures. It is sufficient if the base region is configured so that it is almost or completely pinched off in the main active region, leaving a thin potential barrier layer. Of course, it is also possible to use the conventional one with the conductivity type completely reversed.

The PBT and the semiconductor integrated circuit using the same are:
Conventionally well-known crystal growth technology, diffusion technology,
It can be manufactured using ion implantation technology, microfabrication technology, etc. Ion implantation technology is particularly effective when controlling the base region with high precision.

〔Effect of the invention〕

According to the present invention, since the BPT in which the base region is almost pinched off is used, the minority carrier accumulation effect is small and the interelectrode capacitance is small, so a large capacity high speed memory can be realized. According to the present invention, the state in which the carrier diffuses in the base region is not included, and the movement of the carrier is mostly due to drifting due to the electric field, and bulk conduction is used instead of surface conduction. The running time is short and high-speed read/write operations can be performed. According to the present invention, since the memory cells are configured three-dimensionally, high-density integration is possible.

[Brief explanation of the drawing]

FIG. 1a is a plan view of an SRAM memory cell using BPT in which the base region is almost in a pinch-off state.
FIG. 1b is a bird's eye view of the section X-X' in FIG. 1a. FIG. 2 is a diagram showing the circuit shown in FIG. 1, and FIG. 3 is a diagram showing another structural example related to the embodiment of the present invention. 3, 3', 31, 31', 21... Emitsuta,
5, 22... Base, 1, 25... Collector,
7, 8, 26, 27... Insulator, 9, 9', 9''...
...Polysilicon resistor, 10,10'...Wiring for power supply voltage application, 3''...Column line for address, 3''''',3
′′′′... Row line for writing and reading, 4, 41, 4
2, 23...Base extraction area, 6, 61, 6
2, 25'...Collector extraction area.

Claims (1)

[Claims] 1 First conductivity type high impurity density collector region 1,
25, first semiconductor regions 2, 24 formed on the upper part of the collector region, first conductivity type high impurity density collector extraction regions 6, 61, 62, 25' formed on the surface of the first semiconductor region; and emitter regions 3, 3', 31, 31', 21, second conductivity type high impurity density base extraction regions 4, 41, 42, 2 arranged to surround the emitter regions in a cylindrical shape.
3. Inside the first semiconductor region, a small number of base regions 5 and 22 of the second conductivity type are formed so that the base extraction region and the outer peripheral portion are in contact with each other, and the dimensions and impurity density of the base regions are opposite to each other. The first and second layers are almost pinched off only by the diffusion potential generated at the contact portion with the conductivity type region, forming a thin potential barrier layer.
bipolar transistors, the base lead-out regions and the collector lead-out regions of the first and second bipolar transistors are cross-coupled to each other, and the emitter regions of the first and second bipolar transistors are arranged in a row. line 3
A semiconductor integrated circuit characterized in that a structure connected to ``'', 3'''' and a column line 3'' is a basic memory cell.