JPS6044833B2 - Insulated gate static induction transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device and an integrated circuit using an insulated gate static induction transistor with sufficiently reduced gate capacitance.

Conventional field effect transistors, whether junction type, insulated, or gate type (MOS type, MIS type), exhibit saturated current/voltage characteristics in which the drain current gradually saturates as the drain voltage increases. . On the other hand, when the drain current increases and the drain voltage increases. Static induction field effect transistors (hereinafter referred to as SITs), which continue to increase in number, were proposed by the present inventor in Japanese Patent Application No. 1, Field Effect Transistor, No. 1, Field Effect Transistor, No. 1, No. 1, 28405, 1982, and No. 0, Field Effect Transistor, No. 1, No. 57, 768, 1982, by the present inventor. Ta.

SIT has the following characteristics compared to field effect transistors (hereinafter referred to as FETs).

1 In the main operating region, there remains a state in which there is no punch-through L between the source and drain, that is, a state in which there is no depletion state between the source and gate, a carrier injection state exists, and the product of the series resistance 5 and the conversion conductance Gm remains. By having an impurity density and various dimensions selected such that is less than 1, current/voltage characteristics exhibit unsaturated characteristics.

Since the current/voltage characteristics exhibit unsaturated characteristics, it can be used as a high input impedance, low output impedance element, and the apparent conversion conductance Gm can be increased and distortion can be reduced.

3. A large output current can be obtained, and by using a high-resistance layer in a predetermined region, the withstand voltage can be increased, and a large output device with a large current and a high withstand voltage can be obtained.

Since the gate region has a high impurity density and the gate shape can be made small, the interelectrode capacitance and gate resistance can be reduced, allowing for higher frequencies and higher speeds, and at the same time, the series resistance can be set small. This also makes higher frequencies and speeds even more advantageous.

j Over a very wide gate voltage range, and not only in the low current region where the channel is pinched off by the gate voltage alone and the current/voltage characteristics almost follow an exponential law, but also in the low current region where the series resistance R
Due to the effects of s and drain resistance Rd, the characteristics deviate from the exponential law, and the amplification coefficient can be adjusted over an extremely wide current range, including a large current region where the characteristics become almost linear. Able to perform operations with extremely low distortion, such as by keeping it almost constant.

3. Even when the current value is extremely small, since a large number of carriers are injected, there is almost no effect of surface recombination or recombination within the depletion layer, and the amplification coefficient can be kept almost constant.
Ability to perform extremely excellent switching operations under low current and low power consumption conditions.

7. Temperature characteristics in large current state can be made negative, so thermal runaway does not occur.

Also, it is possible to design a structure that has almost no temperature characteristics. 8
Over a very wide operating temperature range, e.g. 200°C
The amplification factor can be kept constant over the above period.

9 By narrowing the channel width and lowering the channel impurity density, a high-speed switching operation is achieved in which almost no current flows when the gate voltage is zero, and current only flows when forward voltage is applied to the gate. What you can do.

As mentioned above, SIT is superior in all aspects such as high power, high withstand voltage, large electric planer, low distortion, low noise, low power consumption, and high speed operation.Including its temperature characteristics, SIT is superior to conventional This transistor has many advantages over bipolar transistors and FETs.

Its excellence has already been demonstrated both as an individual element and as an element for integrated circuits, and it is opening up new fields of application in various fields. Because it has a high input impedance, it can be directly connected to the next stage, and since no drive power is required, the degree of integration can be increased.
Since it exhibits unsaturated current/voltage characteristics and has a large conversion conductance, it is extremely suitable for integrated circuits that can provide a large number of fan outs. The drain current 1d of SIT is equal to the gate voltage Vgl drain voltage Vd
In any case, in a low current state, it almost follows an exponential law, and as the current increases and the negative feedback effect by the series resistance begins to take effect, the exponential law is no longer followed.
The basic structure of an insulated gate (IG) static induction transistor that operates in enhancement mode (E mode) or enhancement mode and depletion mode (E/D mode) was developed by the inventor on January 11, 1932. Application, patent application 1972
-No. 1756 and patent application filed on February 1, 1973-
It has already been made clear in No. 13558.

In order to reduce the gate capacitance in IG-SIT, it is natural to either reduce the area of the gate electrode existing on the channel or increase the thickness of the insulating layer under the gate electrode. . If the insulating film is made thicker, the voltage applied to the gate (threshold voltage) necessary to create an inversion layer and make the channel conductive becomes higher, which is not desirable in terms of operating characteristics. The only remaining method is to make the gate electrode smaller. Cross-sectional views of examples of the structure of a conventional IG-SIT with a sufficiently small gate electrode are shown in FIGS. 1, 2, and 3 of an n-channel type. n+ in Figure 1a
The regions 51 and 54 are a source region and a drain region, respectively, and the impurity density is about 1017 to 1σ1 cm−3.

The p region 52 becomes a channel portion that controls the amount of electrons injected from the source to the drain side, and its impurity density is 1014 to 1018c!, depending on the channel length. T
It is about i-3. The impurity density in this region is selected so that there is no punch-through between the source and drain in the main operating region, that is, so that the entire region is not covered by a depletion layer extending from the drain. Also, its length is several 10
It is several μm from 0A. The p-region 53 is a low impurity density region, and has such dimensions and impurity density that the entire p-region becomes a depletion layer just by the diffusion potential with the drain region 54. For example, the impurity density is 1011 to 1017an-3
The longer the distance from the channel to the drain region, the lower the impurity density must be. 55 is
This is an insulating layer made of SiO2, Si3N4, Al2O3, etc., or a combination of a plurality of these.

5" and 54" are source and drain metal electrodes, respectively. Reference numeral 56 denotes a gate electrode, which may be made of a metal such as N, or may be made of a low resistivity semiconductor such as polysilicon.

However, if the channel becomes very short and the gate electrode becomes thin, the time constant determined by the gate electrode resistance and gate capacitance will limit the operating speed, so a metal electrode is preferable. Moreover, the thicker the metal, the lower the resistance, which is desirable. The thickness of the insulating layer under the gate electrode depends on the channel length and operation mode (E
It varies depending on the current mode (E/D mode or E/D mode), but it ranges from about 100A to about 1000A. When used for high voltage applications, it may be thicker. For the same channel length, the thickness of the insulating layer is slightly thicker when operating in E mode than when operating in E/D mode. When a positive voltage is applied to the gate electrode and the potential near the surface of the p-region in contact with the insulating layer is lowered, electrons are injected across this potential barrier into the p-layer, which has become a depletion layer, and an electric field is generated within the p-layer. Therefore, it drifts and flows into the drain region. Of course, the potential barrier is also controlled by the drain voltage. Therefore, in this structure, the flowing current is mostly determined by the amount of electrons injected into the drain side, so there is a negative feedback effect due to the series resistor 5 from the source to the potential barrier, and a negative feedback effect from the potential barrier to the drain. In the current region where the voltage effect of the drain resistance is not significant, the drain current increases with the gate voltage g.
For any one drain voltage Vd, the current flows almost according to an exponential law. If a sufficient positive voltage is applied to the gate and the p-region 53 is completely depleted by the drain voltage, a resistive current may flow. If the impurity density of the p-region, which becomes a channel, is distributed near the surface so that it gradually decreases from the surface to the inside, the inversion layer, which becomes a channel, becomes wider, the series resistance decreases, and the rise of the current becomes steeper. The same is true for the p-region on the drain side; if the impurity density decreases from the surface to the inside, the injected electrons will spread out and flow, reducing the drain resistance. Although the gate capacitance is sufficiently small in the structure shown in FIG. 1a, there is one more MOS, . S.I.
The source-to-substrate capacitance and the drain-to-substrate capacitance, which were major factors in reducing the operating speed of T, have hardly decreased. Of course, when using the source and substrate at the same potential, the capacitance between the source and the substrate does not affect the operation, and when the drain and the substrate are at the same potential, the capacitance between the lower lane and the substrate does not affect the operation. For example, in order to reduce the capacitance between the drain and the substrate, a structure as shown in FIG. 1b may be used.
That is, the p region 62 which should become a channel is formed only around the source region 61. The thickness is determined together with the impurity density so that punch-through between the source and drain does not occur, that is, the depletion layer does not completely reach the source from the drain, as in FIG. 3a. The n+ region 64 is a drain, and 66 is a gate electrode.
The impurity density etc. of each region are the same as in the case of FIG. 1a. Since the drain region 64 is in contact with the p-region, the depletion layer is sufficiently expanded, and the capacitance between the drain and the substrate can be made very small. In the structure shown in FIG. 1b, if the drain voltage changes rapidly, the change in the width of the depletion layer in the p layer cannot be followed, which causes power consumption. Therefore, when operating at a very high speed, a p region 67 is further provided below the p region as shown in FIG. 1c, so that the depletion layer from the drain region becomes p It suffices if the area 67 is reached. The impurity density of the p region 67 is 1015~
It is about 1σ0cm-3. FIG. 1d has a structure in which the source region is extended toward the drain side by ion implantation or the like. The impurity density and operation are almost the same as in FIG. 1b.
If the delay in the change in drain depletion layer width limits the operating speed as in Figure 1b, then p
Region 77 may be provided so that the depletion layer from the drain reaches p region 77 under most operating conditions.
In either structure, the impurity density and dimensions are selected so that a depletion layer is formed from the drain to the channel core with only the diffusion potential. FIG. 2 shows an example of the cross-sectional structure of a vertical IG-SIT in which the gate capacitance is sufficiently reduced by reducing the gate electrode area, taking an n-channel as an example.

FIG. 2 a'8n+ regions 81 and 84 are a source and a drain, respectively, a p region 82 is a region to become a channel, a p- region 83 is a region to be a vacant layer with only a diffusion potential, 8
5 is an insulating layer, and 86 is a gate electrode.

The impurity density etc. are the same as in the case of FIG. When an inversion layer begins to form due to the gate electrode, a drain current begins to flow.
In Fig. 2a, the gate-source capacitance tends to increase, but Fig. 2b shows an example in which this has been improved, except that the gate electrode is mostly limited to the p-region that becomes the channel. is the same as in Figure 2a. In FIG. 2c, there is an example in which the source is arranged on the substrate side. n+ area 101, 10
4 are the source and drain regions, and the p region 102 is the channel region, p? 103 is a region which becomes a depletion layer only by a diffusion potential, 105 is an insulating layer, and 106 is a gate electrode. FIG. 2 d is an example in which the character-shaped structure shown in FIG. 2 c is approximated to a U-shaped structure. The structure is the same as that in FIG. 2c except that the gate electrode 116 is divided into two parts. Of course, if the capacitance between the source and gate is allowed to be a little larger,
A gate electrode may be provided over the entire insulating layer 115 on the n+ region 111. In FIG. 2, when regions 82, 83, etc. are shortened for the purpose of high-speed operation by having the source and drain facing each other over a wide area, the source and drain
The drain-to-drain capacitance tends to increase and becomes a factor that limits high-speed operation.

To overcome this difficulty, it is necessary to
One of them may be made smaller. An example is shown in FIG. FIG. 3 shows a case where the source region is configured to be smaller than the example shown in FIGS. 2A and 2B.

In FIG. 3a, n+ regions 121 and 131 are sources, 124 is a drain, p regions 122 and 132 are regions that become channels, p- regions 123 are regions that become depletion layers only by diffusion potential, 125 is an insulating layer, 126, 136 are gate electrodes, 1
2" and 13" are the metal electrodes of the source, respectively.
Figure b is the same as Figure 3a, except that the letter-shaped cut reaches L up to n+ of the substrate. FIG. 3c shows an example in which the drain shown in FIG. 2c is formed in a small region 164. By configuring as shown in FIG. 3, the various capacitances can be kept sufficiently small and an IG-SIT capable of high-speed operation can be obtained. For the purpose of high power operation, p-
Just make it long to ensure sufficient pressure resistance. Also, at this time, it is okay to apply a certain amount of drain voltage so that the entire p- region becomes a depletion layer, so the length and impurity density are selected so that the entire p- region does not become a depletion layer with just the diffusion potential. You can leave it there. Further, in such a case, even if the gate electrode protrudes considerably over the p1 region, the capacitance will hardly increase because the p1 region eventually becomes a depletion layer in most operating conditions. Of course, when used for low-power, high-speed switches in integrated circuits, etc., it is often advantageous to have a full-area depletion layer because current flows with a small drain voltage. However, in order to apply a certain amount of drain voltage and cause the desired current to flow, the region that does not become a depletion layer with only the diffusion potential must be p
In some cases, it is designed to remain in one area. If the channel length is short, the insulating layer under the gate electrode is thin, and the dielectric constant is set high, most of the voltage applied to the gate will be applied to the semiconductor region that becomes the channel, so it will not exceed the potential barrier. The amount of carriers injected into the drain side is quite similar to that of a bipolar transistor. Since the mechanism by which the injected carriers flow to the drain is exactly the same as in the case of a bipolar transistor, it is possible to have a conversion conductance close to that of a bipolar transistor. Moreover, since the capacitance between each electrode (including between the electrodes and the substrate) can be sufficiently reduced, extremely high-speed operation can be performed. However, the conventional IG-
In all SITs, the region between the source and drain is a region of the opposite conductivity type to the source and drain regions, so unless a certain amount of drain voltage is applied, a potential barrier will not be created near the source; Figures 1 to 3
In the figure, the area near the P/P junction boundary becomes a virtual gate that provides a potential barrier, and the series resistance from the source to the virtual gate increases, resulting in insufficient current rise and small conversion conductance. have. SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks and to provide a MOS with a sufficient drain current rising from a small drain voltage region and a large conversion conductance. ．． MlS,. S
The purpose of the present invention is to provide IT and also to provide a semiconductor integrated circuit using this SIT.

In the conventional IG-SIT shown in FIGS. 1 to 3, a virtual gate that provides a potential barrier is created by changing the high resistance region provided on the drain side to a high resistance region of the same conductivity type as the drain. The position can be substantially fixed near the source region.

Examples of the cross-sectional structure of the IG-SIT of the present invention, which correspond to FIGS. 1 to 3, are shown in FIGS. 4 to 6, taking an n-channel case as an example. The impurity density and length of the high-resistance region inserted on the drain side are selected so that it becomes almost a depletion layer due to the diffusion potential difference with the region of the opposite conductivity type, which becomes the channel. SlO2, Si3N on the area that becomes the channel
4, Al. An insulating layer made of O3 or a combination thereof is set thin, and a gate electrode is provided thereon.
The thickness of the insulating layer is from several hundred amps to several thousand amps. In FIGS. 4C and 4E, the distance between the drain region and the p-region substrate is also set so that a depletion layer is formed in the main operating region. The height of the potential barrier created by the opposite conductivity type region in front of the source is controlled by the gate voltage and drain voltage via the insulating layer. The length of the channel region and the impurity density are such that as the drain voltage increases, the depletion layer region partially extends into the channel region and acts to lower the potential barrier in front of the source.
In addition, the channel region is selected such that the entire channel region does not become a depletion layer and punch-through with respect to the drain voltage of the main operating region. For example, if the semiconductor is silicon and the channel impurity density is 1 x 1013 cm-3, 1 x 10
14crfL-3, 1x1015CTT1-3, 1x1
0160-3, and the maximum value of the drain voltage is, for example, 1.
0, the length of each channel region is 12
μMl3.8μMll. 2μM,. O. It will be longer than 38 μm. It is also possible to create a distribution in the impurity density in the channel region such that the density decreases toward the drain, and to bring the virtual gate position where the potential barrier is closer to the front of the source j to sufficiently reduce the series resistance from the source to the virtual gate. to make the current rise more noticeable. The IG-SIT of the present invention having the structure shown in FIGS. 4 to 6 is different from the IG-SIT of the conventional structure shown in FIGS. It retains the features of SIT.

Since the gate electrode is provided only on the required channel and has a small area, the capacitance between the gate and the substrate and the capacitance between the gate and drain are extremely small.At the same time, the capacitance between the gate and the substrate is also small, making it extremely suitable for high-speed operation. It will be suitable.
In addition, the gate capacitance becomes very small, and the number of fan-outs that can be obtained from an inverter, logic gate, clock pulse generator, etc. with the same driving capability increases. In addition, if the voltage applied to the gate electrode is applied to the semiconductor in the channel part by making the insulating layer under the gate electrode thinner or increasing the dielectric constant, carriers injected from the source to the drain side can be reduced. Control of the amount by gate voltage is
It is close to a bipolar transistor, and the flow of carriers passing through the potential barrier in the channel part to the drain is exactly the same as that of a bipolar transistor, so the conversion conductance of the MOS, MIS, and SIT of the present invention is the same as that of a bipolar transistor. It is possible to set the value close to a very large value and increase the number of fan outs. 4 to 6 show some specific examples of the IG-SIT of the present invention.
Of course, the IT structure is not limited to this. Of course, it is also possible to use a conductivity type that is completely reversed.
With a vertical structure as shown in FIGS. and 6, it is easy to make it multi-channel. FIG. 7 shows the IG of the present invention.
An example of a cross-sectional structure of a complementary 1G-SIT using -SIT is shown.

FIG. 7a shows an equivalent circuit of a complementary 1G-SIT (C-1G-SIT) inverter, and FIG. 7b shows an example of its cross-sectional structure, which is based on the structure shown in FIG. 4b. 61-62
-63-64-66 constitute an n-channel IG-SITTl, and 6"-62"-642-66" constitute a p-channel IG-SITT2.

Of course, it goes without saying that the structure constituting the circuit of FIG. 7a is not limited to this. An example of a basic logic configuration based on a C-1G-SIT using the IG-SIT of the present invention that operates at low power and high speed is shown in FIG. 8 in the case of three inputs. Figure 8a shows a three-input NOR gate, and Figure 8b shows a three-input NOR gate.
It is AND. Compared to a CMOSFET structure using a MOSFET, the gate capacitance, drain capacitance, etc. are smaller, and the conversion conductance is larger, so the operating speed is faster and the power consumption is lower. Furthermore, since the next stage driving capacity is large, it also has the advantage of being able to obtain a large number of fan outs. It can also be easily connected directly to the next stage. NOR. with SIT in the normally on state as a load. An example of a NAND gate is shown in Figure 9A,
Figure b shows the case of two-person operation. Although power consumption is higher than that of the C-1G-SIT configuration, such a configuration can of course operate at high speed. The number of inputs in FIGS. 8 and 9 is not limited to what is shown in these drawings, and can be increased or decreased as desired. Alternatively, the conductivity types may be reversed. In addition, the IG-SIT of the present invention, which has a small electrode capacitance and a large conversion conductance, can be used to configure various logic circuits that operate at low power and high speed. An example is shown in FIG. Drive transistor (Tl,
n-channel junction type SIT for T2, T3...)
The p-channel IG-S of the present invention is used as the load transistor.
This is a circuit using IT.

The circuit is a combination of single-power, four-output inverters (basic circuit). FIG. 10b shows an example of the cross-sectional structure of the basic circuit portion. The driving SIT is of a surface wiring type.
If a notched gate is used, the gate capacitance can be further reduced, making it suitable for higher speed operation. In FIG. 10b, n+ area 171, n- area/area 172, n+ area 173, 173
″ The p+ region 174 is the source of the driving SIT,
It becomes a channel, drain, and gate, and the impurity density of each is 1017~1σ0C77! -3, 101
1~1016cTn-3, 1σ8~1 (Plcm-3,
1α5 to 1[α-3]. The p1 region 176 and the n region 177 are the source and channel of the 1G-SIT for load. P+ region 174 is also the drain of IG-SIT. In this example, the p-region between 177 and 174 is sufficiently depleted by the diffusion potential alone. Inverted SIT
The channel is also completely pinched off and in a cut-off state when the gate bias is zero. It becomes conductive only when a certain amount of forward bias is applied to the gate. Figure 10a
, a four-output inverter is depicted, and only two drains, 173 and 173'', are depicted in Figure 10b, but the remaining two drains are arranged perpendicular to the plane of the paper. 174 174″ as the metal electrode in Fig. 10b.
However, it is not necessarily necessary, as it can be provided if necessary from the layout of the entire integrated circuit.

175 is an insulating layer, and 178 is a gate electrode.

In the example shown in FIG. 10, the gate of the load IG-SIT is kept at the same potential as the drain, and when the gate of the drive SIT is kept at a high potential V2 (the preceding drive SIT is in a cut-off state), the IG-SIT -SIT gate potential is VSS-V2=V
4, the inversion layer is not sufficiently formed and no current flows. That is, no current flows through the gate of the driving SIT. The driving SIT in the conductive state is supplied with current from the next-stage load 1G-SIT. In other words, the drive SI in a conductive state
Since the drain potential of T is V1 (V1<2), the voltage between the source and drain of the load SIT (which is also the gate potential at the same time) becomes V3 = VSS - 1, which supplies the current h (1972 February (See 0 Semiconductor Devices and Semiconductor Integrated Circuits). In this embodiment, the gate of the IG-SIT is set to the same potential as the drain, but it is not necessarily limited to this, and may be kept at the same potential as the source.
A predetermined potential may be applied independently. In the structure shown in FIG. 10b, the source region of the load 1G-SIT is surrounded by a fairly dense layer of impurity of the opposite conductivity type.

Therefore, it has the characteristic that the difference in diffusion potential between both regions can be large. Since the configuration is such that a forward voltage is applied to the source region of the drive SIT and the source region of the load SIT, the source region of the load SIT is surrounded by high-density regions of opposite conductivity type, as in this example. The structure has the feature of suppressing unnecessary current flow. For load 1
This is an example of an integrated circuit in which the drain of the G-SIT and the gate of the driving junction type SIT are configured in a common area, and the degree of integration is extremely high.Of course, the structure is not limited to this. do not have. It may also be a combination of an n-channel IG-SIT and a p-channel junction type SIT whose conductivity types are completely reversed. The structure of the IG-SIT is not limited to that shown in FIG. 10, but may be any structure as shown in FIG. 4. p+
Regions 176 and 174 may reach n+ region 171. Furthermore, the structure of the inverted junction type SIT is not limited to this. The inventor of this application is Japanese Patent Application No. 51-143698 1
Field effect transistor and patent application No. 1982-4633
The structure may be similar to that proposed in the electrostatic induction transistor integrated circuit. Of course, it is also possible to use an IG-SIT integrated circuit for both the load and the drive. An example is shown in FIG. When local fluctuations occur in the current flowing through the power supply distribution line, which is inconvenient, Japanese Patent Application No. 52-4633 1 Static Induction Transistor Integrated Circuit
As stated in the application specification of Japanese Patent Application No. 52-1587 J Semiconductor Device and Semiconductor Integrated Circuit, the power supply distribution line and the drain are set at the same potential, and the source is configured to have the same potential as the source of the driving SIT. It is sufficient to arrange an SIT whose gate is directly connected to the gate of the driving SIT (FIG. 12).

Even when the IG-SIT of the present invention, which operates at low power and high speed, is used as a semiconductor memory device, its performance is further improved. FIG. 13 shows an example of a dynamic RAM memory cell using the IG-SIT of the present invention.

FIG. 13a shows a memory cell that uses one IG-SIT3O3 to store memory in a capacitor C3O4.

301 is a write/read address line (column line), 30
2 is a data line (row line) for writing and reading.

The writing and reading speeds are almost given by C/GITl, assuming the conversion conductance of IG-SIT. Since the IG-SIT (7) GrTl of the present invention can have a value quite close to that of a bipolar transistor, it can be used as a MOSFE.
Writing and reading can be performed at least one order of magnitude faster than the T memory cell. FIG. 13b shows a memory cell using three SITl3l5, 3l6, and 3l7 of the present invention, 311 and 312 are write and read address lines, and 313 and 314 are data read lines and write lines. In this circuit, since the memory is stored in the gate capacitance of the SIT 316, it is desirable that the gate capacitance of the SIT 316 is large. Also, since 316 does not affect the operating speed so much, Japanese Patent Application No. 1756-1987 7M0S,
Electrostatic induction field effect transistor. It may be a conventional MOS or MISSIT as shown in the specification, or it may be a MOSFE.
T-temyoi. FIG. 14a shows an example in which the IG-SIT of the present invention is applied to a static RAM memory cell.

321 is an address line, 322 is a data read line, 32
3 is a data write line, 324 to 329 are I of the present invention.
There is G-SIT.

In particular, 324, 325, 328, 3 that determines the operating speed
In SIT No. 29, each capacitance such as the gate capacitance is set to be small, and Gm is also set to be large. 3
26 and 327 are the SIT shown in Fig. 2, and the conventional MOSF
It may be ET.

With the configuration shown in FIG. 14a, it is possible to operate at a read/write speed of about one order of magnitude faster than that conventionally configured with MOS FETs. Of course, the circuit configuration of the RAM is not limited to these. Further, although the circuit is mainly constructed using an n-channel SIT, it goes without saying that a p-channel may also be used. FIG. 14b shows an example of a static RAM memory cell when the IG-SIT of the present invention is configured in a complementary type. Compared to the one in FIG. 14a, since it has a complementary configuration, power consumption is extremely low, and the culm sales rate is reduced. 331 is an address line, 332 is a data read line, 333 is a data write line, and 334 to 339 are IG-SITs of the present invention.

The SlT of the present invention can be used not only for such RAM but also for RO
It can be applied to M (ReadOnlyMemOry), programmable ROM1 shift registers, and nonvolatile memories equipped with floating gates.

The IG-SIT described above and the integrated circuit using it are:
All of these can be manufactured by conventionally known crystal techniques, diffusion techniques, ion implantation techniques, microfabrication techniques, selective diffusion, selective etching, selective growth, selective oxidation, and the like.

In the IG-SIT of the present invention, a gate electrode is formed via an insulating layer on a narrow semiconductor region that is to become a channel near the source, and the region from the channel to the drain is a high resistivity region and is a depletion layer. The carrier then drifts.

By configuring in this way, the gate capacitance can be made sufficiently small, the capacitance between the drain and the substrate can be made sufficiently small, and the current can rise sufficiently with a small drain voltage to increase the conversion conductance. Therefore, extremely low power and high Works at speed. Coupled with the fact that its manufacture is not so complicated, it brings about extremely significant performance improvements when applied to logic circuits and memory devices, and its industrial value is extremely large.

[Brief explanation of drawings]

Figures 1 a to e1, Figures 2 a to d, and Figures 3 a to c are examples of cross-sectional structures of conventional IG-SITs, Figures 4 a to e, Figures 5 a to d, and Figure 6 a. to c are IG-SITs of the present invention
Figures 7a and b are circuit examples and cross-sectional structures of complementary 1G-SIT, Figures 8a and b1 Figures 9a and b are examples of IG-SIT basic logic configuration, Figure 10a and b are an inverter that combines an IG-SIT and a junction type (inverted) SIT, Figures 11a and b are a circuit diagram and an example of a cross-sectional structure of an inverter that combines an IG-SIT, and Figure 12 is a power supply distribution line. An example of a circuit that keeps the current constant; FIGS. 13a and 13b are an example of a dynamic RAM memory cell configured with IG-SIT; FIG. 14a is an example of a static RAM memory cell using IG-SIT; Diagram b is complementary type 1
This is an example of a G-SIT static RAM memory cell.

Claims (1)

[Scope of Claims] 1. In an insulated gate transistor formed near the main surface of a semiconductor substrate, a source formed adjacent to the main surface of a first conductivity type having a high impurity density for supplying at least carriers. a drain region formed adjacent to the main surface of the first conductivity type having a high impurity density for recovering carriers; a drain region of the first conductivity type having a lower impurity density than the drain region; an auxiliary drain region located away from the source region and adjacent to the drain region, a portion of which reaches the main surface; a gate consisting of a channel region of a second conductivity type opposite to the first conductivity type in density, an insulating layer formed on the channel region, and a conductive gate electrode formed on the insulating layer, The height of the potential barrier of the channel region is controlled according to the gate voltage applied to the gate and the drain voltage applied to the drain region, thereby exhibiting unsaturated current-voltage characteristics. An insulated gate type static induction transistor featuring: 2. In the insulated gate static induction transistor according to claim 1, the semiconductor substrate is of a second conductivity type, and the channel region and the semiconductor substrate are a common region,
An insulated gate static induction transistor characterized in that the auxiliary drain region extends from the adjacent drain region along the main surface to the source region. 3. In the insulated gate static induction transistor according to claim 1, the semiconductor substrate is of the first conductivity type, the auxiliary drain region and the semiconductor substrate are shared regions, and the channel region is at least the source region. An insulated gate static induction transistor characterized by being formed so as to surround a part of the transistor. 4. In the insulated gate static induction transistor according to claim 1, the semiconductor substrate is of the second conductivity type, and a first region of the first conductivity type and low impurity density is formed on the semiconductor substrate. , the insulated gate static induction transistor is formed in the first region, the first region and the auxiliary drain region are shared regions, and the channel region is formed to surround at least a part of the source region. An insulated gate static induction transistor characterized by: 5. The insulated gate static induction transistor according to claim 3 or 4, characterized in that a portion of the source region extends toward the drain region along the main surface. Insulated gate static induction transistor. 6 In an insulated gate transistor formed on a semiconductor substrate having a main surface, at least a source region of a first conductivity type with high impurity density for supplying carriers and a drain region with high impurity density for recovering carriers. , a channel region of a second conductivity type opposite to the first conductivity type, which is located between the source region and the drain region, and at least a part of which is formed in contact with a part of the source region; an auxiliary drain region having the first conductivity type and lower impurity density than the drain region; Each region is formed in a direction perpendicular to the main surface, with at least a portion of each region overlapping each other, and a groove of a predetermined shape is formed from the main surface, and the channel region is at least partially a groove portion. The gate includes an insulating layer formed on at least the channel region and a conductive gate electrode formed on the insulating layer, and a gate voltage applied to the gate and a gate voltage applied to the drain region. 1. An insulated gate static induction transistor, characterized in that the height of the potential barrier in the channel region is controlled according to the drain voltage, thereby exhibiting unsaturated current-voltage characteristics.