JPS6329419B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a novel structure of a bipolar mode static induction transistor, and particularly to a structure that can shorten the channel length and can be easily configured as a normally-off type transistor.

Traditional field effect transistors are junction type, MIS
In either type, the drain current exhibits saturation type current-voltage characteristics where the drain current gradually saturates as the drain voltage increases.

On the other hand, a static induction field effect transistor (hereinafter referred to as SIT), whose drain current continues to increase as the drain voltage increases, was invented (Patent No. 968336 (Special Publication No. 52-6076), ``Field Effect Transistor'',
Patent No. 968337 (Special Publication No. 52-17720) "Field Effect Transistor"), SIT is a field effect transistor (hereinafter referred to as FET) that has high power, high withstand voltage, large current, low distortion, low noise, and low power consumption. It is excellent in all aspects such as high-speed operation, and has many advantages over conventional bipolar transistors and field effect transistors, including its temperature characteristics. Its excellence as an individual element and as an element for integrated circuits has already been demonstrated, and it is opening up new fields of application in various fields.

SIT has a high input impedance, so it can be directly connected to the next stage, and does not require driving power.It has a low output impedance and low noise, so the logic voltage amplitude can be made very small, so the power consumption is sufficient. It can be made small and the degree of integration can be extremely high. Furthermore, since the conversion conductance is large, the driving capacity of the next stage is large, and a large number of fanouts can be obtained.Since the channel is in a high resistance region, the capacitance between each electrode is small, and there is almost no minority carrier accumulation effect. SIT is particularly suitable for use in integrated circuits because it has characteristics such as high-speed operation due to the absence of a SIT is also possible with junction gate, MOS
It is well known that this is possible with type gates (Japanese Patent Laid-Open No. 1973-
(Refer to Publication No. 24682). Normally-off type SIT, in which no current flows when no bias is applied to the gate, is suitable for constructing logic gates. By narrowing the channel width W _G and lowering the impurity density of the channel, normally-off type SIT enables high-speed switching operation in which current flows only when forward voltage is applied to the gate, and bipolar mode. Also called SIT. However, in bipolar mode SIT using a pn junction, a small number of minority carriers are injected when the gate is forward biased, and this accumulation effect of minority carriers makes high-speed operation difficult. To overcome this drawback, bipolar mode SIT using MOS gates can realize SIT with no minority carriers and a true electrostatic induction effect. An example of this is shown in Figure 1. In order to operate at higher speed, it is sufficient to shorten the source-drain distance _lSD , and the vertical structure MOS-SIT shown in FIG. 1 is suitable for this purpose. In FIG. 1, n ⁺ regions 11 and 13 are source and drain regions, respectively.
The p region 32 is a channel region, 11' and 15 are a source electrode and a gate electrode, respectively, and 16 is an insulating film. For ultra-high speed switching on the order of picoseconds, the source-drain distance _lSD must be approximately 0.1 micron, but in order to achieve normally-off, the impurity density in the p region must be increased, and the source It is necessary to prevent punch-through between the drains when no drain voltage is applied. When the aforementioned l _SD is about 0.1 micron, the impurity density in the p region needs to be about 1×10 ¹⁸ cm ^-3 , but the Debye length L _D in this case is 0.004 micron. MOS−
There are two types of SIT: a surface channel type in which the carrier flows on the surface, and an internal channel type in which the carrier flows in the bulk.However, since the mobility of the carrier is small on the surface, the internal channel type is better for high-speed operation, but in this case, the The W _G shown in Figure 1 is required to be approximately 2L _D , or approximately 0.01 micron. This dimension is not achievable with current lithographic techniques. By adopting a vertical structure, _LSD can be easily shortened by ion implantation or epitaxial growth, whereas _WG , which is a planar dimension, is extremely difficult to shorten to submicron dimensions due to lithography constraints. be. In other words, even in the case of a vertical structure, there are constraints on planar lithography in order to shorten the channel, just as in the case of a horizontal structure.

A bipolar transistor whose base region is almost punch-through operates almost the same as SIT (Patent No. 1217657 (Special Publication No. 58-53517))
"Semiconductor integrated circuit", Patent No. 1060320 (Special Publication No. 1987)
-50420) "Semiconductor integrated circuit").

In Figure 2, n ⁺ regions 1 and 3 form the source and drain, n ^- region 2 forms a channel, and p region 6
4 is a buried region with a protrusion in part, 4 is a gate electrode, 1' and 3' are source and drain ohmic electrodes, respectively, and 5 is an insulating layer such as SiO ₂ , Si ₃ N ₄ and Al ₂ O ₃ or these. It is a composite insulating layer that combines multiple layers. The impurity density of each region is about 10 ¹⁸ to 10 ²¹ cm ^-3 for n ⁺ region and 10 ¹¹ for n ^- region, respectively.
-10 ¹⁶ cm ^-3 or so, p region: about 10 ¹⁵ - 10 ²⁰ cm ^-3 or so. The gate electrode 4 is made of metal such as Al or Mo, or low resistance polysilicon.

A potential barrier in front of the source is formed and controlled by the p-region 6 having a protrusion and the MIS gate electrode 4. The p region 6 is made by being embedded in the n region,
The buried region may be only the portion corresponding to the MIS gate. The potential of the buried region is floating.

FIG. 2 is an example of a bipolar structure with a thin p ^- base region across the channel between the p-region 6 and the MIS gate. p ^-region 2' is source n ⁺
It is separated from area 1. The p ^- base region 2' is almost pinched off and punched through by the diffusion potential alone. Although the p-substrate protrusion is shown separated from the source n ⁺ region in FIG. 2, it may be in almost or complete contact with the source n+ region. However, the structure of FIG. 2 is not easy to manufacture due to limitations of planar lithography.

An object of the present invention is to provide a bipolar mode SIT with a new structure that allows the channel length to be easily shortened.

The present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an example of a vertical structure in which p ^- base region 12' and a part of the channel are surrounded by p ⁺ region 14, and the remaining part is surrounded by MIS gate electrode 15. 35 is a gate insulating film. 1
1, 12, 13, 14, 14', 15, and 16 are a source, a channel, a drain, a first gate region, a first gate electrode, a second gate electrode, and an insulating layer, respectively, and are connected to the n ⁺ region 11 ^. A potential barrier is formed in the p ^- base region 12' which is almost depleted by the diffusion potential of the p ^- junction. The impurity density in each region is almost the same as in FIG. Third
Figure 4 shows an example in which a gate is provided in the cut portion, and the p ^- base region and channel are p ⁺
It is surrounded by the region 14 or 24 and the MIS gate electrode 15 or 25. 11' is a source electrode, and 13' is a drain electrode. Figure 4 shows n ⁺
This is an example of an inverted SIT in which the substrate 21 is the source and the n ⁺ region 23 is the drain. 22 and 26 are n ^- channel regions and insulating layers, and 45 is a gate insulating film. 21' is a source electrode, and 23' is a drain electrode. In order to reduce the series resistance r _S and increase the conversion conductance without increasing the capacitance between the source and the gate, a protrusion may be provided on the source (Patent No. 1083882 (Japanese Patent Publication No. 56-26148), "Field Effect "transistor"). To explain this as an example of the structure of a bipolar transistor in which a thin base layer is almost or completely punched through only by the diffusion potential, in FIG. 3, the n ⁺ region 11 corresponds to the emitter and 13 corresponds to the collector. In FIG. 4, the n ⁺ region 21 corresponds to the emitter, and 23 corresponds to the collector. The potential barrier created in the p ^- base region is connected to the p ⁺ gate region and the MIS
Controlled by gate electrode. The difference from bipolar transistors is that the potential barrier is not controlled by flowing current through the base, but by capacitive coupling. In FIGS. 3 and 4, W _G ′ corresponding to the channel width W _G in FIG. 1 can be controlled by the lateral diffusion depth of the p ⁺ regions 14 and 24, and is approximately 0.1 micron or less. dimensions can be easily realized. Since the channel width can be narrowed without being subject to the constraints of planar lithography, l _SD , that is, the channel length can also be easily shortened, and W _G ′<
l Since it can be used as _SD , it is a suitable structure for shortening channels. Although FIGS. 3 and 4 show only an example of an n-channel, a p-channel whose conductivity type is completely reversed operates in the same manner. Further, the structure is not limited to this example, and various modified structures are possible.

The transistors mentioned above are in bipolar mode
While retaining the advantages of bipolar transistors that only require SIT or punch-through, it has the advantage of being easy to shorten the channel and preventing excessive minority carrier injection from the gate. That is, conventional bipolar transistors and bipolar mode SITs have a G _n that is more than 10 times higher than MIS type FETs and MIS type SITs, but they have the drawback of injection of minority carriers. On the other hand, MIS type FET and MIS type SIT
is a bipolar transistor or bipolar mode
Although G _n is smaller than SIT, it has the advantage of not having the accumulation effect due to minority carrier injection. The present invention combines the advantages of both, eliminates the accumulation of minority carriers, and realizes a high G _n transistor. That is,
By setting the gate voltage of bipolar mode SIT or the base voltage of a bipolar transistor that can only punch through below the on-voltage of the pn junction near zero potential, and controlling the gate potential or base potential with the MIS gate, the minority carrier can be reduced. This means that high G _n transistors can be realized without implantation. The junction gate side may be floating. Therefore, use of these transistors in integrated circuit devices is effective in realizing low power and high speed operation. Bipolar mode has been proposed so far for integrated circuit devices.
It can be applied to logic circuit devices, memory devices, etc. that include bipolar transistors that can only perform SIT or punch-through.

The semiconductor device of the present invention can be produced using conventionally known crystal growth techniques (selective growth), diffusion techniques (selective diffusion), etching techniques (chemical and dry, selective etching),
It can be manufactured using microfabrication technology, ion implantation technology, etc.

The bipolar mode SIT of the present invention, which has a junction type and an MIS gate on the same channel, can easily be made into a short channel with a source-drain distance of 0.5 microns or less, has a small interelectrode capacitance, has a large conversion conductance, and has a minority carrier accumulation effect. This makes the features of SIT, such as small size, more prominent and facilitates integrated circuit configuration. Also, from the perspective of MIS gate SIT, it is possible to operate the MIS gate in forward bias and the junction gate in reverse bias.
Unlike gate SIT or MIS gate FETs, the impurity density in the channel does not have to be high, and it can be made normally off by biasing the pn junction gate. Therefore, the impurity density in the channel can remain low;
As a result, the mobility is large and higher speed operation is possible. This effect is particularly effective for short channel MIS gate SIT with submicron length or less. A cut is made from the surface and a gate is formed in the cut, so there are no opposing electrodes.
The interelectrode capacitance is greatly reduced. In particular, when manufacturing MIS gate transistors with a channel length of 1 micron or less using this cut gate structure, the first
The gate spacing W _G illustrated in the figure needs to be 0.7 microns or less, which is comparable to the wavelength of light, but it is extremely difficult to control such a dimension using current photolithography technology. In the claimed invention
By controlling the diffusion depth of the p ⁺ diffusion layer 14, dimensions of 0.7 microns or less can be easily achieved without being constrained by photolithography technology, and gate spacing of 0.1
Sub-micron dimensions are also possible. That is, the present invention facilitates the manufacture of short channel transistors with a three-dimensional structure, is suitable for ultra-high frequency operation and integration, and has great industrial significance.

[Brief explanation of the drawing]

Figure 1 shows a conventional MOS-SIT with a vertical structure;
The diagrams are reference diagrams of horizontal structure SIT, Figures 3 and 4.
The figure is a cross-sectional view of a transistor according to an embodiment of the present invention.

Claims (1)

[Claims] 1. Drain region 13 of first conductivity type with high impurity density.
and a first conductivity type low impurity density channel region 12 formed above the drain region and having a convex portion on a part of the surface opposite to the drain region.
and a base region 1 of a second conductivity type formed to extend the convex portion above the channel region.
2', and a first
a source region 11 of high impurity density of conductivity type; and a first gate region 14 of high impurity density of second conductivity type formed on the side wall of the convex portion adjacent to the base region.
and a gate insulating film 35 formed on a side wall of the base region facing the first gate region, and a drain formed adjacent to the drain region, the source region, the first gate region, and the gate insulating film, respectively. It is composed of an electrode 13', a source electrode 11', a first gate electrode 14', and a second gate electrode 15, and the base region is formed by the regions above and below it.
Due to the depletion layer due to the diffusion potential of the p-n junction, the potential barrier is almost punched through to the extent that a very small amount remains in the base region, and the voltage applied to the second gate electrode and the voltage applied to the drain electrode are Therefore, by changing the height of the potential barrier through capacitive coupling, the current flowing between the source region and the drain region is controlled, and the current flowing between the first gate region and the gate insulating film is controlled. The distance W _G ' is shorter than the distance between the drain region and the source region, and the voltage applied to the first gate electrode is fixed at approximately zero potential below the rising voltage of the pn junction, or the voltage applied to the first gate electrode is A semiconductor device characterized by having a floating region and exhibiting unsaturated drain current characteristics shown by an exponential law with respect to both gate voltage and drain voltage. 2 First conductivity type high impurity density source region 21
a base region 22' of a second conductivity type disposed adjacent to the source region so as to form a convex portion on a part of the surface of the source region; a first conductivity type low impurity density channel region 22 formed on the channel region, a first conductivity type high impurity density drain region 23 formed above the channel region, and adjacent to the base region;
A first gate region 24 of a second conductivity type with high impurity density formed on a part of the side wall of the convex portion, and a first gate region 24 of the second conductivity type formed on a portion of the side wall of the convex portion at a position opposite to the first gate region. A source electrode 21', a drain electrode 23', a first gate electrode 24', and a second gate are formed adjacent to the gate insulating film 45, the source region, the drain region, the first gate region, and the gate insulating film, respectively. The base region is formed by the upper and lower regions of the base region.
Due to the depletion layer due to the diffusion potential of the p-n junction, the potential barrier is almost punched through to the extent that a very small amount remains in the base region, and the voltage applied to the second gate electrode and the voltage applied to the drain electrode are Therefore, by changing the height of the potential barrier through capacitive coupling, the current flowing between the source region and the drain region is controlled, and the current flowing between the first gate region and the gate insulating film is controlled. The distance W _G ' between the drain region and the source region is shorter than the distance between the drain region and the source region, and the voltage applied to the first gate electrode is fixed at approximately zero potential below the diffusion potential of the pn junction or the first 1. A semiconductor device characterized by having a floating gate region and exhibiting unsaturated drain current characteristics shown by an exponential law with respect to gate voltage and drain voltage.