JP2011124268A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device with a structure that facilitates manufacture, does not raise a voltage between a source and a drain, and has stable current characteristics to reduce an S value for a FET. <P>SOLUTION: The device includes a channel layer 101 formed in a semiconductor layer 100, a first gate electrode 103 formed on the channel layer 101, and a source 104 and a drain 105 disposed in the semiconductor layer 100 with the channel layer 101 therebetween. The semiconductor device also includes a second gate electrode 109 formed on the channel layer 101 between the first gate electrode 103 and the source 104, the second gate electrode 109 being insulated from the first gate electrode 103, and a third gate electrode 111 formed on the channel layer 101 between the first gate electrode 103 and the drain 105, the third gate electrode 111 being insulated from the first gate electrode 103. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device that realizes steep on / off current characteristics at a low voltage.

  Transistors are used as switching elements in computers and various electronic devices. For example, field effect transistors (FETs) are widely used in general. As shown in FIG. 6A, this FET includes, for example, a gate electrode 603 formed on a silicon substrate 601 through an insulating layer 602, and a source 604 and a drain 605 formed on the silicon substrate 601 so as to sandwich the gate electrode 603 therebetween. It is configured. The source 604 and the drain 605 are formed by introducing so-called impurities.

This FET controls the kind of impurities used for the source 604 and the drain 605, the voltage applied to the gate electrode 603, and the voltage applied between the source and drain to control holes or electrons from the source 604 to the drain 605. It becomes possible to flow. Such an FET has a characteristic of a current (I) between a source and a drain with respect to a gate voltage (V _g ) as shown in FIG. 6B.

Usually, when an FET is used as a switching element, a gate voltage (on voltage V _on ) at which a sufficient source-drain current (on current I _on ) can be obtained, and a source-drain current (off current) having a small current value. used as I _off) to become a gate voltage (oFF voltage V _off) and a binary signal. Therefore, in order to realize a normal switching operation, it is important to obtain a sufficiently large on-current I _on and on / off ratio (I _on / I _off ). On the other hand, it is desired that the difference between the on voltage V _on and the off voltage V _off is small from the viewpoint of reducing power consumption.

In order to realize these, generally, the off-voltage V _off is set in a saturation region where the source-drain current changes nonlinearly with respect to the gate voltage, and the on-voltage V _on is set in a linear region where the current changes linearly. It is set. As a further improvement, it is also desired to increase log (I) / V _g in the saturation region. Reciprocal of the log (I) / V _g is the subthreshold swing value (subthreshold swing value: S value) is represented, it has been used as an indication of important performance of the FET (characteristics). At present, attempts have been made to reduce the S value due to the structure of the FET. However, the minimum value of the S value is determined by temperature. I can't.

  On the other hand, a new FET having an S value of 60 mV / dec or less has been reported. As an example of this, there is a metal oxide semiconductor (MOS) using an impact ionization phenomenon (see Non-Patent Document 1). As shown in FIG. 7A, the MOS using the impact ionization phenomenon includes a gate electrode 703 formed via an insulating layer 702, and a source 704 and a drain 705 arranged so as to sandwich the gate electrode 703. Is a p-type region, drain 705 is an n-type region, and source 704 is formed away from gate electrode 703.

  In this MOS, when a positive bias is simply applied to the drain 705, a pn junction diode is reversely biased as shown in FIG. 7A, so no current flows. However, in this state, if a gate voltage is applied to the gate electrode 703 to invert the semiconductor region immediately below the gate electrode 703, carriers are injected into the semiconductor region immediately below as shown in FIG. The electric potential between the end of the formed inversion region (pinch-off point) and the end of the source 704 is increased.

  As a result, minority carriers accelerated in a high electric field region have high energy and form electron-hole pairs. When this phenomenon occurs in an avalanche manner, as shown in FIG. 7A (b), electrons (white circles) and holes (black circles) are generated abruptly, and the electrons flow into the drain 705 which is the n region. Flows into the source 704 which is the p region. As a result, a source / drain current is generated.

In the MOS (impact ionization MOS) using the impact ionization phenomenon described above, carriers generated in an avalanche type are used, and therefore, as shown in FIG. Is obtained, and an S value smaller than 60 mV / dec can be obtained. Therefore, in the impact ionization MOS, even if the difference between V _on and V _off is reduced, a large I _on / I _off can be secured, and low power consumption and high speed operation can be expected. For this reason, impact ionization MOS is attracting attention as a high-performance device.

K. Gopalakrishnan, et al, "Impact Ionization MOS (I-MOS). Part I: Device and Circuit Simulations", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.52, no.1, pp.69-76, 2005. William M. Reddick and Gehan A. J. Amaratunga, "Silicon surface tunnel transistor", Appl. Phys. Lett., Vol.67, no.4, pp.494-496, 1995. N. Abele1, et al., "Suspended-Gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor", International Electron Devices Meeting Technical Digest, pp.479-481, 2005. K. Nishiguchi, et al., "Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node", IEEE ELECTRON DEVICE LETTERS, vol.28, no.1, pp.48-50, 2007.

  However, the impact ionization MOS described above has the following problems.

  First, the impact ionization MOS has a problem in that a large source-drain voltage is required to give carriers sufficient energy to form an electron-hole pair. As a general report, the above-described source-drain voltage requires 5 V or more. Since the power consumption is determined by the source-drain voltage, a large source-drain voltage hinders low power consumption.

Further, in the impact ionization MOS, the point that hysteresis appears in the current-gate voltage characteristic is raised as a problem. In the impact ionization MOS, as shown in FIG. 7C, the current-gate voltage characteristic (solid line) in the on state is different from the current-gate voltage characteristic (dotted line) in the off state. This is because the impact ionized MOS cannot remove the avalanche-increased carriers when it is switched from the off state to the on state and then back to the off state. In the impact ionization MOS, minority carriers flow as current even in the off state, and therefore the off current I _off tends to be larger than that of a normal FET. These are inherently difficult to solve.

  There is also a difficulty in production. In the impact ionization MOS, the source and drain have different conductivity types, and the source is formed away from the gate electrode. Thus, different impurities are introduced at the source and the drain, and forming a gap between the gate electrode and the source has a problem that the manufacturing method is complicated as compared with a normal FET. .

  In addition to the above-described impact ionization MOS, a new FET with a smaller S value has been proposed. For example, there are a tunnel FET (see Non-Patent Document 2) and a bridged gate FET (see Non-Patent Document 3). However, these FETs also have problems such as a high drain-source voltage, a complicated element structure, and hysteresis in current characteristics.

  The present invention has been made to solve the above-described problems, and has a structure that is easy to manufacture, reduces the S value of the FET with stable current characteristics, without increasing the source-drain voltage. The purpose is to do.

  A semiconductor device according to the present invention is formed on a channel layer formed in a semiconductor layer, a source and a drain formed in the semiconductor layer with the channel layer interposed therebetween, and spaced from the position of the source and drain A first gate electrode, a second gate electrode formed on the channel layer between the first gate electrode and the source so as to be insulated from the first gate electrode, and a channel between the first gate electrode and the drain A third gate electrode formed on the layer so as to be insulated from the first gate electrode, and a fourth gate disposed opposite to the first gate electrode, the second gate electrode, and the third gate electrode with the channel layer interposed therebetween And at least an electrode.

  In the semiconductor device, the second gate electrode and the third gate electrode may be equipotential. In addition, the source and the drain may be regions where impurities are introduced into the semiconductor layer.

  In the semiconductor device, two storage layers in which carriers are induced in each of the channel layers at the positions of the second gate electrode and the third gate electrode by applying voltages to the second gate electrode and the third gate electrode, respectively. In a state where two storage layers are formed, a gate voltage is applied to the first gate electrode, whereby an inversion layer is formed in the channel layer between the two storage layers, and the two storage layers Are connected by an inversion layer, and a current can flow between the source and the drain.

  In the semiconductor device, when a gate voltage is applied to the first gate electrode in a state where two storage layers are formed, a voltage having the same polarity as the gate voltage is applied to the fourth gate electrode. May be. Further, when a gate voltage is applied to the first gate electrode in a state where two storage layers are formed, a voltage having a polarity different from the gate voltage may be applied to the fourth gate electrode. .

  As described above, according to the present invention, the second gate electrode formed on the channel layer between the first gate electrode and the source and insulated from the first gate electrode, and the first gate electrode and the drain Since the third gate electrode formed on the channel layer between the first gate electrode and the first gate electrode is isolated, the structure is easy to manufacture and stable without increasing the source-drain voltage. With the current characteristic, an excellent effect that the S value of the FET can be reduced is obtained.

It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is a top view which shows the partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. 1 is a circuit diagram showing an equivalent circuit of a semiconductor device in a first embodiment of the present invention. It is a characteristic view which shows the characteristic of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 2 of this invention. FIG. 11 is a cross-sectional view illustrating a structure of a field effect transistor. FIG. 11 is a characteristic diagram illustrating characteristics of a field effect transistor. It is sectional drawing which shows the structure of impact ionization MOS. It is a characteristic view which shows the characteristic of impact ionization MOS. It is a characteristic view which shows the characteristic of impact ionization MOS.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described. As shown in FIGS. 1A to 1C, the semiconductor device according to the first embodiment includes a channel layer 101 formed in the semiconductor layer 100, a first gate electrode 103 formed on the channel layer 101, and a channel. A source 104 and a drain 105 formed in the semiconductor layer 100 are provided with the layer 101 interposed therebetween. The first gate electrode 103 is formed on the channel layer 101 with the insulating layer 102 interposed therebetween, and is formed on the channel layer 101 at a distance from the positions of the source 104 and the drain 105. 1A shows a cross section taken along line aa ′ of the plan view of FIG. 1B, and FIG. 1C shows a cross section of line cc ′ of the plan view of FIG. 1B.

  In addition, the semiconductor device in this embodiment includes a first gate electrode 109 formed on the channel layer 101 between the first gate electrode 103 and the source 104 so as to be insulated from the first gate electrode 103, and a first gate electrode 109. A third gate electrode 111 is provided on the channel layer 101 between the gate electrode 103 and the drain 105 and formed by being isolated from the first gate electrode 103. In addition, a fourth gate electrode 107 disposed to face the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111 with the channel layer 101 interposed therebetween is provided. The second gate electrode 109 is insulated from the first gate electrode 103 by the insulating layer 108, and the third gate electrode 111 is insulated from the first gate electrode 103 by the insulating layer 110. An insulating layer 106 is formed between the fourth gate electrode 107 and the channel layer 101.

  For example, the semiconductor device in this embodiment can be manufactured by using a well-known SOI (Silicon on Insulator) substrate. In this case, the silicon base portion of the SOI substrate becomes the fourth gate electrode 107, the buried insulating layer becomes the insulating layer 106, and the surface silicon layer becomes the semiconductor layer 100.

  The manufacturing method will be briefly described. First, the surface silicon layer of the SOI substrate is patterned by a known photolithography technique and etching technique to form a stripe-like semiconductor layer 100 having a width of about 50 nm and a height (thickness) of about 30 nm. Form. A channel layer 101, a source 104, and a drain 105 are formed in the semiconductor layer 100.

  Next, an insulating layer (insulating layer 102) covering the formed semiconductor layer 100 is formed, and a polysilicon layer is formed on the insulating layer. These may be formed by depositing each material by a well-known CVD method or sputtering method. Next, the formed polysilicon layer is patterned by a known photolithography technique and etching technique to form the first gate electrode 103. The first gate electrode 103 is formed so as to extend in a direction orthogonal to the extending direction of the semiconductor layer 100.

  Next, an insulating layer covering the first gate electrode 103 is formed. For example, the insulating layer can be formed by thermally oxidizing the surface of the first gate electrode 103. This insulating layer becomes the insulating layer 108 and the insulating layer 110.

  Next, a polysilicon layer is formed on the first gate electrode 103 so as to cover the first gate electrode 103 on which the insulating layer is formed, and this polysilicon layer is formed by a known photolithography technique and etching technique. To pattern. In this patterning, a polysilicon pattern having a width corresponding to a region where the channel layer 101 is to be formed is formed in the direction in which the semiconductor layer 100 extends.

  Next, the polysilicon pattern is etched back to expose the upper surface of the first gate electrode 103 where the insulating layer is formed, and the second gate electrode 109 and the third gate electrode are formed on both sides of the first gate electrode 103. 111 is formed. For example, etching back may be performed using a well-known CMP method.

  Next, using the second gate electrode 109, the third gate electrode 111, and the first gate electrode 103 formed as described above as a mask, the insulating layer formed over the semiconductor layer 100 is selectively used. Etch. By this etching, the insulating layer 102 described above is formed, the channel layer 101 is formed in the semiconductor layer 100 in the region covered with the insulating layer 102, and the regions to be the source 104 and the drain 105 of the semiconductor layer 100 are exposed. .

  Next, an impurity is introduced into the above-described exposed portion of the semiconductor layer 100 by, for example, a well-known ion implantation method to form, for example, an n-type, thereby forming the source 104 and the drain 105 sandwiching the channel layer 101. . Thus, the semiconductor layer 100, the channel layer 101, the first gate electrode 103, the source 104, the drain 105, the second gate electrode 109, the third gate electrode 111, and the fourth gate electrode 107 are formed.

  Thereafter, although not shown in FIGS. 1A to 1C, an interlayer insulating layer covering the second gate electrode 109, the third gate electrode 111, the first gate electrode 103, and the like is formed, and the interlayer insulating layer is contacted By forming holes, source electrode wirings and drain electrode wirings connected to the source 104 and the drain 105 are formed. Further, in the same manner, a gate electrode wiring connected to each of the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111 may be formed.

  Here, an example is shown about the design dimension of each part. The insulating layer 102, the insulating layer 106, the insulating layer 108, and the insulating layer 110 are preferably as thin as possible so that dielectric breakdown does not occur at the voltage when driving the FET. For example, these layer thicknesses may be about 10 nm when the driving voltage (gate voltage, etc.) is 10V. If the drive voltage is lowered, the layer thickness can be reduced in proportion to this. In addition, regarding the insulating layer 102, the insulating layer 108, and the insulating layer 110, it is desirable that current does not flow from the respective gate electrodes in contact with the insulating layer 102 to the channel layer 101, and 5 nm or more is required.

  The channel layer 101 may have a thickness of about 20 to 40 nm. Moreover, the width | variety (length of the paper surface up-down direction of FIG. 1B) should just be about 20-100 nm. Further, the height (layer thickness) of the first gate electrode 103 may be about 50 nm, and the width (the length in the horizontal direction of FIG. 1B) may be 10 nm or more. The second gate electrode 109 and the third gate electrode 111 may have a height of about 50 nm. The second gate electrode 109 and the third gate electrode 111 only need to be within the width of the channel layer 101.

Next, the impurity concentration in each gate electrode and the source 104 and drain 105 will be described. In the case where each gate electrode is made of silicon, a donor such as phosphorus may be introduced as an impurity to show a metallic characteristic. The same applies to the source 104 and the drain 105. For this purpose, for example, there is no problem if the concentration of introduced phosphorus is about 10 ¹⁸ / cm ³ . The channel layer 101 may have an impurity concentration that has semiconductor characteristics. However, as will be described later, in order to reduce the off-current I _off caused by a physical pn junction formed between the source 104 and the drain 105, the impurity contained in the channel layer 101 has a low concentration. Is preferred.

  Next, the operation of the semiconductor device (FET) in this embodiment will be described.

  As an initial state, a case is considered in which no voltage is applied to the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111, and there is no electron in the channel layer 101 as shown in FIG. 2A.

  A positive voltage is applied to the second gate electrode 109 and the third gate electrode 111 with respect to this initial state. For example, the same positive voltage is applied to the second gate electrode 109 and the third gate electrode 111. When the applied voltage exceeds a certain value, the channel layer 101 is inverted, and an accumulation layer 201 in which electrons (carriers) are induced is formed in the channel layer 101 under the second gate electrode 109 as shown in FIG. 2B. The accumulation layer 202 in which electrons are induced is also formed in the channel layer 101 below the third gate electrode 111. This means that the so-called source and drain are electrically formed.

  When a positive voltage is applied to the first gate electrode 103 in the state where the storage layer 201 and the storage layer 202 are formed in this way, as shown in FIG. 2C, the channel layer below the first gate electrode 103 An inversion layer 203 is formed in 101, and the accumulation layer 201 and the accumulation layer 202 are connected by the inversion layer 203, so that a current flows between the source 104 and the drain 105.

As described above, according to the present embodiment, the inversion layer formed by the first gate electrode 103 that contributes to the transistor current, and the source electrically formed by the second gate electrode 109 and the third gate electrode 111. Since there is no physical pn junction between the (storage layer) and the drain (storage layer), it is possible to suppress the off-current I _off due to the physical pn junction. As is well known, pn junctions exist in the source / inversion layer and inversion layer / drain in MOS transistors and the like, and the off-current caused by the pn junction becomes a problem in n-channel MOS transistors (non- (See Patent Document 3). On the other hand, according to the semiconductor device in this embodiment, there is no pn junction between the inversion layer 203 and the storage layer 201 and the storage layer 202 adjacent to the inversion layer 203, so that the problem of off-current does not occur.

  Next, the S value in the semiconductor device of this embodiment will be described. First, consider a case where a positive voltage is applied to the drain 105 and the source 104 is grounded. In this case, as shown in FIG. 3A, when a complete inversion layer is not formed under the first gate electrode 103 and a small number of electrons (white circles) flow from the source 104 to the drain 105, the channel layer 101 is formed. Electrons having energy higher than the band gap of the semiconductor to form an electron-hole pair with a certain probability. Newly generated electrons flow into the drain 105.

  On the other hand, holes (black circles) accumulate in the channel layer 101 on the side opposite to the first gate electrode 103 (on the side of the fourth gate electrode 107). This is due to a so-called phenomenon called the floating body effect. On the other hand, the source 104, the channel layer 101, and the drain 105 have a bipolar transistor structure of n region-intrinsic region (or low concentration region) -n region, and each serves as an emitter-base-collector. This state is equivalent to a state in which a bipolar transistor is connected in parallel to a normal field effect transistor, as shown in FIG. 3B.

  Accordingly, holes accumulated in the channel layer 101 flow into the base region, and the number of electrons flowing from the emitter to the collector, that is, from the source 104 to the drain 105 is amplified. As a result, electron-hole pairs are further formed (amplified), and the source-drain current rapidly increases in an avalanche manner. This is equivalent to a decrease in the S value of the current characteristic as a result.

  According to the present embodiment, the holes accumulated in the channel layer 101, the recombination rate between the holes and electrons, and the like are controlled by the element dimensions, the gate voltage, etc., as shown in FIG. The S value can be lowered to 60 mV / dec or less while realizing a reduction in voltage and a small hysteresis characteristic.

By the way, when the amplification effect by the bipolar transistor structure is used as described above, the off-current I _off is generally amplified, but in this embodiment, the off-current I _off itself is suppressed as described above. Therefore, good off-current characteristics can be obtained as shown in FIG. 3C.

  As described above, in the semiconductor device in this embodiment, first, the second gate electrode and the third gate electrode may be newly provided, and the source and the drain may have the same conductivity type. In addition, the distance between the source and the gate electrode and the distance between the drain and the gate electrode need not be different. As described above, the semiconductor device according to the present embodiment has a structure that can be easily manufactured without largely changing the manufacturing process of the FET that is generally used at present. Also, according to the semiconductor device of the present embodiment, as described above, the S value of the FET can be reduced with stable current characteristics without increasing the source-drain voltage.

  Next, other operations will be described.

  In the above description, the fourth gate electrode 107 has a fixed potential. However, the present invention is not limited to this. For example, by using the fourth gate electrode 107, more flexible current control is possible. Since the fourth gate electrode 107 is also capacitively coupled to the channel layer 101, for example, by applying a positive voltage, an accumulation layer and an inversion layer in the channel layer 101 are more easily formed. As a result, the voltage applied to the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111 can be lowered.

  For example, by applying a positive voltage (a voltage having the same polarity as the gate voltage) to the fourth gate electrode 107, even if the gate voltage with respect to the first gate electrode 103 is lowered, the current that can flow between the source and drain is reduced. Even if the gate voltage with respect to the first gate electrode 103 is lowered, it is possible to pass a current of the same level as described above. In other words, if the gate voltage is the same, the current between the source and the drain can be amplified by applying a positive voltage to the fourth gate electrode 107.

  By the way, since there are the insulating layer 108 and the insulating layer 110 between the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111, the channel layer 101 formed immediately below these insulating layers is formed. The charge density of the storage layer to be reduced is lowered. For this reason, during operation, the voltage applied to the first gate electrode 103, the second gate electrode 109, and the third gate electrode 111 may increase. On the other hand, by using the fourth gate electrode 107 (applying a voltage having the same polarity as the gate voltage to the fourth gate electrode 107), it becomes possible to compensate the voltage applied to each gate electrode described above. .

  In addition, the voltage applied to the fourth gate electrode 107 can further reduce the voltage between the source 104 and the drain 105. When a negative voltage (voltage having a polarity different from the gate voltage) is applied to the fourth gate electrode 107, holes (black circles) in the channel layer 101 are likely to accumulate on the fourth gate electrode 107 side as shown in FIG. Become. As a result, the bipolar transistor effect described with reference to FIG. 3B becomes more prominent, and the voltage between the source 104 and the drain 105 can be lowered. This indicates that even when the source-drain voltage is lowered, the same source-drain current as that in the above case can be obtained. In other words, the source voltage is applied to the fourth gate electrode 107, so that the source-drain current is obtained. -An effect of amplifying the drain-to-drain current can be obtained.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. In the above description, the case where the same potential is applied to the second gate electrode 109 and the third gate electrode 111 has been described. This is the same as the case where the second gate electrode 109 and the third gate electrode 111 are integrally formed. For example, as shown in FIG. 5, the insulating layer 508 is formed so as to straddle the first gate electrode 103. It is good also as the electrode 509 integrally formed. Note that in FIG. 5, other structures are the same as those of the semiconductor device described with reference to FIGS. 1A to 1C.

  However, in Embodiment 1 described above, the second gate electrode 109 and the third gate electrode 111 do not need to be equipotential, and different potentials are applied to the second gate electrode 109 and the third gate electrode 111, respectively. An accumulation layer of electrons in different states may be formed in the lower channel layer 101.

  It should be noted that the present invention is not limited to the embodiment described above, and that many modifications can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

  For example, in the above description, so-called impurities are introduced into the source and drain regions and the impurity is introduced into the semiconductor layer to obtain the n-type or p-type, but this is not restrictive. For example, when the silicon layer forming the channel layer and the source / drain is as thin as 20 nm or less, impurities need not be introduced into the source / drain. In this case, when an electrical contact to the source / drain is formed of a metal, the metal reacts with the semiconductor region and the portion acts as an n region. Also, it is not necessary to introduce impurities into the source / drain by inverting the semiconductor region such as the channel layer with the fourth gate electrode 107.

  In the above description, the distance between the first gate electrode formation position and the source and the distance between the first gate electrode formation position and the drain are the same distance. However, the present invention is not limited to this, and these distances are different. It is good. In the above description, the source and drain are n-type. However, the present invention is not limited to this, and the source and drain may be p-type regions. In this case, carriers of current (source-drain current) become holes, and the polarity of each voltage to be applied is reversed.

  In the above description, silicon is used as the semiconductor. However, the present invention is not limited to this, and the same applies to the case of using other semiconductor materials such as germanium and a compound semiconductor.

  DESCRIPTION OF SYMBOLS 100 ... Semiconductor layer, 101 ... Channel layer, 102 ... Insulating layer, 103 ... 1st gate electrode, 104 ... Source, 105 ... Drain, 106 ... Insulating layer, 107 ... 4th gate electrode, 108 ... Insulating layer, 109 ... 1st 2 gate electrodes, 110 ... insulating layer, 111 ... third gate electrode.

Claims (6)

A channel layer formed in the semiconductor layer;
A source and a drain formed in the semiconductor layer across the channel layer;
A first gate electrode formed on the channel layer and spaced apart from the source and the drain;
A second gate electrode formed on the channel layer between the first gate electrode and the source and insulated from the first gate electrode;
A third gate electrode formed on the channel layer between the first gate electrode and the drain so as to be insulated from the first gate electrode;
A semiconductor device comprising: at least a first gate electrode, a second gate electrode, and a fourth gate electrode disposed to face the third gate electrode with the channel layer interposed therebetween. The semiconductor device according to claim 1,
The semiconductor device characterized in that the second gate electrode and the third gate electrode are equipotential. The semiconductor device according to claim 1 or 2,
The source and drain are regions in which impurities are introduced into the semiconductor layer. The semiconductor device according to any one of claims 1 to 3,
Two storage layers in which carriers are induced in each of the channel layers at the positions of the second gate electrode and the third gate electrode by applying voltages to the second gate electrode and the third gate electrode, respectively. Formed,
In a state where the two storage layers are formed, a gate voltage is applied to the first gate electrode, whereby an inversion layer is formed in the channel layer between the two storage layers, and the two storages A semiconductor device, wherein layers are connected by the inversion layer, and current can flow between the source and the drain. The semiconductor device according to claim 4.
When the gate voltage is applied to the first gate electrode in a state where the two storage layers are formed, a voltage having the same polarity as the gate voltage is applied to the fourth gate electrode. A featured semiconductor device. The semiconductor device according to claim 4.
When the gate voltage is applied to the first gate electrode in a state where the two storage layers are formed, a voltage having a polarity different from the gate voltage is applied to the fourth gate electrode. A featured semiconductor device.

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