KR101420967B1 - Inverter used for light emitting element driving circuit and method for manufacturing the same - Google Patents

Inverter used for light emitting element driving circuit and method for manufacturing the same Download PDF

Info

Publication number
KR101420967B1
KR101420967B1 KR1020130009106A KR20130009106A KR101420967B1 KR 101420967 B1 KR101420967 B1 KR 101420967B1 KR 1020130009106 A KR1020130009106 A KR 1020130009106A KR 20130009106 A KR20130009106 A KR 20130009106A KR 101420967 B1 KR101420967 B1 KR 101420967B1
Authority
KR
South Korea
Prior art keywords
oxide semiconductor
semiconductor layer
substrate
gate
transistor
Prior art date
Application number
KR1020130009106A
Other languages
Korean (ko)
Inventor
장진
강동한
한지웅
Original Assignee
경희대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경희대학교 산학협력단 filed Critical 경희대학교 산학협력단
Priority to KR1020130009106A priority Critical patent/KR101420967B1/en
Application granted granted Critical
Publication of KR101420967B1 publication Critical patent/KR101420967B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

An inverter used in a drive circuit of a display element and a method of manufacturing the same are disclosed. The disclosed inverter includes a driving transistor; And a load transistor connected in series with the driving transistor, wherein the driving transistor includes one first gate electrode, and the load transistor includes at least two second gate electrodes arranged in a row.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an inverter used in a driving circuit of a display device, and a method of manufacturing the inverter.

Embodiments of the present invention relate to a method of manufacturing an inverter used in a driving circuit of a display device capable of ensuring high gain and high efficiency through a simple process, and an inverter manufactured thereby.

Recently, the utilization of oxide semiconductors in display devices of various fields is increasing. Particularly, development of a new circuit using an excellent electron mobility and on / off characteristics of an oxide semiconductor transistor (TFT) is actively under way.

However, in the case of an oxide semiconductor transistor, there is a problem in that it can be driven only in the n-type, and there is a disadvantage in terms of gain and efficiency as compared with the silicon-based CMOS transistor using the n / p-type.

FIG. 1 is a view showing an example of a conventional inverter used in a drive circuit of a display device, and FIG. 2 is a diagram showing voltage transfer characteristics (VTC) of the inverter shown in FIG.

Referring to FIG. 1, all of the two transistors M1 and M2 operate in an enhancement mode including a driving transistor M1 and a load transistor M2 The gate electrode of the load transistor M2 is connected to the power supply voltage V DD ).

The conventional inverter 100 has a low gain as shown in FIG. 2, and has a disadvantage in that a voltage loss is generated at the output voltage as much as the threshold voltage of the load transistor 120.

Accordingly, studies have been made on an oxide semiconductor transistor that can ensure high gain and high efficiency by using an n-type oxide semiconductor transistor.

In this connection, a concept of connecting a driving transistor operating in the enhancement mode and a load transistor driven in the depletion mode in series in designing an inverter used in a driving circuit of a display device has been conventionally proposed . In the above conventional method, the driving mode is set by adjusting the thickness of the oxide semiconductor layer included in the driving transistor / the load transistor.

However, in general, the driving transistor and the load transistor constituting the inverter are simultaneously manufactured through a single process. In order to form the thickness of the oxide semiconductor layer of the driving transistor and the thickness of the oxide semiconductor layer of the load transistor differently, And the structure of the inverter is also complicated.

In order to solve the problems of the prior art as described above, the present invention proposes a method of manufacturing an inverter used in a driving circuit of a display device capable of ensuring high gain and high efficiency through a simple process, and an inverter I want to.

Other objects of the invention will be apparent to those skilled in the art from the following examples.

In order to achieve the above object, according to a preferred embodiment of the present invention, there is provided an inverter used in a driving circuit of a display device, comprising: a driving transistor; And a load transistor connected in series with the driving transistor, wherein the driving transistor includes one first gate electrode, and the load transistor includes at least two second gate electrodes arranged in a row. Is provided.

The driving transistor may be driven in an enhancement mode, and the load transistor may be driven in a depletion mode.

The driving transistor includes: a first substrate; A first oxide semiconductor layer formed on the first substrate and including an n + undoped region located at a center portion and an n + doped region that is an area other than the one n + undoped region; And a first source electrode / first drain electrode formed on an n + doped region of the first oxide semiconductor layer, wherein the first gate electrode comprises one n + undoped region included in the first oxide semiconductor layer, Lt; / RTI >

The load transistor comprising: a second substrate; A second oxide semiconductor layer formed on the second substrate and including at least two n + undoped regions located at the center and n + doped regions other than the at least two n + undoped regions; And a second source electrode / second drain electrode formed on an n + doped region located at both end portions of the second oxide semiconductor layer, May be formed on the n + undoped region.

The length of one n + undoped region included in the first oxide semiconductor layer is equal to or greater than a critical length, and the length of each of two or more n + undoped regions included in the second oxide semiconductor layer may be less than the critical length.

The critical length may be determined based on the material of the first oxide semiconductor layer and the second oxide semiconductor layer.

Wherein the driving transistor includes: a first buffer layer formed between the first substrate and the first oxide semiconductor layer; A first gate insulating layer formed between the first oxide semiconductor layer and the first gate electrode; And a first passivation layer formed on the first gate electrode, wherein the load transistor comprises: a second buffer layer formed between the second substrate and the second oxide semiconductor layer; At least two second gate insulating films respectively formed between the second oxide semiconductor layer and the at least two second gate electrodes; And a second passivation layer formed on the at least two gate electrodes.

According to another embodiment of the present invention, there is provided a method of manufacturing an inverter including a driving transistor and a load transistor connected in series, the method comprising forming a first oxide semiconductor layer on a first substrate, Forming a second oxide semiconductor layer on a second substrate; Forming a first gate electrode on the first oxide semiconductor layer, forming at least two second gate electrodes arranged in a line on the second oxide semiconductor layer, and forming the first gate electrode on the first oxide semiconductor layer, Doping the region of the first oxide semiconductor layer of the first gate electrode and the region of the second oxide semiconductor layer where the second gate electrode is not formed with n +; And a first source electrode / a first drain electrode in a region of the first oxide semiconductor layer doped with n +, and a second source electrode / a second drain electrode in a region of the n + doped second oxide semiconductor layer, Wherein the first substrate, the first oxide semiconductor layer, the one first gate electrode, and the first source electrode / first drain electrode constitute the driving transistor, 2 substrate, the second oxide semiconductor layer, the second or more second gate electrodes, and the second source electrode / second drain electrode constitute the load transistor.

The inverter used in the driving circuit of the display device according to the present invention can be manufactured through a simple process, and has advantages of high gain and high efficiency.

1 is a diagram showing an example of a conventional inverter used in a drive circuit of a display device.
FIG. 2 is a view showing voltage transfer characteristics of the inverter shown in FIG. 1. FIG.
3 is a view showing an equivalent circuit of an inverter used in a driving circuit of a display device according to an embodiment of the present invention.
4 is a diagram showing a detailed configuration of a driving transistor constituting an inverter according to an embodiment of the present invention.
5 is a diagram showing a detailed configuration of a load transistor constituting an inverter according to an embodiment of the present invention.
6 is a flowchart showing an overall flow of a method of manufacturing an inverter according to an embodiment of the present invention.
7 is a graph showing current-voltage characteristics of a transistor according to an embodiment of the present invention.
FIG. 8 is a graph showing a change in threshold voltage and a field effect mobility characteristic of a transistor according to an embodiment of the present invention.
9 is a diagram illustrating an input / output relationship of an inverter according to an embodiment of the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a view showing an equivalent circuit of an inverter used in a driving circuit of a display device according to an embodiment of the present invention.

Referring to FIG. 3, an inverter 300 according to an embodiment of the present invention includes a driving transistor 310 and a load transistor 320 connected in series with the driving transistor 310.

The bias voltage V DD for driving the inverter 300 is input to the drain electrode of the load transistor 320 and the input voltage V in for driving the display device is applied to the gate electrode And the input terminal of the display element is connected to the drain electrode of the driving transistor 310 and the source electrode / gate electrode of the load transistor 320 and is connected to the output voltage V out .

4 is a diagram showing a detailed configuration of the driving transistor 310 described above.

4, a driving transistor 310 according to an embodiment of the present invention has a self-aligned type coplanar structure and includes a first substrate 311, a first buffer layer 312, an n + The first gate insulating film 314, the first gate electrode 315, the first passivation layer 316, and the second passivation layer 313 including the n + doped region 313-1 and the n + And includes a first source electrode 317 and a first drain electrode 318.

5 is a diagram showing a detailed configuration of the load transistor 320 described above.

5, the load transistor 320 according to an exemplary embodiment of the present invention also has a self-aligned coplanar structure. The second substrate 321 includes a second buffer layer 322, an n + undoped region 323-1 A second gate insulating film 324, a second gate electrode 325, a second passivation layer 326, and a second source electrode 323 including an n + doped region 323-2. A first drain electrode 327, and a second drain electrode 328.

Here, the driving transistor 310 and the load transistor 320 may be an oxide semiconductor thin film transistor (TFT).

The driving transistor 310 and the load transistor 320 may be simultaneously manufactured through a single manufacturing process. In FIG. 6, the driving transistor 310 and the load transistor 320 may include the driving transistor 310 and the load transistor 320, And shows a general flow of the manufacturing method of the inverter 300.

4 to 6, a detailed structure of the driving transistor 310 and the load transistor 320 constituting the inverter 300 according to an embodiment of the present invention and a manufacturing method thereof will be described in detail .

First, in step S602, buffer layers 312 and 322 are formed on the substrates 311 and 321, respectively.

Here, the substrates 311 and 321 support the respective components of the transistors 310 and 320, and may be made of an insulating material such as glass or a silicon material. The buffer layers 312 and 322 function to prevent the inflow of impurities that may occur in the manufacturing process.

Next, in step S604, the oxide semiconductor layers 313 and 323 are formed on the buffer layers 312 and 322, respectively.

The oxide semiconductor layers 313 and 323 function as an active layer and are formed of amorphous-InGaZnO 4, zinc oxide (ZnO), indium zinc oxide (IZO), indium tin oxide (ITO) , Zinc tin oxide (ZTO), and gallium zinc oxide (GZO), or a mixture thereof. However, the present invention is not limited thereto.

Subsequently, in step S606, gate insulating films 314 and 324 and gate electrodes 315 and 325 are sequentially formed on the oxide semiconductor layers 313 and 323, and a part of the oxide semiconductor layers 313 and 323 is formed n +. < / RTI > Here, the gate insulating films 314 and 324 may be oxides or metal oxides (for example, silicon oxide (SiO 2 )), and the gate electrodes 315 and 325 may be metal materials (for example, molybdenum have.

According to an embodiment of the present invention, in step S606, the gate insulating film forming material and the gate electrode forming material are sequentially stacked on the oxide semiconductor layers 313 and 323, and then the gate insulating films 314 and 324 And the gate electrodes 315 and 325 can be formed. At this time, the regions of the oxide semiconductor layers 313 and 323 where the gate insulating film forming material and the gate electrode forming material are etched are doped with n +, and the regions of the oxide semiconductor layers 313 and 323 that are not etched are not doped with n + . In addition, additional doping processing may be further performed to increase the concentration of n + doping. Thus, as shown in FIGS. 4 and 5, n + undoped regions 313-1 and 323-1 and n + doped regions 313-2 and 323-2 can be formed.

In detail, in the case of the driving transistor 310, one n + undoped region 313-1 is formed in the center portion of the first oxide semiconductor layer 313, and the remaining portion of the first oxide semiconductor layer 313 The region becomes the n + doped region 313-2, and one first gate insulating film 314 and one first gate electrode 315 are formed on the n + undoped region 313-1.

In addition, in the case of the load transistor 320, at least two n + -type doped regions 323-1 are formed in the middle portion of the second oxide semiconductor layer 323, and the remaining region of the second oxide semiconductor layer 323 Doped region 323-2, and at least two second gate insulating films 324 and at least two second gate electrodes 325 are formed on the n + undoped region 323-1, respectively. 5, the number of the n + undoped regions 323-1, the second gate insulating film 324, and the second gate electrodes 325 is four. However, this is only an example, and the present invention is not limited thereto Do not.

In short, the driving transistor 310 includes one first gate electrode 315, and the load transistor 320 includes two or more second gate electrodes 325 arranged in a row.

Thereafter, passivation layers 318 and 328 are formed on the gate electrodes 315 and 325 in step S608. In step S606, a material for forming a protective layer is deposited and a part of the material is patterned to expose at least a portion of the n + doped regions 313-2 and 323-2 of the oxide semiconductor layers 313 and 323, The protective layers 318 and 328 can be formed.

Finally, in step S610, source electrodes 317 and 327 and drain electrodes 318 and 328 are formed on the protective layers 318 and 328, more precisely, in the contact hole portions of the protective layers 318 and 328 do. The source electrodes 317 and 327 and the drain electrodes 318 and 328 may be made of a metal material (for example, molybdenum (Mo)). A first source electrode 317 and a first drain electrode 318 are formed on the n + doped region 313-2 of the first oxide semiconductor layer 313, The second source electrode 327 and the second drain electrode 328 are formed on the n + doped region 323-2.

Thus, the manufacture of the inverter 300 having the structure in which the driving transistor 310 having the long channel single gate structure and the load transistor 320 having the short channel multi gate structure are connected in series is completed.

The inverter 300 having the above structure has the following advantages.

As described above, in order to realize an inverter capable of ensuring high gain and high efficiency by using an n-type oxide semiconductor transistor, a drive transistor operating in the enhancement mode and a load transistor driven in the depletion mode are connected in series However, when the thickness of the oxide semiconductor layer is adjusted as in the conventional method, the process and the structure of the inverter become complicated.

However, when the load transistor 320 is formed into a single-channel multi-gate structure and two or more gate electrodes 325 are connected to the source electrode 327 of the load transistor 320 as in the present invention, Is driven in the depletion mode. Accordingly, when the load transistor 320 is connected in series with the driving transistor 310 operating in the enhancement mode, the two transistors 310 and 320 can be manufactured at the same time, And the structure of the inverter is simplified to realize a small-sized circuit, and it is possible to secure the gain and efficiency of a high inverter.

More specifically, in order for the oxide semiconductor transistor to operate in the depletion mode, an n + undoped region (that is, a length of the gate electrode) in the oxide semiconductor layer forming a channel must be secured over a certain length. However, when a transistor having a long channel single gate structure (i.e., a transistor having a long single gate electrode) is used as a load transistor, W / L (width / length) of the gate electrode of the load transistor and W / (Β-ratio), which is a ratio of the output voltage of the inverter to the output voltage of the inverter, is rapidly lowered, which causes a disadvantage of reducing the gain and efficiency of the inverter.

However, when the load transistor 320 is implemented to include two or more gate electrodes 325 having a short length L, as in the embodiment of the present invention, sufficient n + (The length of the entire n + undoped region (gate electrode) corresponds to the sum of the lengths of two or more n + undoped regions (gate electrodes)) while ensuring the length of the doped region (gate electrode) The length L of the load transistor 320 for calculating the beta-ratio corresponds to the length of each of the two or more gate electrodes 325, being).

For example, when the length of the n + undoped region 323-1 to be secured for driving the load transistor 320 in the depletion mode is 8 μm, four n + undoped regions 323 having a length of 2 μm -1). In this case, since the length of the n + undoped region 323-1 of the load transistor 320 as a parameter for calculating the beta-ratio becomes 2 mu m, the beta-ratio does not decrease, .

In other words, the inverter 300 according to the present invention includes a driving transistor 310 having one gate electrode 315 driven in an enhancement mode and a load transistor 322 having two or more gate electrodes 325 driven in a depletion mode. The inverter 300 has a structure in which a driving area and a noise margin are increased, a high gain can be realized, and a circuit size, which is important in application of an actual display driving circuit, can be reduced .

The length of one n + undoped region 313-1 included in the first oxide semiconductor layer 313 is equal to or greater than the critical length and two or more n + undoped regions included in the second oxide semiconductor layer 323 323-1) may be less than the critical length. Here, the critical length may be determined based on the material of the first oxide semiconductor layer 313 and the second oxide semiconductor layer 323, the structure of the driving transistor 310 and the load transistor 320, and the like. As an example, the critical length may be 3 [mu] m.

Hereinafter, the performance of the inverter 300 according to an embodiment of the present invention will be described in detail with reference to FIGS. 7 to 9 show that the transistors 310 and 320 are oxide semiconductor thin film transistors and the voltage applied to the drain electrode is 0.1 V and the ratio of the width to the length of the channel (i.e., n + ) Is 20 mu m / 12 mu m.

7 is a graph showing current-voltage characteristics of the transistors 310 and 320 according to an embodiment of the present invention. That is, FIG. 7 shows the transfer characteristics (the relationship between the gate voltage and the drain current) in accordance with the change in the number of gate electrodes (1, 2, 3, or 4).

Referring to FIG. 7, it can be seen that the threshold voltages of the four types of oxide semiconductor thin film transistors having the same total channel area are differentiated. In particular, when the number of gate electrodes is four, it can be confirmed that the threshold voltage is shifted by about -8 V as compared with the case where the number of gate electrodes is one. As a result, the oxide semiconductor thin film transistor (that is, the driving transistor 310) of the long channel single gate structure having the same total channel length is driven in the enhancement mode and the oxide semiconductor thin film transistor (320) is driven in the depletion mode.

Next, FIG. 8 is a graph showing a change in threshold voltage and a field effect mobility characteristic of the transistors 310 and 320 according to an embodiment of the present invention. That is, FIG. 8 shows changes in the threshold voltage and the field effect mobility according to the change in the number of gate electrodes (1, 2, 3, and 4).

Referring to FIG. 8, it can be seen that the larger the number of gate electrodes, the lower the threshold voltage and the greater the field effect mobility.

Lastly, FIG. 9 is a diagram showing an input / output relationship of the inverter 300 according to an embodiment of the present invention.

Meanwhile, two or more of the inverters 300 may be connected to form a shift register. Therefore, the above-described contents are also applied to a shift register composed of two or more inverters 300. [

As described above, the present invention has been described with reference to particular embodiments, such as specific elements, and limited embodiments and drawings. However, it should be understood that the present invention is not limited to the above- Various modifications and variations may be made thereto by those skilled in the art to which the present invention pertains. Accordingly, the spirit of the present invention should not be construed as being limited to the embodiments described, and all of the equivalents or equivalents of the claims, as well as the following claims, belong to the scope of the present invention .

Claims (8)

1. An inverter used in a drive circuit of a display element,
A driving transistor including a first gate electrode; And
And a load transistor connected in series with the driving transistor,
The load transistor includes: a second substrate; A second oxide semiconductor layer formed on the second substrate and including at least two n + undoped regions located at the center and n + doped regions other than the at least two n + undoped regions; Two or more second gate electrodes formed on two or more n + undoped regions included in the second oxide semiconductor layer and arranged in a row, the number of the second or more second gate electrodes and the two or more n + undoped regions are the same , One second gate electrode is formed on the at least two n + undoped regions; And a second source electrode / second drain electrode formed on n + doped regions located at both end portions of the second oxide semiconductor layer. The method according to claim 1,
Wherein the drive transistor is driven in an enhancement mode and the load transistor is driven in a depletion mode. The method according to claim 1,
The driving transistor includes: a first substrate; A first oxide semiconductor layer formed on the first substrate and including an n + undoped region located at a center portion and an n + doped region that is an area other than the one n + undoped region; And a first source electrode / first drain electrode formed on an n + doped region of the first oxide semiconductor layer,
Wherein the first gate electrode is formed on one n + undoped region included in the first oxide semiconductor layer. delete The method according to claim 1,
Wherein a length of one n + undoped region included in the first oxide semiconductor layer is equal to or greater than a critical length, and a length of each of two or more n + undoped regions included in the second oxide semiconductor layer is less than the critical length. inverter. 6. The method of claim 5,
Wherein the critical length is determined based on a material of the first oxide semiconductor layer and the second oxide semiconductor layer. The method of claim 3,
Wherein the driving transistor includes: a first buffer layer formed between the first substrate and the first oxide semiconductor layer; A first gate insulating layer formed between the first oxide semiconductor layer and the first gate electrode; And a first passivation layer formed on the first gate electrode,
A second buffer layer formed between the second substrate and the second oxide semiconductor layer; At least two second gate insulating films respectively formed between the second oxide semiconductor layer and the at least two second gate electrodes; And a second passivation layer formed on the at least two second gate electrodes. A method of manufacturing an inverter including a drive transistor and a load transistor connected in series, the drive transistor being used in a drive circuit of a display device,
Forming a first oxide semiconductor layer on a first substrate and a second oxide semiconductor layer on a second substrate;
Forming a first gate electrode on the first oxide semiconductor layer, forming at least two second gate electrodes arranged in a line on the second oxide semiconductor layer, and forming the first gate electrode on the first oxide semiconductor layer, Doping the region of the first oxide semiconductor layer of the first gate electrode and the region of the second oxide semiconductor layer where the second gate electrode is not formed with n +; And
A first source electrode / a first drain electrode is formed in a region of the n + doped first oxide semiconductor layer, and a second source electrode / a second drain electrode is formed in a region of the n + doped second oxide semiconductor layer, The method comprising:
Wherein the first substrate, the first oxide semiconductor layer, the one first gate electrode, and the first source electrode / first drain electrode constitute the driving transistor, and the second substrate, the second oxide semiconductor layer, Wherein the at least two second gate electrodes and the second source electrode / second drain electrode constitute the load transistor. .
KR1020130009106A 2013-01-28 2013-01-28 Inverter used for light emitting element driving circuit and method for manufacturing the same KR101420967B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020130009106A KR101420967B1 (en) 2013-01-28 2013-01-28 Inverter used for light emitting element driving circuit and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130009106A KR101420967B1 (en) 2013-01-28 2013-01-28 Inverter used for light emitting element driving circuit and method for manufacturing the same

Publications (1)

Publication Number Publication Date
KR101420967B1 true KR101420967B1 (en) 2014-07-17

Family

ID=51742504

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130009106A KR101420967B1 (en) 2013-01-28 2013-01-28 Inverter used for light emitting element driving circuit and method for manufacturing the same

Country Status (1)

Country Link
KR (1) KR101420967B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102577282B1 (en) 2022-03-30 2023-09-12 호서대학교 산학협력단 Inverter and bootstrap inverter with improved output characteristics

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801961B1 (en) * 2006-05-26 2008-02-12 한국전자통신연구원 Organic Inverter with Dual-Gate Organic Thin-Film Transistor
KR20100037407A (en) * 2008-10-01 2010-04-09 삼성전자주식회사 Inverter, method of operating the same and logic circuit comprising inverter
KR20120028226A (en) * 2010-09-13 2012-03-22 미쓰비시덴키 가부시키가이샤 Power amplifier
KR20120070709A (en) * 2010-12-22 2012-07-02 경희대학교 산학협력단 Oxide semiconductor inverter using depletion mode of dual gate thin film transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100801961B1 (en) * 2006-05-26 2008-02-12 한국전자통신연구원 Organic Inverter with Dual-Gate Organic Thin-Film Transistor
KR20100037407A (en) * 2008-10-01 2010-04-09 삼성전자주식회사 Inverter, method of operating the same and logic circuit comprising inverter
KR20120028226A (en) * 2010-09-13 2012-03-22 미쓰비시덴키 가부시키가이샤 Power amplifier
KR20120070709A (en) * 2010-12-22 2012-07-02 경희대학교 산학협력단 Oxide semiconductor inverter using depletion mode of dual gate thin film transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102577282B1 (en) 2022-03-30 2023-09-12 호서대학교 산학협력단 Inverter and bootstrap inverter with improved output characteristics

Similar Documents

Publication Publication Date Title
US11088032B2 (en) Electronic device based on two-dimensional semiconductor and method for manufacturing electronic device
US8791529B2 (en) Semiconductor device including gate and conductor electrodes
US7709311B1 (en) JFET device with improved off-state leakage current and method of fabrication
US20110220878A1 (en) Thin film transistor and method of manufacturing the same
US20180012980A1 (en) Lateral insulated gate bipolar transistor
US8486754B1 (en) Method for manufacturing a gate-control diode semiconductor device
US7525136B2 (en) JFET device with virtual source and drain link regions and method of fabrication
US20130270637A1 (en) Semiconductor device
US20130178012A1 (en) Method for manufacturing a gate-control diode semiconductor device
US20220157978A1 (en) p-GaN HIGH ELECTRON MOBILITY TRANSISTOR
KR101420967B1 (en) Inverter used for light emitting element driving circuit and method for manufacturing the same
US20100084684A1 (en) Insulated gate bipolar transistor
KR101275713B1 (en) Oxide semiconductor inverter and display driving apparatus using thereof
US6548356B2 (en) Thin film transistor
KR100540404B1 (en) Semiconductor device
CN104282754A (en) High-performance and high-integration-level L-shaped gate-control schottky barrier tunneling transistor
CN113644069B (en) Novel CMOS inverter with homogeneous grid metal and preparation method thereof
KR20100081836A (en) Logic circuit device having stacked semiconductor oxide transistors
JP2011124268A (en) Semiconductor device
CN116544246A (en) Array substrate and display panel
WO2016127337A1 (en) Preparation method for multi-layer tunneling junction three-dimensional tunneling field-effect transistor
KR20140021405A (en) Inverter used for light emitting element driving circuit and load transitor comprised in the inverter
KR20130138045A (en) Ndr semiconductor device and production process thereof
JP2012033682A (en) Semiconductor device, method of manufacturing the same, and method of driving the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E90F Notification of reason for final refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20170627

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20180702

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20190703

Year of fee payment: 6