KR20100081836A - Logic circuit device having stacked semiconductor oxide transistors - Google Patents

Abstract

PURPOSE: A logical circuit device including stacked semiconductor oxide transistors is provided to convert transistors from a depletion mode to an enhancement mode by regulating a threshold voltage between transistors. CONSTITUTION: A first semiconductor oxide transistor includes a first semiconductor oxide channel layer(CH1). A second semiconductor transistor includes a second semiconductor oxide channel layer(CH2). A body gate(V_body) is located between the first transistor and the second transistor. A negative voltage is applied to the body gate, and the threshold voltages of the first transistor and the second transistor are transferred toward a positive direction. A first gate oxide(GOX1) is formed between the body gate and the first channel layer. A second gate oxide(GOX2) is formed between the body gate and the second channel layer.

Description

Logic devices having stacked semiconductor oxide transistors

Embodiments of the present invention relate to logic devices having stacked semiconductor oxide transistors.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In order to improve the operating characteristics of the transistor, a method of applying an oxide layer having a high carrier mobility, for example, a ZnO-based material layer, as a channel layer has been attempted. Most of the channel layer formed of oxide is an n-channel layer, and an oxide transistor is a depletion mode transistor in which a threshold voltage is a negative voltage.

Continuous scaling-down is required to increase the performance and integration of logic circuits and to reduce the cost required to implement unit functions. Implementation of stacked logic circuits using oxide semiconductors is required for scaling down beyond the limits of lithography technology.

Stacked logic circuits, when implemented using oxide transistors, require enhanced mode transistors.

An embodiment of the present invention provides a logic device having a body gate for controlling a threshold voltage between stacked semiconductor oxide transistors to convert from a depletion mode transistor to an enhancement mode transistor.

A logic device having a stacked semiconductor oxide transistor according to an embodiment of the present invention includes: a first semiconductor oxide transistor having a first semiconductor oxide channel layer;

A second semiconductor oxide transistor having a second semiconductor oxide channel layer; And

The first transistor and the second transistor are vertically stacked, and a body gate disposed therebetween.

When a negative voltage is applied to the body gate, the threshold voltages of the first transistor and the second transistor move in a positive direction.

A first gate oxide is formed between the body gate and the first channel layer, and a second gate oxide is formed between the body gate and the second channel layer.

The second gate oxide thickness may be greater than the first gate oxide thickness.

The first transistor acts as an enhancement mode transistor and the second transistor acts as a depletion mode transistor according to the negative voltage applied to the body gate.

In accordance with another aspect of the present invention, a logic device includes: a first metal wiring connecting a drain of the first transistor and a source of the second transistor; And

And a second metal wire connecting the first metal wire and the second gate.

A ground voltage source is connected to a source of the first transistor, an input voltage source is connected to a drain of the second transistor, an input terminal is connected to the first gate, and an output terminal is connected to the first metal wire.

And a second metal wiring connecting the drain of the second transistor and the second gate.

A ground voltage source is connected to the source of the first transistor, an input voltage source is connected to the second metal wiring, an input terminal is connected to the first gate, and an output terminal is connected to the first metal wiring.

The first channel layer and the second channel layer may each have a thickness of 100 μs to 1000 μs.

In another embodiment, a logic device includes: a first semiconductor oxide transistor having a first semiconductor oxide channel layer;

A second semiconductor oxide transistor having a second semiconductor oxide channel layer on the first transistor;

A third semiconductor oxide transistor having a third semiconductor oxide channel layer on the second transistor; And

And a body gate disposed between the first transistor and the second transistor,

When a negative voltage is applied to the body gate, the threshold voltages of the first transistor and the second transistor move in a positive direction.

According to a negative voltage applied to the body gate, the first transistor and the second transistor serve as an enhancement mode transistor, and the second transistor and the first transistor are connected in series with a source and ground voltage source of the third transistor. The logic element is a NOR circuit.

A logic device according to an embodiment of the present invention, the first metal wiring for connecting the drain of the first transistor and the source of the second transistor;

A second metal wire connecting a drain of the second transistor and a source of the third transistor; And

And a third metal wire connecting the gate of the second metal wire and the third transistor.

And a third metal wire connected to the drain of the third transistor and a gate of the third transistor and a drain of the third transistor.

An input voltage source is connected to the third metal wiring, a first input terminal is connected to a gate of the first transistor, a second input terminal is connected to a gate of the second transistor, and an output terminal is connected to the second metal wiring. Connected.

The first transistor and the second transistor act as enhancement mode transistors according to the negative voltage applied to the body gate, and the second transistor and the first transistor are connected in parallel to the source and ground voltage sources of the third transistor. The logic element is a NAND circuit.

According to another aspect of the present invention,

A first metal wire connecting the source of the first transistor and the source of the second transistor;

A second metal wiring connecting the drain of the first transistor and the drain of the second transistor;

A third metal wire electrically connecting the second metal wire and the source of the third transistor; And

And a fourth metal wiring connecting the gate of the third transistor and the third metal wiring.

A ground voltage source connected to the first metal line, and a third metal line connecting a drain of the third transistor and a gate of the third transistor to a drain of the third transistor; And

And a fourth metal wiring electrically connecting the second metal wiring and the source of the third transistor.

A ground voltage source is connected to the first metal line, an input voltage source is connected to the third metal line, a first input terminal is connected to the first gate, and a second input terminal is connected to the second gate. An output terminal is connected to the fourth metal wiring.

According to an embodiment of the present invention, a stacked logic device using a semiconductor oxide transistor can be manufactured, and thus the degree of integration can be shaped. By shifting the threshold voltage of the stacked semiconductor oxide transistor, a logic device including an oxide transistor of an enhancement mode and a depletion mode may be implemented.

Hereinafter, a logic device having a stacked semiconductor oxide transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The width and thickness of the layers or regions shown in the accompanying drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

1 is a cross-sectional view showing a logic device according to an embodiment of the present invention. Referring to FIG. 1, a first semiconductor oxide transistor and a second semiconductor oxide transistor are stacked on a substrate, and a body gate Vbody is formed among these transistors. Both the first transistor and the second transistor are originally depletion mode transistors, and the threshold voltage is negative. However, to be used as a logic device, one of them must be an enhancement mode transistor. When a predetermined negative voltage is applied to the body gate Vbody, one of the first transistor and the second transistor is converted into an enhancement mode transistor.

The first semiconductor oxide transistor includes an insulating layer INS1 on the substrate SUB, a first gate G1 on the insulating layer INS1, and a first gate oxide GOX1 covering the first gate G1 on the insulating layer INS1. ), A first semiconductor oxide channel layer CH1 on the first gate oxide GOX1, and a first source S1 and a first drain D1 connected to both sides of the first channel layer CH1 and spaced apart from each other. do. The first transistor is a bottom transistor.

The substrate SUB may be formed of glass, plastic, silicon, or the like. When the substrate SUB is formed of a non-conductive material, the insulating layer INS1 may be omitted.

The first gate G1 may be formed of a general gate material such as aluminum.

The first gate oxide GOX1 may be formed of silicon nitride or silicon oxide.

The first semiconductor oxide channel layer CH1 (hereinafter also referred to as a first channel layer) may be an n-type semiconductor layer including a ZnO-based material. Group 3 elements such as In and Ga, Group 4 elements such as Sn, or other elements may be further included.

The first source S1 and the first drain D1 may be formed of a metal material such as molybdenum or aluminum.

A third gate oxide GOX3 on the first channel layer CH1; A body gate Vbody; The fourth gate oxide GOX is sequentially formed. The body gate Vbody may be formed of the same material as the first gate G1, and the third gate oxide GOX3 and the fourth gate oxide GOX4 are each formed of the same material as the first gate oxide GOX1. Can be.

A second semiconductor oxide transistor is formed on the fourth gate oxide GOX4.

The second semiconductor oxide transistor includes a second source S2 and a second drain D2 formed on both sides of the second semiconductor oxide channel layer CH2 and the second semiconductor oxide channel layer CH2 on the fourth gate oxide GOX4. It is provided. The second gate oxide GOX2 is formed on the second channel layer CH2, and the second gate G2 is formed on the second gate oxide GOX2. The second transistor is a tower transistor. A protective layer INS2 may be further formed on the second transistor as an insulating layer.

The second gate G2 may be formed of a general gate material such as aluminum.

The second gate oxide GOX2 may be formed of silicon nitride or silicon oxide.

The second semiconductor oxide channel layer CH2 may be an n-type semiconductor layer including a ZnO-based material. Group 3 elements such as In and Ga, Group 4 elements such as Sn, or other elements may be further included.

The second source S2 and the second drain D2 may be formed of a metal material such as molybdenum or aluminum.

The first channel layer CH1 and the second channel layer CH2 may each have a thickness of 100 μs to 1000 μs. When the first and second channel layers are to be formed at less than 100 Hz, the thickness of the channel layers is difficult to be uniformly formed. If the thickness of the channel layer is formed to be 1000 Å or more, current flows poorly because current flows only on the surface.

FIG. 2 is an I-V characteristic curve of the first gate G1 and the second gate G2 when a predetermined negative voltage is applied to the body gate Vbody according to the exemplary embodiment of the present invention.

Referring to FIG. 2, when no voltage is applied to the body gate Vbody, the gate becomes a depletion mode transistor whose threshold voltage is a negative voltage. As a negative voltage is applied to the body gate Vbody, the threshold voltage moves toward the positive voltage. When more than -2V is applied to the body gate Vbody, the depletion mode transistor is switched to the enhancement mode transistor.

3 is a view for explaining the operation of the logic device according to an embodiment of the present invention.

When no voltage is applied to the body gate Vbody, both the first transistor and the second transistor become a depletion mode transistor with both threshold voltages as negative voltages.

When the -3 V voltage is applied to the body gate Vbody, the threshold voltage of the first transistor and the second transistor is shifted, so that the threshold voltage of the first transistor becomes a positive voltage, so that the first transistor is an enhanced mode transistor. do. The intrinsic threshold voltages of the first and second transistors may be determined according to the type, thickness, etc. of the semiconductor oxide channel layer. For example, when the thicknesses of the first channel layer and the second channel layer are the same and formed of the same material, when the thickness of the second gate oxide GOX2 is greater than the thickness of the first gate oxide GOX1, the second channel layer may be formed. The transistor is less affected by the bi-gate voltage Vbody than the first transistor, and therefore, only the first transistor can be selectively converted to the enhancement mode transistor. Hereinafter, a description will be given of a case in which the first transistor becomes an enhancement mode transistor by the body gate voltage.

4 is a logic device diagram according to an embodiment of the present invention. The same reference numerals are used for the components substantially the same as the components of FIG. 1, and the detailed description is omitted.

4 is an inverter circuit. A predetermined negative voltage is applied to the body gate Vbody, whereby the first transistor becomes the enhancement mode transistor E-TFT and the second transistor is maintained as the depletion mode transistor D-TFT. The second transistor and the first transistor are connected in series between an input voltage source to which the input voltage Vdd is applied and a ground power source to which the ground voltage is applied.

Referring to FIG. 1, the first drain D1 of the first transistor and the second source S2 of the second transistor are connected to the first metal wiring ML1, and the second drain D2 gate of the second transistor is connected. G2 is connected to the first metal wiring ML1 by the second metal wiring ML2. These metallizations ML1 and ML2 may be plugs between the silver connection elements.

The input voltage source is connected to the second metal wiring ML2 drain D2, the ground power source is connected to the first source S1, the input terminal Vin is connected to the first gate G1, and the output terminal Vout. ) Is connected to the first metal wiring ML1 between the first transistor and the second transistor, and the body voltage source Vbody is connected to the body gate Vbody.

When a turn-on voltage, for example, a 1 V voltage is applied to the first gate G1 and a 5 V voltage is applied to the input voltage, the ground voltage is detected at the output terminal Vout. When a voltage equal to or lower than the turn-on voltage is applied to the first gate G1, the input voltage Vdd is output to the output terminal Vout. Thus, the logic elements of FIGS. 1 and 4 act as inverter circuits.

Inverter circuit according to an embodiment of the present invention can be implemented by stacking transistors to improve the integration efficiency. In addition, in the semiconductor oxide transistor according to the present invention, fluctuation in threshold voltage due to process variation is reduced.

5 is a cross-sectional view of a noah logic device according to another embodiment of the present invention. The same reference numerals are used for the components substantially the same as the components of FIG. 1, and the detailed description is omitted.

Referring to FIG. 5, a third semiconductor oxide transistor is further stacked on the structure of FIG. 1. An insulating layer INS2 covering the second gate G2 is formed on the structure of FIG. 1. A metal wire (not shown) may be further formed on the second insulating layer INS2, and the metal wire may be used as a wire for applying power to the first transistor and the second transistor. The third gate G3 is formed on the insulating layer INS2, and the third gate oxide GOX3 is formed on the third gate G3 to cover the insulating layer INS2. The third semiconductor oxide channel layer CH3 (hereinafter also referred to as a second channel layer) is formed on the third gate oxide GOX3. The third source S3 and the third drain D3 are formed at both sides of the third channel layer CH. A protective layer INS3 serving as an insulating layer is formed on the third semiconductor oxide transistor. The third transistor is a bottom gate transistor. However, the third transistor may be a top gate transistor, and a detailed description thereof will be omitted.

The first channel layer CH1, the second channel layer CH2, and the third channel layer CH3 may each have a thickness of 100 μs to 1000 μm.

The first transistor and the second transistor are both converted to the enhancement mode transistor while a predetermined negative voltage, for example, a −3 V voltage is applied to the body gate Vbody. Since the third transistor is hardly affected by the body gate voltage even when the body gate voltage Vbody is applied, the third transistor maintains the depleted transistor.

FIG. 6 is a noah logic element diagram of FIG. 5. Components that are substantially the same as those of FIG. 5 are given the same reference numerals and detailed descriptions thereof will be omitted.

When a predetermined negative voltage is applied to the body gate Vbody, the first transistor and the second transistor act as the enhancement mode transistor E-TFT. Since the third transistor is not affected by the body gate Vbody, it is maintained as a depletion mode transistor D-TFT.

Referring to FIG. 6, a third transistor, a second transistor, and a first transistor are connected in series between an input voltage source and a ground voltage source. The third drain D3 and the third gate G3 of the third transistor are connected to an input voltage, and the ground voltage is connected to the first source S1 of the first transistor. A first input terminal Vin1 and a second input terminal Vin2 are connected to the first gate G1 and the second gate G2, respectively, and are output between the third source S3 and the second drain D2. Terminal Vout is connected.

Referring to FIG. 5, a first input terminal and a second input terminal are connected to the first gate G1 and the second gate G2, respectively. The first drain D1 and the second source S2 are connected by the first metal wiring ML1, and the second drain D2 and the third source S3 are connected by the second metal wiring ML2. do. The third drain D3, the second wiring ML, and the third gate G3 are connected by the third metal wiring ML3. An input voltage source is connected to the third metal line ML3 and the drain D3.

The ground voltage is output to the output terminal Vout only when the respective threshold voltages are applied to both the first input terminal Vin1 and the second input terminal Vin2. That is, the low value is output only when both the first and second input voltages are high, otherwise the signal is high because the input voltage is output. Therefore, FIG. 5 and FIG. 6 become a noah circuit.

7 is a cross-sectional view of a NAND logic device according to another embodiment of the present invention. Components that are substantially the same as those of FIG. 5 are given the same reference numerals and detailed descriptions thereof will be omitted.

Referring to FIG. 7, the components of FIG. 7 may include a metal wiring, a second source S2, a second drain D2, a third source S3, and a third drain D3. It may be the same as the structure of.

The first transistor and the second transistor are switched to the enhancement mode transistor while a predetermined negative voltage, for example, a −3 V voltage is applied to the body gate Vbody. Since the third transistor is hardly affected by the body gate voltage even when the voltage of the body gate Vbody is applied, the third transistor maintains the depletion mode transistor.

A metal wiring (not shown) is further formed on the insulating layer INS2 to be used as a path for wiring for applying a voltage to the first transistor and the second transistor and for connecting the third transistor with another transistor. Can be.

FIG. 8 is a NAND logic device diagram of FIG. 7. The same reference numerals are used for the components substantially the same as those in FIG. 7, and detailed descriptions thereof will be omitted.

When a predetermined negative voltage is applied to the body gate Vbody, the first transistor and the second transistor become the enhancement mode transistor E-TFT. Since the third transistor is not affected by the bar gate Vbody, it is maintained as the depletion mode transistor D-TFT.

Between the input voltage source and the ground voltage source, a third transistor is connected to the input voltage source, and the first and second transistors are connected in parallel to the third transistor and the ground voltage source.

An input voltage source is connected to the third drain D3 and the third gate G3 of the third transistor, and a ground voltage source is connected to the first source S1 of the first transistor and the second source S2 of the second transistor. do. The first input terminal Vin1 and the second input terminal Vin2 are respectively connected to the first gate G1 and the second gate G2, and the output terminal Vout is electrically connected to the third source S3. do. The first to fourth metal wires ML1 to ML4 will be described with reference to FIG. 7.

The first source and the second source may be connected to the first metal line ML1, and the ground voltage source may be connected to the first metal line ML1. The first drain and the second drain are connected by the second metal wiring ML2. The third drain D3 and the third gate G3 may be connected by the third metal line ML3, and the input voltage source may be connected to the third metal line ML3 drain D3. The third source S3 and the second metal wire ML2 may be connected by the silver fourth metal wire ML4ML3, and the output terminal Vout may be connected to the 43rd metal wire ML4ML3. The third gate G3 and the third wiring ML3 are connected to the fourth wiring ML4.

The metal wiring may be a metal wiring horizontally, but may be a plug formed by a hole when connected vertically.

The input voltage Vdd is output to the output terminal Vout only when the threshold voltage is lower than the first input terminal Vin1 and the second input terminal Vin2, respectively, and is not turned on. (Vg) is output. That is, the high value is output only when both the first and second input voltages are low. Otherwise, the ground voltage Vg is output. Therefore, FIG. 7 and FIG. 8 become NAND circuits.

Although the present invention has been described with reference to the embodiments with reference to the drawings, this is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined only by the appended claims.

1 is a cross-sectional view showing a logic device according to an embodiment of the present invention.

2 is an I-V characteristic curve of the first gate G1 and the second gate G2 when a negative voltage is applied to the body gate Vbody in the logic device according to the exemplary embodiment of the present invention.

3 is a view for explaining the operation of the logic device according to an embodiment of the present invention.

4 is an inverter logic diagram according to an embodiment of the present invention.

5 is a cross-sectional view of a noah logic device according to another embodiment of the present invention.

FIG. 6 is a noah logic element diagram of FIG. 5.

7 is a cross-sectional view of a NAND logic device according to another embodiment of the present invention.

FIG. 8 is a NAND logic device diagram of FIG. 7.

Claims (13)

A first semiconductor oxide transistor having a first semiconductor oxide channel layer; A second semiconductor oxide transistor having a second semiconductor oxide channel layer; And The first transistor and the second transistor are vertically stacked, and a body gate disposed therebetween. And when a negative voltage is applied to the body gate, threshold voltages of the first transistor and the second transistor move in a positive direction. The method of claim 1, And a first gate oxide formed between the body gate and the first channel layer, and a second gate oxide formed between the body gate and the second channel layer. The method of claim 2, And the second gate oxide thickness is greater than the first gate oxide thickness. The method according to claim 2 or 3, The first transistor acts as an enhancement mode transistor and the second transistor acts as a depletion mode transistor according to the negative voltage applied to the body gate. The method of claim 4, wherein A first metal wire connecting the drain of the first transistor and the source of the second transistor; And And a second metal wiring connecting the drain first metal wiring of the second transistor and the second gate. A ground voltage source is connected to a source of the first transistor, an input voltage source is connected to a drain of the second metal wiring transistor, an input terminal is connected to the first gate, and an output terminal is connected to the first metal wiring. device. The method of claim 1, And a first channel layer and a second channel layer each having a thickness of 100 ns to 1000 ns. A first semiconductor oxide transistor having a first semiconductor oxide channel layer; A second semiconductor oxide transistor having a second semiconductor oxide channel layer on the first transistor; A third semiconductor oxide transistor having a third semiconductor oxide channel layer on the second transistor; And a body gate disposed between the first transistor and the second transistor, And when a negative voltage is applied to the body gate, threshold voltages of the first transistor and the second transistor move in a positive direction. The method of claim 7, wherein And a first gate oxide formed between the body gate and the first channel layer, and a second gate oxide formed between the body gate and the second channel layer. The method of claim 8, According to a negative voltage applied to the body gate, the first transistor and the second transistor serve as an enhancement mode transistor, and the second transistor and the first transistor are connected in series with a source and ground voltage source of the third transistor. Wherein the logic element is a noah circuit. The method of claim 9, A first metal wire connecting the drain of the first transistor and the source of the second transistor; A second metal wire connecting a drain of the second transistor and a source of the third transistor; And And a third metal wiring connecting the drain 2 metal wiring of the third transistor and the gate of the third transistor. An input voltage source is connected to a drain of the third transistor of the third metal wiring, a first input terminal is connected to a gate of the first transistor, a second input terminal is connected to a gate of the second transistor, and the second Logic device connected to the output terminal to the metal wiring. The method of claim 8, The first transistor and the second transistor act as enhancement mode transistors according to the negative voltage applied to the body gate, and the second transistor and the first transistor are connected in parallel to the source and ground voltage sources of the third transistor. Wherein the logic element is a NAND circuit. The method of claim 11, A first metal wire connecting the source of the first transistor and the source of the second transistor; A second metal wiring connecting the drain of the first transistor and the drain of the second transistor; A third metal wiring connecting the drain of the third transistor and the gate of the third transistor; And A 43rd metal wire electrically connecting the second metal wire and the source of the third transistor; And And a fourth metal wiring connecting the gate of the third transistor and the third metal wiring. A ground voltage source is connected to the first metal line, an input voltage source is connected to a drain of the third metal line transistor, a first input terminal is connected to the first gate, and a second input terminal is connected to the second gate. And a logic terminal connected to the output terminal of the 43rd metal line. The method of claim 7, wherein And the first channel layer, the second channel layer, and the third channel layer are each 100 μs-1000 μs thick.

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