JPS6024595B2 - Semiconductor devices and injection logic semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of field effect transistors (FETs), particularly static transfer transistors (SITs), which are incorporated into discrete devices or as part of integrated circuits, and which have improved properties. The present invention provides semiconductor devices and semiconductor integrated circuit devices.

FIG. 1 is a cross-sectional view of an injection logic integrated circuit (SITL) using a subordinate SIT as a driving transistor, and is composed of a lateral pnp bipolar transistor L and an inverted n-channel SITT2.

When a positive signal enters the signal input terminal 4, the current from the power supply connected to the emitter (injector) terminal of the Pnp bipolar transistor T, flows through the emitter p+ region 15.
The hole current flows from the base n region 13 to the collector p region 14, which is the gate of the SIT and is connected to the input terminal 4, increasing the gate potential of the SITT 2, and at the same time, holes flow into the channel region 13 of the SIT. flows in. Therefore, the source 12 and drain 11 of SIT
The current flowing between SI increases rapidly due to the decrease in resistance, and SI
T is turned on and the drain voltage decreases. However, the OFF signal (approximately 0 to 0.3V) is applied to input terminal 4 again.
), the potential of the gate region 14 decreases, the resistance increases, the current decreases, the transistor becomes off, and the drain voltage increases. SITLs that operate in this manner have small capacitance, low on-resistance, and large off-resistance, so the power consumption required for logic operation is 12 L compared to conventional injection type logic integrated circuits (12L) using bipolar transistors. /1
0 or less, making it an epoch-making logic integrated circuit.

However, when the SIT transitions from the on state to the off state, from the gate p+ region 14 to the n- region 1 to a small extent.
Due to the accumulation effect of the holes injected into the circuit 3, the logic speed did not necessarily improve, and was only about 10 to 5 marks sec at most. Particularly in the case of SITL, excess holes accumulated in the n-region 13 are either diffused back to the gate p-region 14 or diffused to the drain and source n-regions 11 and 12, recombined, and disappeared. The logic speed is improved because the diffusion rate is slow and the lifetime of the n- region is long due to the low impurity density. It is preventing this. Furthermore, the drain n region 11 and the gate p
One of the causes is that the + region 14 directly forms a pn junction, making the capacitance larger than necessary. This phenomenon is not limited to injection-type SITL's, but is a similar problem in other logic integrated circuits using SIT, such as TTL, ECL, or memory, as well as in analog integrated circuits and individual elements. At present, the advantages of good high-frequency characteristics and low control power consumption cannot be fully utilized. This is an important problem not only for SITs but also for FETs having almost the same structure. The present invention provides a novel SIT or FET that eliminates the disadvantages of the conventional SIT or FET described above.
The present invention provides an IT or FET structure to realize an SIT or FET with improved high frequency characteristics.

Furthermore, in the logic integrated circuit partially including the SIT or FET according to the present invention, while maintaining the advantage of low power consumption,
It also enables high-speed logic. The present invention provides an SIT (or FET) structure that promotes the annihilation process of excess minority carriers injected into a low impurity density channel region.
). The present invention will be described in detail below with reference to the drawings.

FIG. 2a is a cross-sectional view of one structural example of a SIT or FET according to the present invention, showing one unit. one main electrode 1 and 2
And between the regions 11 and 12, relatively low impurity density semiconductor regions (n regions) 131, 13, and 132 are present, passing through the p+ gate region 14.

In a normal SIT or FET, the n region 13 is almost uniformly sandwiched between the n+ regions 11 and 12, but the relatively high resistance layer 131 inserted according to the present invention
, 132 have the following effects. That is, although the potential distribution for electrons is shown in FIG. 2b, even when no voltage is applied to the gate, the high resistance layer 131 is , 132 has the effect of drawing back the holes accumulated in the gate p+ region. At that time, the high resistance layer 131
, 132, at least at the voltage between the main electrodes, electrons flow in large quantities, holes are easily recombined, and an electric field due to the diffusion potential is generated in all regions other than the channel.
A thickness and impurity density of 1,132 is chosen. Of course, it is more desirable for this electric field to occur in the channel portion as well in order to improve the frequency characteristics. Therefore, the high resistance layer may be inserted adjacent to the gate p+ region 14 as shown in FIG. 2a (example of high resistance layer 131).
, and n-region 13 (example of high-resistance layer 132). The point is whether the depletion layer reaches exactly the main electrode n+ regions 11 and 12 due to the diffusion potential of the junction with the gate p+ region.
This has been fully achieved. (In Figure 2 a, d,
, d2≦depletion layer thickness due to diffusion potential). Therefore, n(
or n- or intrinsic convenience n) region 131, 13, 1
32 may all have uniform impurity density,
Alternatively, it may have a stepped or gentle impurity density distribution. In particular, the impurity density in the n region is determined depending on the desired characteristics of the device. Furthermore, n regions 131, 13, 1
Although it is effective to add impurities such as AuCuFe to 32 to shorten its life, this is not necessarily preferable since it also has adverse effects such as an increase in reverse current. To describe one embodiment of the SIT according to the present invention, the gate p+ region 14 has a diameter of about 15 mm and an interval of 10 µm, the impurity density of the n- region 13 has an impurity density of n = 3 × 1 and 3 arc-3, and a thickness of about 10 µm, n - area 131 n=8×1
If the thickness of N-regions 132 and 2-3 is approximately 15 cm, and the thickness of n-region 132 is approximately 7 cm with the same impurity density, then n-regions 13, 13
Compared to when 1,132 was set to n=3×1 and 3−3, the switching speed was improved by about twice when the gate voltage was applied in the forward direction. Similarly, by selecting the impurity density and dimensions, the product of the source negative feedback resistance tai and the individual conversion conductance Gm is 1
If it is made larger, an FEH with improved switching time having pentode characteristics can be obtained. It is also possible to form the rain electrode portion into a Schottky junction. Second
The structure in figure a can be realized as follows. Referring to FIG. 3, first, n-layers 131 and 13 having desired impurity density and thickness are epitaxially grown on an n+Si substrate 11.
. After forming an oxide film 16 on the surface of the n-type growth layer 13, the oxide film is selectively etched by photolithography, and a P-type impurity (for example, B) is selectively diffused into the region 14 that is to become a gate region b. The oxide film 16 is removed and the n-type epitaxial growth layers 13' and 132 are formed again.c. Growth layer 13
' has a slightly high impurity concentration to suppress auto-doping of impurities from the gate p+ region 14, and the gate p+ region also extends to the growth layer 13' side due to auto-doping and heat treatment during growth. An n+ region 12 is obtained by n+ diffusion or n+ epitaxial growth, a part of the gate region 14 is exposed to the surface by selective etching of Si, and AI is deposited to form each electrode.d. In this case, the drain 1, source 2, and gate 4 are of an erect type, but it goes without saying that the drain and source can be exchanged.
Although an example having a buried gate has been described above, the cross-sectional shape of the gate is not limited to a circular shape, but other shapes (for example, an elliptical shape, a rectangular shape) are also possible, and a parallel cylinder shape, a mesh shape, and other arrangements are also possible. Furthermore, a P channel can also be realized by reversing the conductivity type of each region. FIG. 4 is another specific example of the present invention, and shows a unit cross section of a structure (surface type and notch type) in which the gate is exposed on the surface.

A is an example in which the present invention is applied to an inverted type in which a source electrode 2 and an n+ region 12 are formed in F, and a p+ region 14 and a drain n+ region 11 are formed with relatively low impurity at a distance d. Electrodes 4 and 1 are provided on the same surface of the n (or n-) density region 131, respectively. Also gate p
The ten region 14 and the source n ten region 12 are the high resistance layer 132.
They are in contact with each other at a distance. The distance d and also the thickness of the depletion layer due to the diffusion potential of the gate junction are suppressed. Especially in the case of SIT, the density of undeliverables is set to 131.
If it is set lower on the region 132 side, a potential barrier against majority carriers is formed on the side closer to the source n+ region 12, so even in an inverted type, the voltage amplification factor can be increased, and o
n-resistance can be lowered. Of course, this structure can also be applied to an upright type in which the source electrode is on one side. This structure can be easily manufactured using techniques such as continuous epitaxial growth, selective diffusion, and ion implantation. b is also a surface type, and is an upright type SIT (or FET) in which the source electrode 2 and the gate electrode 4 are provided on the same surface. The high resistance region 131 is formed mainly surrounding a relatively low impurity density region 132 which becomes a channel, and the distance between the gate p+ region 14 and the source n+ region 12 and drain n+ region 11 is also d.
, are opposed to each other with the high resistance region 131 interposed therebetween. d
,, also satisfies the depletion layer thickness due to the diffusion potential. This structure can be easily realized by forming a channel portion by diffusion or ion implantation. An example has been described above in which an n-type or intrinsic high-resistance layer is inserted between the gate region and the source and drain regions, but a p-type high-resistance layer may also be used.

c is a p-type high resistance layer 141 around the gate p-type region 14;
This is an example in which a depletion layer is inserted, and due to the junction with the drain n+ region 11, the depletion layer spreads toward the high resistance layer 141 side due to the diffusion potential and reaches the gate p+ region 14. source n
+ region 12 and gate p+ region 14 face n (n- or intrinsic) region 13 with p-type high resistance layer 141 interposed therebetween. This is an example in which a depletion layer is formed. The protruding region 121 in the source n region is an example of how it is possible to obtain majority carrier injection efficiency and a large voltage amplification factor without increasing the capacitance between the gate and the source, and it reduces the electric field caused by the diffusion potential. By eliminating the small area, the gist of the present invention is made more effective. Formation of the p high resistance layer can be achieved by simultaneous diffusion of impurities with large diffusion coefficients and impurities with small diffusion coefficients, double diffusion of the same impurity, ion implantation, etc. when forming the gate p+ region. d is an example in which the present invention is applied to a notched structure, in which a p-type high resistance layer 141 is formed by forming a gate p+ region 14, a source n+ region 12, and a drain n+ region 11.
It was inserted in the common part between the two. In this example, the gate electrode 4 is in contact with the p-region 14 on the side wall of the recess and is insulated from the bottom surface of the recess by the insulator 6, but the present invention can be applied to all the notch structures that have already been proposed. In the case of a notch structure, the distance between the electrode on the top surface of the protrusion and the electrode on the side surface or bottom surface is relatively long, so the present invention is more effective. FIG. 5 shows the manufacturing process of the structural example shown in FIG. 4d. An n (or n- or intrinsic) epitaxial growth layer 13 is provided on an n+Si substrate 11, a p-type high resistance layer 141 is formed by selective diffusion, and the p-type high resistance layer 141 is further buried with an n epitaxial growth layer 13' as shown in FIG. Heat treat until layer 141 has the desired dimensions. Thereafter, the n+ region 12 is selectively diffused, and at the same time a thick oxide film 161 is formed on the surface. a. The oxide film 161 is selectively etched, and Si is directionally etched using the remaining oxide film 161 as a mask to form a recess. Directional etching can be performed by plasma etching, KOH, etc. Oxidation is performed again, the oxide film on the bottom of the recess is removed by directional etching, and p is diffused into the bottom surface. b. The bottom of the recess is dug deeper by directional etching again. , penetrates the p diffusion layer 4. After depositing an insulator 6 on the bottom of the recess by directional vapor deposition, sputtering, etc., a contact hole for the n+ region envelope 2 is opened in the upper surface, and each electrode is formed by directional deposition again. Although several examples of structures according to the present invention have been shown above, the high-resistance layer inserted between the gate and the source or between the gate and the drain may be of the same conductivity type as the channel, the opposite conductivity type, or an intrinsic semiconductor layer. Furthermore, there may be a difference in impurity density or distribution.

Furthermore, the thickness of the high resistance layer to be inserted may be all or part of the low impurity density region between the high impurity density regions of each electrode, and if the diffusion potential makes all the areas between the high impurity density regions a depletion layer, the desired thickness is achieved. is achieved, and various combinations of the above specific examples are also possible. It is also relatively effective to add impurities to the high resistance layer to shorten its lifetime. Although the n-channel example has been described above, the same applies to the p-channel, and the source electrode and drain electrode are interchangeable and can be selected depending on the purpose. Furthermore, the drain electrode can be formed into a Schottky junction, which is effective in logic circuits. Although the gate junction has been described using a pn junction as an example, a Schottky junction can be similarly applied. Furthermore, the present invention can be applied to both SIT and FET, but since the present invention has the effect of reducing the accumulation effect of minority carriers and lowering the capacitance of each electrode, both in the forward gate voltage region and the reverse gate voltage region. High frequency is achieved. It is natural from the gist of the present invention that the present invention can be applied not only to SITs or FETs having a vertical structure, but also to a rattan structure.

FIG. 6 shows an example of a horizontal structure, in which the distance d between each electrode (1: drain, 2: source, 4: gate) is set so that the distance d,... is less than the depletion layer thickness due to the diffusion potential. or an impurity density of 132 is selected. In this example, a has a junction type, b has a Schottky junction type, and wealth 4? Wandering’
is the channel opposite conductivity type region. The method of inserting the high resistance layer 31 or 132 is not limited to this.
Variations of the various embodiments described above are possible. FIG. 7 is an example in which the present invention is applied to an SIT' having a low base resistance type structure.

In the diagram a, the buried gate region base 4 is interconnected with a low impurity density thin layer region 24 of the same conductivity type. This thin layer 24 (or gate region 1
4) as the high impurity density region 11 adjacent to the main electrodes 1 and 2;
A high resistance layer 131 or 1
32 has been inserted. The impurity density t thickness is selected like the depletion layer thickness due to the diffusion potential d and d2. b is an example applied to a surface type, and can be considered almost the same as a. In this case, the inserted high-resistance layer 141 has the same conductivity type as the gate region 4 and crosses the channel at the same time. Examples of basic logic configurations using the electrostatic induction transistor of the present invention are shown in FIGS. 8 and 9.

Figure 8 shows an NO in which three units of SITL using the electrostatic transfer transistor of the present invention as the driving transistor are combined.
They are an R gate and an OR gate. FIG. 8b shows an example in which the load transistor in FIG. 8a is an insulated gate electrostatic conduction transistor instead of a lateral bipolar transistor. T. , T2, L are static induction transistors of the present invention. FIG. 9 shows a field effect transistor Q. . . . Static induction transistor T. of the present invention using Q6.・・・・・・T,. This is an example of a 3-input NOR gate and an OR gate. As described above, the present invention suppresses the minority carrier accumulation effect by inserting a high resistance layer between each electrode and forming an electric field due to the diffusion potential of the junction in the high resistance layer and the channel low impurity density region. , which greatly reduces the SI
The present invention is not only effective when applied to TFETs, but is even more effective when applied to integrated circuits containing these.

In particular, logic integrated circuits using a vertical gate voltage region,
For example, it can be applied to PL, ECL, NTL, TTL, FEL, and other memories (including RAM, ROM, etc.) to achieve low power consumption and high-speed operation. Furthermore, high frequency operation and high voltage resistance are being promoted in other integrated circuits.
Furthermore, the effects of the present invention are significant even in the reverse gate voltage region. Semiconductor materials include not only Si but also Ge and GaAs.
Equal m-V compounds, mixed crystals thereof, etc. can be used. In addition, the drawing states, ``Although only one unit cross section is shown, depending on the purpose of use,
Needless to say, it can be transformed into one unit, several units, and multi-channel.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a conventional SITL, FIGS. 2 a and b are a specific example of the present invention, and FIGS. 3 a to d are diagrams for explaining an example of a method for manufacturing the structure of FIG. 2 a. , FIGS. 4 a to d are specific examples of the present invention, and FIGS. 5 a to c are one of the structural examples of FIG. 4 d.
Diagrams for explaining the manufacturing method, FIGS. 6 a and b are specific examples of the present invention, FIGS. 7 a and b are specific structural examples of the present invention, FIGS. 8 a and b are basic logical configuration examples, and FIGS. Figure 9 shows an example of the basic logical configuration. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] 1. In a field effect transistor or static induction transistor having a source, a drain, and a gate and having a forward gate voltage region as its main operating region, at least one region between each of the source region and the drain region and the gate junction. A high-resistance layer is inserted on both sides, and the thickness of the high-resistance layer is made equal to or less than the thickness of the depletion layer due to the diffusion potential of the gate junction, so that the accumulation effect of minority carriers is reduced by the electric field due to the diffusion potential. semiconductor devices. 2. The semiconductor device according to claim 1, wherein an impurity that shortens the carrier life is added to at least a common portion of the high-resistance layer. 3. In an injection logic semiconductor integrated circuit in which a driver transistor and an injector transistor for injecting carriers into a specific semiconductor region of the driver transistor are integrally formed in a common semiconductor wafer, the driver transistor has a forward gate. It is a field effect transistor or a static induction transistor whose main operating region is a voltage region, and a high resistance layer is inserted between each of the source region and drain region of the driver transistor and the gate junction at least on both sides. An injection logic type semiconductor integrated circuit characterized in that the thickness of the resistance layer is less than or equal to the thickness of a depletion layer due to a diffusion potential of a gate junction, and the specific semiconductor region is a gate of the driver transistor. 4. The injection logic type semiconductor integrated circuit according to claim 3, wherein an impurity that shortens the carrier life is added to at least a common portion of the high-resistance layer.