JPH05267674A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce ON resistance, safely control a main current, and improve switching speed. CONSTITUTION:The MOS structure using an inversion layer which has been used for controlling an electron current in the conventional technique is not adopted but the following is used; as the channel structure, a region (channel region 100) having the same conductivity type as a source region 2 and a drain region 1 is sandwitched by an insulating gate 6 and a Schottky junction 8, and the potential height for the majority carrier in said region 100 is controlled by the potentials of the gate 6 and the junction 8. A region 10 of the opposite conductivity type for injecting minority carrier is individually formed to control the conductivity of the drain region 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a normally-off type MOS power device using a storage layer as a channel, and more particularly to a semiconductor device driven in a bipolar mode.

[0002]

2. Description of the Related Art The lower the on-resistance of a power device, the better. A normal power bipolar transistor has a low on-resistance due to the conductivity modulation effect, but a single transistor has a low h _FE . That is, in a low voltage high current operation region of most single bipolar transistors,
Since h _FE = 10 at most, a base current of 10 A is required to pass a main current of 100 A. On the other hand, since the MOS power device is a voltage control type, it does not require a large amount of energy to control the main current.
Instead, the on-resistance is orders of magnitude higher than that of bipolar transistors because it is unipolar.

There is a device described in US Pat. No. 4,364,073 as a device having both advantages. This is an IGBT (Insulated Gate Bipolar Transis)
tor: Insulated gate type bipolar transistor). FIG. 21 is a diagram showing a typical cross-sectional structure of the above device. In FIG. 21, 1 is an n-type drain region, 2 is an n + type source region, 3 is a gate insulating film, 4 is a gate electrode, 5 is an interlayer insulating film, 7 is a source electrode, 14 is a drain electrode, and 15 is p-type. Base region, 16
Is a contact p for keeping the p-type base region at the ground potential.
The + region, 18 is a p-type anode region. The above structure is a so-called DMOS structure. In summary, such an IGBT connects a pn junction to the drain region 1 of the DMOS structure, and in operation, injects minority carriers from the pn junction into the drain region 1 having a high resistance, thereby reducing the resistance by the high injection level state. To do. The p-type anode region 18 is provided for this purpose.

The operation of the above device will be briefly described below. The n-type drain region 1 has a relatively high resistance, and in the cutoff state, the depletion layer spreads to maintain the breakdown voltage.
From this state, an appropriate electric potential is applied to the gate electrode 4, and MO
When electrons start flowing from the S structure toward the p-type anode region 18, holes are also injected from the p-type anode region 18 into the n-type drain region 1. As a result, when the inside of the n-type drain region 1 is in a high injection level state, the conductivity becomes high and the on-resistance of the device sharply drops. This device is characterized in that the bipolar operation is controlled by the MOS gate in this way.

However, this device also has the following inevitable drawbacks. First, the holes existing in the drain region 1 at the time of turn-off can flow away to the source electrode 4 through the p-type base region 15, but the electrons can be emitted in the p-type region.
Due to the presence of the mold anode region 18, it cannot flow away to the drain electrode 14 and must disappear in the drain region. Therefore, there is a drawback that the turn-off time becomes long. Second, the structure of this device has a parasitic device (p
-Type anode region 18)-(n-type drain region 1)-(p
There is a pnpn thyristor consisting of the type base region 15)-(n + type source region 2). The flow of the hole current during the normal operation is, as indicated by the solid arrow in FIG. 21, (p-type anode region 18) → (n-type drain region 1) → (p-type base region 15) → (contact p + In the region 16), as the amount of hole current increases, the potential of the p-type base region 15 around the n + -type source region 2 increases,
Pn formed by the type base region 15 and the n + type source region 2
When the junction is in the forward bias state, holes flow into the n + type source region 2 as shown by the broken line arrow in FIG. Then, the above parasitic thyristor operates,
In the so-called latch-up state, current continues to flow and the controllability of the gate electrode is lost. In order to prevent the above phenomenon, the arrangement of each region around the n + source region 2 is devised, or the n + region is inserted between the p-type anode region 18 and the n-type drain region 1 to increase the amount of holes injected. Methods such as suppressing or introducing a lifetime killer into the n-type drain region 1 are taken. Lifetime Killer is the first turn
It is also effective in reducing the off time. However, although the latch-up phenomenon can be suppressed to some extent by these devices, all of these devices have the adverse effect of increasing the on-resistance of the device, and as a result, the feature of the device such as low on-resistance due to bipolar operation is reduced. Has become.

[0006]

As described above, the conventional single bipolar transistor has a problem that the ON resistance is low but a large current is required to drive the element. Further, the MOS transistor is of the voltage control type, which can control the main current with a small amount of energy and has a high switching speed but a high on-resistance.

An IGBT having both properties
Although the control power is similar to that of a MOS transistor and the on-resistance is low in principle, there is a problem that the on-resistance cannot be lowered sufficiently in order to avoid latch-up of the parasitic thyristor. As described above, each of the conventional devices has advantages and disadvantages, has a low on-resistance, can safely control the main current, and is difficult to realize an element having a high switching speed.

The present invention has been made to solve the problems of the prior art as described above, and has a low on-resistance.
An object of the present invention is to provide a semiconductor device capable of safely controlling a main current and having a high switching speed.

[0009]

In order to achieve the above object, the present invention is constructed as described in the claims. That is, in the present invention, the gate electrode is formed in contact with one main surface of the semiconductor substrate of the first conductivity type, which is the drain region (e.g., corresponding to 1 in FIG. 1) and the surface of which is covered with an insulating film. An insulated gate (e.g., corresponding to 6 in FIG. 1) and a channel region of the first conductivity type formed in contact with the drain region and the insulated gate (e.g., FIG. 1).
100)) and a source region of the first conductivity type formed so as to be in contact with the insulated gate and the channel region and not with the drain region (e.g., corresponding to 2 in FIG. 1).
And makes ohmic contact with the source region, and
The channel region and the drain region are in contact with the source electrode (for example, 7 in FIG. 1) made of a metal forming a Schottky junction, the drain region, the contact with or in the vicinity of the insulated gate, and the source. A second conductivity type region (e.g., corresponding to the p-type region 10 in FIG. 1) formed so as not to contact the region and the source electrode;
The second conductivity type region is in ohmic contact with another electrode independent of the source electrode (e.g., corresponding to the injection electrode 12 of FIG. 1), and has the gate electrode (e.g., FIG. 1).
(Corresponding to No. 4) is composed of a metal or a high-concentration second-conductivity-type semiconductor.

[0010]

As described above, in the present invention, the MOS using the inversion layer used in the prior art for controlling the electron current.
Instead of adopting a structure, as a channel structure, a region of the same conductivity type as the source region and drain region is sandwiched between an insulated gate and a Schottky junction, and the potential of both is controlled to control the height of the potential for majority carriers in the same region. A region of opposite conductivity type for injecting minority carriers is separately provided to control the conductivity of the drain region. With the above configuration, I
The bipolar operation can be controlled by the insulated gate without having a parasitic thyristor such as GBT.
Therefore, the on-resistance can be reduced, the main current can be safely controlled, and the switching speed can be increased.

[0011]

EXAMPLES The present invention will be described below based on examples.
FIG. 1 is a sectional view showing a first embodiment of the present invention. Figure 1
In the figure, 1 is an n-type drain region, 2 is an n + type source region, 3 is a gate insulating film, 4 is a gate electrode, and is made of p + type conductive polysilicon or metal. Reference numeral 5 is an interlayer insulating film. The above items 3, 4, and 5 will be collectively referred to as an "insulated gate" and will be numbered 6. Since FIG. 1 is a schematic view, the bottom of the insulated gate 6 is illustrated as square, but the actual corner is preferably rounded, and the electric field concentration can be avoided, which is preferable. Further, 7 is a metal serving as a source electrode, which is in ohmic contact with the n + type source region 2. The insulated gate 6 is embedded in a groove dug such that the side wall is substantially vertical from the surface of the substrate, and n
The + type source region 2 is in contact with the insulated gate 6. Also,
The source electrode 7 is buried in a groove that is dug such that the side wall thereof is substantially vertical with a certain distance from the side wall of the insulated gate 6. The source electrode 7 forms a Schottky junction with the n-type drain region 1. The Schottky junction is numbered 8. A mask material 9 is used to realize the structure of FIG. 1
A drain electrode 4 is in ohmic contact with the n + type substrate region 13. In addition, the n-type drain region 1
In FIG. 3, the part sandwiched between the insulated gate 6 and the Schottky junction 8 is called the “channel region” of this semiconductor device,
Reference numeral 100 is attached. The gate electrode 4 is made of p + type polysilicon or metal, and even if the gate potential is grounded,
Due to this and the effect of the Schottky junction 8, the potential of the channel region 100 for electrons is raised and depleted. In FIG. 1, L is a channel length, which is defined as the distance from the boundary with the n + type source region 6 along the gate insulating film 3 to the bottom of the groove in which the source electrode 7 is buried. H is the channel thickness, and the channel region 10
0 is the distance from the Schottky junction surface to the gate insulating film interface. This channel thickness is an important amount for the semiconductor device of the present invention. As will be described later in detail, the ratio of the channel length L to the channel thickness H is set to a value that prevents the channel from opening even if the drain potential is increased to a desired value, for example, L / H> 2. ing.

Numeral 10 is a p-type region for injecting holes into the n-type drain region 1. Reference numeral 11 is given to the pn junction between the p-type region 10 and the n-type drain region 1. 1
An injection electrode 2 is in ohmic contact with the p-type region 10. The p-type region 10 may or may not be in contact with the insulated gate 6. Further, the distance between the two insulated gates sandwiching the p-type region 10 may not be the same as the distance between the two insulated gates sandwiching the source electrode. However, at the position of the p-type region 10, when the channel opens from the cut-off state of the element and an electron current flows, the potential of the drain region near the p-type region 10 becomes low, and a positive potential is applied to the p-type region 10.
It must be located at a position where holes can be sufficiently injected from the mold region 10 to the drain region 1. The p-type region 10 may be in contact with the insulated gate 6, but when in contact, the electron storage layer formed around the insulated gate 6 in the conductive state is in contact with the p-type region 10 and the source electrode 7. There is a possibility that useless current may flow between the injection electrodes 12. Reference numeral 13 is an n + type substrate region. Since the breakdown voltage of the device itself is realized by forming a depletion layer in the n-type drain region 1, the thickness required for the device to obtain a desired breakdown voltage is at most several to several tens of μm. On the other hand, in order to maintain the physical strength of the chip, a thickness of several hundreds μm is required. If this region is made up of a region having the same low impurity concentration as the drain region, the on-resistance will be increased. Therefore, it is preferable that the impurity concentration of the region not involved in maintaining the breakdown voltage is as high as possible. The n + type substrate region 13 is a region that exists for this purpose and is not essential for the function of the device.

Next, the operation of the channel region 100 of FIG. 1 will be described in comparison with the conventional structure. 5 and 6
21 is a band diagram in the B-B cross section in FIG. 21, that is, a diagram showing a band structure of a channel of a conventional n-channel MOS structure. FIG. 5 shows a cutoff state at a gate potential of 0 V, and FIG. The potential is an appropriate positive potential and indicates a conductive state. For comparison with the present invention, the gate electrode was p + type polysilicon. As shown in FIG. 5, when the gate potential is 0 V, the p-type base region has a high potential with respect to electrons, and therefore electrons cannot flow. Then, as shown in FIG. 6, when an appropriate positive potential is applied to the gate electrode, the potential of the p-type base region near the gate insulating film becomes low, an inversion layer is formed, and an electron is generated between the source region and the drain region. Electric current can flow. On the other hand, FIG. 7 and FIG. 8 are views showing the band structure of the AA cross section in FIG. In FIG. 7, the gate potential is 0
The V state indicates a cutoff state, which corresponds to the state shown in FIG. Further, FIG. 8 shows the conduction state of the element in which the gate potential becomes an appropriate positive potential.
Corresponding to the state of. In the state of FIG. 7, the channel region 100, which is originally n-type, has a barrier height φ of the Schottky junction 8.
_B and the potential φ _{G at the} bottom of the conduction band of the p + -type polysilicon that is the gate electrode 4 measured from the Fermi level increase the potential and prevent electrons from flowing. In the state of FIG. 8, an appropriate positive potential is applied to the gate electrode, the potential of the interface of the n-type region in contact with the gate insulating film becomes low, and an accumulation layer is formed so that an electron current can flow. This storage layer is different from the usual one and is compressed by the effect of the adjacent Schottky junction. Therefore, the cross section of the channel region 100 shown in the figure has only a depletion layer and an accumulation layer, and has no neutral region. If the gate potential is removed, the channel region 100 becomes a depletion layer only.

Next, the operation of the device shown in FIG. 1 will be described. Figure 1
In the element (1), the source electrode 7 is grounded, and the drain electrode 14 is applied with an appropriate positive potential. First, the case where the drain potential is relatively small will be described. As described above, when the gate electrode 4 is grounded, the channel region 10
At 0, a Schottky barrier and a potential barrier due to the effect of the gate electrode material exist, and no electron current flows. The p + type polysilicon of the gate electrode material may be replaced with n + type polysilicon, but in that case, the element becomes a normally-on type and a negative potential must be applied to cut off the main current. Next, when a proper positive potential is applied to the gate electrode 4, an accumulation layer is formed at the interface of the gate insulating film in the channel region 100, and an electron current flows. When the injection electrode 12 is grounded, the element operates in unipolar mode. However, when a positive potential is applied to the injection electrode 12 and the pn junction 11 is forward-biased, holes are injected from the p-type region 10 into the n-type drain region 1 and the n-type drain region having a relatively low impurity concentration is injected. In No. 1, the conductivity is dramatically improved. The injection electrode 12 may be constantly given a constant positive potential. The injection current does not flow when the drain potential is relatively high and the pn junction 11 is reverse-biased even in the cutoff state or in the conductive state, so that the operation of the main current is not affected. When the drain potential becomes lower than the injection electrode potential, the pn junction is forward biased and holes are naturally injected. In addition, the injection electrode 1
The potential of 2 may change during the switching operation.
Conventionally, in a bipolar transistor, there is a method of accelerating the elimination of holes by swinging the base potential negatively in order to shorten the turn-off time. Similarly, also in the device of this embodiment, the potential of the injection electrode 12 can be made negative at the time of turn-off to help eliminate holes from the drain region 1. At this time, if the injection electrode potential is changed from positive to negative immediately after the gate is turned off, the power consumption at the time of switching can be reduced. In addition,
The change in the injection electrode potential at this time may be synchronized with the change in the gate electrode potential, or may be ahead of the potential to some extent. In the conventional bipolar transistor, holes flow only to the base electrode, but in the case of the present embodiment, holes flow to the source electrode 7 that is in direct Schottky contact with the drain region 1 in addition to the injection electrode 12. You can also get out of the device quickly.

Next, the surface structure of the device will be described.
18 to 20 are cross-sectional views of the device taken along a plane perpendicular to the plane of the drawing including the line BB in the cross-sectional views of FIGS. 2 to 4 showing the above-mentioned FIG. 1 and other embodiments described below. (Surface pattern). The surface pattern can have a striped configuration as shown in FIG. Further, the insulated gate 6 may have a lattice shape as shown in FIG. 19 or a honeycomb shape as shown in FIG. In these figures, the channel region (the same position as the source region 2 in the figure) and the source electrode 4
The quadrangular and hexagonal corners of are rounded.
This is to make the thickness of the channel region uniform. That is, the thickness H of the channel region (the shortest distance from the surface of the Schottky junction 8 to the surface of the insulated gate 6) is formed to be almost constant throughout. Further, in the case of FIGS. 19 and 20, the scattered p-type regions 10 can be connected to each other by a multilayer wiring technique. Further, the concentration of holes injected from the p-type region 10 to the n-type drain region 1 may be considered to be substantially uniform within a range of several tens of μm from the p-type region 10, but may start to attenuate when the distance is 100 μm or more. It has been revealed by numerical calculation.
Therefore, in order to make the device operate efficiently,
9 and FIG. 20, the p-type regions 10 may be arranged at appropriate intervals so that the distance between a certain p-type region 10 and the adjacent p-type region 10 is about several tens of μm. .. Of course, it doesn't matter if you are closer than that.

Further, as shown in FIG. 1, the embedded depth of the source electrode 7 is shallower than the depth of the insulated gate 6. This is to prevent holes filling the n-type drain region 1 from unnecessarily flowing into the source electrode 7 when the device is conducting. The reason will be described below. A depletion layer associated with the existence of the barrier exists near the Schottky junction. As an example, the impurity concentration of the n-type drain region 1 is 1 × 10 ¹⁵ cm to ³ and the Schottky barrier height φ _B.
Is 0.7 eV, the thickness of the depletion layer is about 0.75 μm. Therefore, if the depth of the source electrode 7 is set to the insulated gate 6
If it is equal to or deeper than that, the holes injected from the p-type region 10 will flow into the source electrode 7 when reaching the vicinity of the source electrode 7, and the conductivity modulation effect will be reduced.
Although the depth of the buried source electrode 7 is determined by the design of the channel length, the depth of the insulated gate 6 is deeper than this, and by making the depth about the distance between adjacent insulated gates deeper, Holes can be suppressed from flowing into the Schottky junction.

Next, the conditions for the channel to have good current cutoff characteristics in the cutoff state of the device of this embodiment will be described. 9 to 11 are band diagrams of the AA cross-sectional view of FIG. 1, and for convenience, only show the presence of the Schottky barrier, the bottom line of the conduction band of the semiconductor region, and the insulating film. The gate electrode material will be described as p + type polysilicon. 9 to 11, φ _B is the height of the Schottky barrier, φ _G is the potential at the bottom of the conduction band of p + -type polysilicon, which is the gate electrode, measured from the Fermi level, E _g is the band gap of silicon, and t is t. _OX is a gate insulating film thickness. Note that the gate potential is 0 V, which is the cutoff state. In FIG. 9, there is no extreme value in the potential distribution in the cross section of the channel region 100 due to the synergistic effect of various amounts in the figure, the channel thickness H, the impurity concentration N _D of the n − region, etc., and conduction electrons are concentrated in the channel. There is no condition. Figure 10
Indicates that the potential distribution in the cross section of the channel region 100 has a minimum point, but the potential at the minimum value measured from the Fermi level is larger than E _g / 2, so conduction electrons do not exist near the minimum point. FIG. 11 shows the channel region 1
There is a minimum point in the potential distribution of the 00 cross section, and the potential of the minimum value measured from the Fermi level is smaller than E _g / 2, so it is a condition that conduction electrons exist near the minimum point. Under this condition, a considerable current will flow as a leakage current. Since the present invention is premised on a normally-off type element, various amounts such as the impurity concentration N _D of the channel region 100 and the channel thickness H must be selected so as not to satisfy the conditions shown in FIG. .. This condition can be easily obtained by solving a simple Poisson equation. As an example, when both φ _B and φ _G are about 0.6 V, the channel thickness H is 1 when N _D = 1 × 10 ¹⁵ cm to ³
It may be μm or less. Further, in FIG. 1, the potential of the channel region 100 in contact with the source region 6 is affected by the source region 6 and becomes low. It has been clarified by numerical calculation that the affected portion is from the boundary of the source region 6 toward the center of the channel region 100 to a distance of about the channel thickness H. on the other hand,
When a potential is applied to the drain electrode 14 close to the breakdown voltage,
The end of the channel region 100 facing the drain electrode 14 is also affected by the same effect and the potential is lowered. The region affected by this is also deepened by the channel thickness H. Therefore, in order to prevent the channel from opening even if the drain potential is applied up to the device breakdown voltage, the channel length L needs to be at least twice the channel thickness H, and if the margin is set to 3 to 4 times, It is enough. For example, when the channel thickness is 300 nm, the channel length L of about 1 μm is sufficient.

Next, FIGS. 12 to 17 are process drawings showing an example of a manufacturing method for realizing the structure of FIG. First, n +
The n-type drain region 1 is epitaxially grown to a desired thickness on the type silicon substrate region 13, and a mask material 222 is patterned on the surface thereof to form a U-shaped groove whose side wall is substantially vertical. This state is shown in FIG. Next, a gate insulating film 3 is formed on the inner wall of this groove to form a gate electrode 4 with p.
+ Type conductive polysilicon or an appropriate metal is buried, an interlayer insulating film 5 is formed on the upper portion, and an insulated gate 6 is formed. This situation is shown in FIG. Next, as shown in FIG. 14, some of the silicon surface is removed. This amount should just be channel thickness H or more. Next, as shown in FIG. 15, arsenic is ion-implanted in a predetermined place for the source region 2, boron is ion-implanted in a predetermined place for the p-type region 10 for hole injection, and heat treatment is performed. To form each region. Then, a mask material is deposited thereon so that the flat portion and the side wall have the same thickness, and the side wall 9 is formed by etching by anisotropic dry etching. This state is shown in FIG. Next, as shown in FIG. 17, the p-type region 10
While protecting the above portion with the mask material 200, the silicon substrate is etched almost vertically using the sidewall 9 as a mask this time to form a groove for filling the source electrode 7. Then, metal is deposited on the surface of the substrate and patterned to form the source electrode 7 and the injection electrode 12. Finally, the drain electrode 14 is formed on the back surface of the substrate to complete the shape of FIG.

Next, FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, in order to eliminate useless current flowing between the n + type source region 2 and the p type region 10 described above, the source of the portion adjacent to the p type region 10 with the insulated gate 6 interposed therebetween is removed. The area (2 'portion) is eliminated.

Next, FIG. 3 is a sectional view showing a third embodiment of the present invention. In this embodiment, the thickness d of the bottom portion of the gate insulating film 3 is made thicker than other portions. This has two effects. That is, one is that the storage layer is formed around the gate insulating film 3 when the channel is in the conductive state. However, if the insulating film at the bottom of the insulating gate 6 is made thicker, the storage layer on both sides of the insulating gate 6 is increased. Since the storage layer is separated, useless current can be prevented from flowing between the n + type source region 2 and the p type region 10. The second is
In the cut-off state, a strong electric field is applied to the bottom of the insulated gate 6, and the thick electric breakdown portion increases the electric breakdown strength.

Next, FIG. 4 shows a fourth embodiment of the present invention. In the embodiment of FIG. 1, when the p-type region 10 is in contact with the insulated gate 6, the n + -type source region 2 and the p-type region 10 are
It was mentioned earlier that a wasteful current will flow between and. Therefore, in this embodiment, the insulated gate 6 in the portion in contact with the p-type region 10 is another insulated electrode 19, and this insulated electrode 19 is in a floating state or fixed to a specific constant potential, or is connected to the injection electrode 12. Thus, the formation of the p-type inversion layer is avoided. At this time, the source region (2 'portion) may not be formed at the position in contact with the insulating electrode 19.

The characteristic actions and effects of the present invention described above are summarized below. 1. In contrast to the conventional MOSFET that uses the opposite conductivity type region as the channel structure, the existence of the parasitic device is unavoidable. On the other hand, according to the present invention, the channel structure uses the same conductivity type region. Do not create a parasitic device that affects the controllability of the. 2. Since the storage layer having a lower resistance than the inversion layer is used as the channel, the channel resistance is small. 3. In the conventional IGBT (for example, the device shown in FIG. 21), the pn junction exists in series in the main current path. Therefore, the drain potential should be lowered to about 0.7 V or less for maintaining the pn junction in the forward bias state. Could not be achieved, which was one of the factors limiting the reduction of on-resistance. On the other hand, in the present invention, since the pn junction for injecting the minority carriers into the high-resistance n-type drain region does not exist in the main current path, the current rise near the voltage 0 V in the voltage-current characteristic is linear. Yes, the on-resistance is as low as a single bipolar transistor. 4. Since the electrons and holes can quickly flow away at turn-off, the turn-off time is short. That is,
Since the electron current is controlled by the channel by the insulated gate, the electron current is promptly cut off as the gate potential changes, and the electrons remaining in the device can also quickly flow away to the drain electrode. In addition to the p-type region, holes can flow to the source electrode through the Schottky junction that is in direct contact with the drain region. Therefore, it is possible to turn off faster than a bipolar transistor or an IGBT. 5. The device of the present invention is a four-terminal device, but the electrode for injecting holes may be applied with a positive constant voltage,
The handling is almost the same as a normal three-terminal device.

[0023]

As described above, in the present invention, since the n-type region in which the potential is forcibly raised by the external force is used as the channel region, 1. 1. A parasitic device that affects the controllability of the gate electrode cannot be created. Low channel resistance, 3. 3. On-resistance is as low as that of a single bipolar transistor. Short turn-off time 5. The handling is almost the same as a normal three-terminal device, and many excellent effects can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an element structure of a first embodiment of the present invention.

FIG. 2 is a sectional view showing an element structure of a second embodiment of the present invention.

FIG. 3 is a sectional view showing an element structure of a third embodiment of the present invention.

FIG. 4 is a sectional view showing an element structure of a fourth embodiment of the present invention.

FIG. 5 is an energy band diagram for explaining a cutoff state of a channel region of a conventional n-channel MOS.

FIG. 6 is an energy band diagram for explaining a conduction state of a channel region of a conventional n-channel MOS.

FIG. 7 is an energy band diagram for explaining a cutoff state of a channel region in the device of the present invention.

FIG. 8 is an energy band diagram for explaining a conduction state of a channel region in the element of the present invention.

FIG. 9 is an energy band diagram for explaining conditions to be satisfied by a channel region in the device of the present invention.

FIG. 10 is an energy band diagram for explaining conditions to be satisfied by the channel region in the device of the present invention.

FIG. 11 is an energy band diagram for explaining conditions to be satisfied by the channel region in the device of the present invention.

FIG. 12 is a cross-sectional view showing the first manufacturing process of the element of the present invention.

FIG. 13 is a sectional view showing a second manufacturing step of the element of the present invention.

FIG. 14 is a cross-sectional view showing step 3 of the manufacturing process of the element of the present invention.

FIG. 15 is a cross-sectional view showing a fourth manufacturing step of the element of the present invention.

FIG. 16 is a cross-sectional view showing step 5 of the manufacturing process of the element of the present invention.

FIG. 17 is a sectional view showing Step 6 of the manufacturing process of the element of the present invention.

FIG. 18 is a plan view showing an example of the surface structure of the element of the present invention.

FIG. 19 is a plan view showing another embodiment of the surface structure of the element of the present invention.

FIG. 20 is a plan view showing another embodiment of the surface structure of the element of the present invention.

FIG. 21 is a sectional view showing an element structure of a conventional example.

[Explanation of symbols]

 L ... Channel length H ... Channel thickness 1 ... N-type drain region 2 ... N + type source region 3 ... Gate insulating film 4 ... Gate electrode 5 ... Interlayer insulating film 6 ... Insulated gate 7 ... Source electrode 8 ... Schottky junction 9 ... Mask material 10 ... P-type region 11 ... Pn junction 12 ... Injection electrode 13 ... N + substrate region 14 ... Drain electrode 15 ... P-type base region 16 ... Contact p + region 18 ... P-type anode region 19 ... Insulating electrode 100 ... Channel Area 200 ... Mask material 222 ... Mask material

Claims (1)

[Claims] 1. An insulated gate, which is formed in contact with one main surface of a semiconductor substrate of the first conductivity type to be a drain region and has a surface covered with an insulating film, comprising: the drain region; A first conductivity type channel region formed in contact with the insulated gate, and a first conductivity type source region formed in contact with the insulated gate and the channel region and not in contact with the drain region. And has a source electrode made of a metal that makes ohmic contact with the source region and forms a Schottky junction with the channel region and the drain region, is in contact with the drain region, is in contact with the insulated gate, or is in the vicinity thereof. And a second conductivity type region formed so as not to contact the source region and the source electrode, the second conductivity type region being the source. And another electrode and the ohmic contact is independent of the electrode, and the gate electrode is made of a semiconductor of metal or high-concentration second conductivity type, wherein a.