JPS59193066A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS59193066A
JPS59193066A JP6732683A JP6732683A JPS59193066A JP S59193066 A JPS59193066 A JP S59193066A JP 6732683 A JP6732683 A JP 6732683A JP 6732683 A JP6732683 A JP 6732683A JP S59193066 A JPS59193066 A JP S59193066A
Authority
JP
Japan
Prior art keywords
layer
channel
p1
p2
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6732683A
Inventor
Takeya Ezaki
Osamu Ishikawa
Masabumi Kubota
Original Assignee
Matsushita Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd filed Critical Matsushita Electric Ind Co Ltd
Priority to JP6732683A priority Critical patent/JPS59193066A/en
Publication of JPS59193066A publication Critical patent/JPS59193066A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel latral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation

Abstract

PURPOSE:To contrive to improve the mobility by thickening the channel at the time of ON-operation by a method wherein an n-layer in n-channel and a p-layer in p-channel are buried in the substrate distant from the interface between an oxide film and a semiconductor. CONSTITUTION:The n-channel part is composed by dividing into an inside p2 layer 8 and a surface p1 layer 10 and burying a p-layer 9 therebetween. In an enhancement type FET, the n-layer 9 is set generally at a lower concentration than that of the p2 layer 8 and completely depleted owing to a depletion layer extending from the p1 layer 10 and the p2 layer 8, therefore electrons contributed to conduction do not exist. Next, when an inversion layer is induced in the p1 layer 10 by applying a positive potential to the gate 5, and the whole p1 layer 10 becomes an n type inversion layer by a high gate potential, then electrons generate also in the depleted n-layer 9, resulting in the ON-state of most part of the p1 layer 10 and the n-layer 9 by conversion into the n-channel. Since the buried n-layer 9 is also contributed as the channel in this invention, the channel width increases effectively, and dispersion in the channel decreases, causing the improvement of the mobility.
JP6732683A 1983-04-15 1983-04-15 Mos semiconductor device Pending JPS59193066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6732683A JPS59193066A (en) 1983-04-15 1983-04-15 Mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6732683A JPS59193066A (en) 1983-04-15 1983-04-15 Mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS59193066A true JPS59193066A (en) 1984-11-01

Family

ID=13341784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6732683A Pending JPS59193066A (en) 1983-04-15 1983-04-15 Mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS59193066A (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63179573A (en) * 1987-01-21 1988-07-23 Seiko Instr & Electronics Ltd Manufacture of insulated gate field-effect transistor
JPS63284858A (en) * 1987-05-15 1988-11-22 Seiko Instr & Electronics Ltd Insulated-gate field-effect transistor
WO2011103314A1 (en) * 2010-02-18 2011-08-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8970289B1 (en) * 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
EP2483915A4 (en) * 2009-09-30 2015-07-01 Suvolta Inc Electronic devices and systems, and methods for making and using the same
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9093469B2 (en) 2011-03-30 2015-07-28 Mie Fujitsu Semiconductor Limited Analog transistor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9741428B2 (en) 2011-05-13 2017-08-22 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9853019B2 (en) 2013-03-15 2017-12-26 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63179573A (en) * 1987-01-21 1988-07-23 Seiko Instr & Electronics Ltd Manufacture of insulated gate field-effect transistor
JPS63284858A (en) * 1987-05-15 1988-11-22 Seiko Instr & Electronics Ltd Insulated-gate field-effect transistor
US10074568B2 (en) 2009-09-30 2018-09-11 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using same
US10224244B2 (en) 2009-09-30 2019-03-05 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US10217668B2 (en) 2009-09-30 2019-02-26 Mie Fujitsu Semiconductor Limited Electronic devices and systems, and methods for making and using the same
US8975128B2 (en) 2009-09-30 2015-03-10 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
EP2483915A4 (en) * 2009-09-30 2015-07-01 Suvolta Inc Electronic devices and systems, and methods for making and using the same
WO2011103314A1 (en) * 2010-02-18 2011-08-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
US9922977B2 (en) 2010-06-22 2018-03-20 Mie Fujitsu Semiconductor Limited Transistor with threshold voltage set notch and method of fabrication thereof
US9985631B2 (en) 2011-02-18 2018-05-29 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9838012B2 (en) 2011-02-18 2017-12-05 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9680470B2 (en) 2011-02-18 2017-06-13 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US10250257B2 (en) 2011-02-18 2019-04-02 Mie Fujitsu Semiconductor Limited Digital circuits having improved transistors, and methods therefor
US9093469B2 (en) 2011-03-30 2015-07-28 Mie Fujitsu Semiconductor Limited Analog transistor
US9741428B2 (en) 2011-05-13 2017-08-22 Mie Fujitsu Semiconductor Limited Integrated circuit devices and methods
US9793172B2 (en) 2011-05-16 2017-10-17 Mie Fujitsu Semiconductor Limited Reducing or eliminating pre-amorphization in transistor manufacture
US9054219B1 (en) 2011-08-05 2015-06-09 Mie Fujitsu Semiconductor Limited Semiconductor devices having fin structures and fabrication methods thereof
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US9953974B2 (en) 2011-12-09 2018-04-24 Mie Fujitsu Semiconductor Limited Tipless transistors, short-tip transistors, and methods and circuits therefor
US8970289B1 (en) * 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US10014387B2 (en) 2012-06-27 2018-07-03 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9812550B2 (en) 2012-06-27 2017-11-07 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US10217838B2 (en) 2012-06-27 2019-02-26 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9893148B2 (en) 2013-03-14 2018-02-13 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9853019B2 (en) 2013-03-15 2017-12-26 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9991300B2 (en) 2013-05-24 2018-06-05 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9786703B2 (en) 2013-05-24 2017-10-10 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods

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