JPS59193066A - Mos semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to improve the mobility by thickening the channel at the time of ON-operation by a method wherein an n-layer in n-channel and a p-layer in p-channel are buried in the substrate distant from the interface between an oxide film and a semiconductor. CONSTITUTION:The n-channel part is composed by dividing into an inside p2 layer 8 and a surface p1 layer 10 and burying a p-layer 9 therebetween. In an enhancement type FET, the n-layer 9 is set generally at a lower concentration than that of the p2 layer 8 and completely depleted owing to a depletion layer extending from the p1 layer 10 and the p2 layer 8, therefore electrons contributed to conduction do not exist. Next, when an inversion layer is induced in the p1 layer 10 by applying a positive potential to the gate 5, and the whole p1 layer 10 becomes an n type inversion layer by a high gate potential, then electrons generate also in the depleted n-layer 9, resulting in the ON-state of most part of the p1 layer 10 and the n-layer 9 by conversion into the n-channel. Since the buried n-layer 9 is also contributed as the channel in this invention, the channel width increases effectively, and dispersion in the channel decreases, causing the improvement of the mobility.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices and integrated circuits, and is the first to be applied to high-speed switching devices, ultra-high frequency signal amplifier (1) devices, ultra-high density, high-speed LSIs, etc. ” is used.

Structure of conventional example and its problems MO3 type field effect transistor (hereinafter MO3F1i: T
) and MO3 type integrated circuits (hereinafter referred to as Mo5t, SI), which use them as basic constituent elements, are becoming more sophisticated year by year, and this trend will continue in the future. It is expected that it will be used in the next few years. At the same time, the so-called short channel effect is becoming more prominent, and in order to prevent it, it is necessary to
according to the classical scaling law.

A variety of measures are required to thin the oxide film and increase the concentration of impurities in the channel. However, in any case, it is inevitable that the electric field strength Iw becomes strong both in the carrier traveling direction and in the perpendicular direction. The vertical electric field increases scattering within the one-surface inversion layer and reduces the gear carrier mobility, but such intra-channel scattering is further exacerbated by increasing the impurity concentration in the channel and decreasing the thickness of the inversion layer. be done.

Figure 1 shows a conventional MOS) transistor with 99. a is a cross-sectional structural diagram, and b is an impurity distribution viewed in the A-A' force direction.

Note that electrode wiring is omitted. In the case of an n-channel, the substrate 1 is set to p-, and nine layers 6 are formed with a higher concentration than the substrate to lower the valleys of the north drains n-+2 and 3 to the substrate and to prevent punch-through. By applying a positive potential 71-e to the gate 5, a channel 7, which is an n-type anti-Qji layer, is formed at the interface V between the pJ density 6 and the gate oxide film 4; With miniaturization, the concentration of the 9th layer 6 increases due to the above-mentioned misaki effect, resulting in a thinning of several hundred angstroms.

Purpose of the Invention In view of these problems in the conventional example, the present invention improves the shape of the channel through which carriers travel, and a) improves the mobility and increases the gain of OS FET. That is.

Structure of the Invention The present invention is to increase the thickness of the channel when the channel is turned on by burying a p-type layer for an n-channel and a p-type layer for a p-channel in a substrate cut away from the oxide film-semiconductor interface. The main point is

DESCRIPTION OF EMBODIMENTS FIG. 2 shows an embodiment of the present invention. Numbers 1 to 5 are the same as in FIG. The 9th layer 6 in Figure 1 is the internal p21m 8
and 95 layers 10 on the surface, and 8 layers 9 are buried between them. Figure 2 shows the impurity distribution. p, is thinner than p2, and is drawn at a lower concentration, but -p, and p2
The shape of can be changed arbitrarily depending on the purpose. size 8
Layer 9 has a lower concentration than any of p, p, and p2, but this is not essential. However, if there are 8 layers 9, there are generally 27 layers.

It is set to a lower concentration than This means that when '1'ii/EvGs between gate and source is zero volts, North 2. This is because in order to realize a normally-off, ie, enhancement type MO3FETi in which VC is off between the drains 3 and 3, the 8th layer 9 must be depleted.

It shows the bottom-year distribution for each state number that is turned on by applying a positive potential to. In the enhancement type, in a, the buried n layer 9 is the 91st layer on the surface 1Q and the 92nd layer inside the paralysis.
It is completely depleted by a depletion layer extending from layer 8,
There are no electrons contributing to conduction. Next, a positive potential is applied to the gate 6 n, p.

If an inversion layer is induced in the layer 1o and the entire p1 layer 10 becomes an n-type inversion layer due to the higher gate potential, electrons will also be generated in the depleted n/layer 9.

As a result, P11'7'O and the thickness of the 8 layer 9 converts into an n-type channel and becomes an on state. In the conventional example, only the surface inversion layer was a chile, but in the present invention,
Since the eight false layers 9 buried inside also contribute as a channel, the channel thickness effectively increases by j.

This reduces scattering within the channel and thus improves mobility. This is particularly important in submicron devices with high channel doping.

Taking a configuration example when the effective channel length is 0.5 μm, the 92 layers 8 have a thickness of 0.2 μm, and are 2×10”c.
m'.

With a thickness of nM9 of 500 people, I x 1016 cm-3
So, 91 layer 10 has a thickness of 300 people and is 3 x 1016 cr.
It is the aI skin of u:'. Such a thin layer can also be created by ion implantation.

For a more precise structure, molecular beam evitaquine (M
olecular BearrlEpitaxy) is preferred.

The above are enhancement-type gifts, or normal/normal gifts.
In order to achieve a 1° on-state, tebration type, the thickness of the n-layer 9 is increased to 0.111 m, and the concentration is 167 cm-' per layer, so that even when the gate voltage is low, it is depleted and electrons are not released. It is sufficient if the configuration is such that .

Next, the diffusion self-aligned chamfer of the present invention (Diffusio
nSelf Aligned) MOSFET
(hereinafter abbreviated as single KDMO3) is shown in FIG. 4.

The inner 2 layer 8 and the surface 9 layer 10 are the source 2 of the gate 6.
They are formed simultaneously by the same diffusion process from the side ends. 9 layers 10 sources 2. The thickness in three directions of the drain is defined as the effective channel length. The n-layer 9 consists of a portion 9a extending between the nine layers 8 and 10, and a portion 9b of the p-layer inner running region of the substrate 1. DMO3 is.

Since the channel length of the gate 5, which is shorter than [4J, is formed by diffusion rather than photoetching, it has the advantage that a submicron channel can be formed with high precision.

nl 90 parts 9a, 9 layers 8 and 1 with higher a degree than that
Therefore, when applying a gate atmosphere bias, the thickness and impurity concentration must be adjusted so that the depletion layer is completely depleted by the depletion layer coming from each p layer. By doing this, this DMO3 can be used for enhancement 111. At this time, although the area around the portion 9b is a p- region with a low concentration, it is not depleted.

It buds as a neutral region. This portion contributes to lowering the resistance of the running region 11 from the end of pl so 1° to the drain 3. As a result, the drain voltage ff1r, 't(8
゜The on-resistance and saturation first electric power of positive characteristics, EVsat, decrease.

In addition, as described with reference to Fig. 3, if <N'rls 9a, it has the effect of increasing the chale thickness (7. Enhanced non-challenge mobility is improved, so the on-resistance is low and the mutual conductance is And the drain voltage becomes high when it is 1-.

Depending on the concentration of parts 9ai'ipJ buds 8 and 1o, it becomes p-type, i-saint, or n-type. Even if the portion 9a is of the p-type, if the concentration is lower than that of the adjacent nine layers 8- or 10, it will act as a channel region when the gate potential is positive, as in the case of the n-type. Even if this is not the case, driving area 1
Since the action of the portion 9b of 1 is still effective, the DMO 3 still has the features of low on-resistance and low saturation.

Although the above is a case of a horizontal DMOS, the present invention is similarly applied to a vertical DMO8. FIG. 5 shows all embodiments for this case. In the figure, a substrate 1 consists of a highly doped n-type substrate 1a and an n-type epitaxial layer 1b thereon, with the n-type substrate 1a serving as a drain. Gate 5V'
When a c-stop potential is applied and an n-type inversion layer is induced at the interface between the p region 8 and the gate oxide film 4, the 8 layer 9 in the running region 11
Since an n-type channel is also generated in 1sfJK between the gate oxide film 4 and the gate oxide film 4, electrons can move from the source 2 to the drain 1a.

At this time, since the 8 layer 9b has a higher surface concentration than the n epitaxial layer 1b, most of the electrons emitted from the p region 8 to the transit region 11 pass through the lower resistance layer 9b. When an alternating current signal is superimposed on gate 5, the electron concentration increases or decreases in n layer 9b, and the change in charge becomes the input capacitance of gate 5 and can be measured.

Without the 8th layer 9b, the electrons travel closer to the gate oxide film 4, so that the input capacitance due to the change in electron concentration in the travel region 11 becomes large. On the contrary,
As in the present invention, when there are eight layers 9b having a lower specific resistance than the surroundings, electrons can travel there perfectly, and as a result, the distance from the oxide film 4 is smaller than in the conventional case. It gets far away. Therefore, the gate input capacitance due to changes in electron concentration in the travel region 11 becomes smaller than in the conventional example.

For the vertical DMO3 in Figure 5, the distance from point A to point B in the diagram is D.
MO3, 0 points from point B with δ go 0 points - soil p region 8
It can be interpreted as a semiconductor device in which these are read directly in series as a junction gate field effect l-run/metal (hereinafter abbreviated as JFET) with the gate as the gate. This is shown in FIG. 8 layers 9b
is expressed as the resistance between point B and point C. Point A is the source.

Usually grounded. Since the p region 8 is used at the same potential as the source, the gate of the JFET between the points -C and D is grounded. There is a harmful feedback capacitance Gf between points B and C and gate 5, which degrades the high frequency characteristics.
The above-mentioned JFET is a special triode tube that exhibits a finite resistance vL value for high-frequency signals. It is known from network theory that the feedback from train D to gate 5 is almost negligible.

Since it is essential that the current path in Jj and Hi 1 be long and thin, the 0 layer 9b is sufficiently l to meet the distance between points B and C:
, 9klkei kl: Not a pound. For example, the distance 1 to 11 between points -B and C is 1 μm;
, 1 ttm or less. Then, at a desired drain voltage, the depletion layer 12 extending from the p region 8 into the epitaxial layer 1b reaches the point c VC, and the n layer 9b
The shape of the layer 9b and the impurity concentration of the layer 1b must be selected so as to substantially enclose it. Alternatively, at that time, the n-layer 9b itself may be substantially depleted. However, if DMO3 becomes a JFET or pentode characteristic before it becomes a pentode characteristic VC, the drain-in current or DMO8;
This is not desirable because it is limited by the FET. If the train voltage is increased and the train voltage is increased, it is possible to achieve both 1.1 and 1.1 pentode characteristics at the same time, thereby achieving both high drain current and low feedback. Therefore, when the 11th layer 9b overlaps the depletion layer 12 by approximately four times, or when the n layer 9b itself becomes approximately depleted, does the channel become depleted near the point B of DMO3?l'l J, El Tea 6-1, U1 Momoki, nJ
, d 9)) length B-C black circle:ll) length 'if
At a drain voltage higher than n Iri and shorter, the n layer 9 b ((J, quadruple the depletion layer. To enclose &;l- near point C, p- or l or n-
High resistance distribution) It is sufficient to form 13 precepts.

As is clear from the above-described embodiments, the present invention has the following features: (1) Embedded!
The layer serves as a current path together with the interface TK and the induced channel, effectively increasing the channel thickness, thereby reducing the influence of layer plane scattering and improving the mobility. Due to the on-resistance, the current and mutual conductance are high.

(2) Traveling region C of IJMO3 (when applied, the gear carrier travels in the buried layer away from the gate insulating film, so the gate-carrier phase t7H effect occurs) ”8:
ii- or decrease-.

(3) Vertical type 1. When applied to the running area of ltA OS, it can achieve both low feedback characteristics, low on-resistance, high current, and high mutual conductance. The VCC horsepower is increased by increasing the resistance, increasing the speed, increasing the current, and increasing the gain and output of the microwave amplification element.

[Brief explanation of drawings]

Figures 1a and 1b are cross-sectional views of a conventional MOSFET. The impurity distribution diagram in the depth direction, FIGS. . b is a diagram showing the off state and on state of the potential distribution of Ra Q S F E T in FIG. 2, FIG. 4 is a cross-sectional view of an embodiment in which the present invention is applied to DMO3, and FIG. Vertical type 1) Cross-sectional view of an embodiment applied to MOS. FIG. 6 is a circuit diagram of FIG. 5. 1...Semiconductor substrate, 2...Source, 3...
Drain, 4... Kate oxide film, 5... Gate, 6°8, 10-piJt region, 9 (9a, 9b
)-n layer. -30: Fig. 1 7 (A) Fig. 2 βn Fig. 3 ((1) Evil 4 q

Claims (4)

[Claims] (1) A region immediately below a gate formed on a semiconductor substrate via a gate insulating film, and a buried layer formed in the substrate apart from the gate insulating film, and an interface between the substrate and the gate insulating film. The conduction channel induced by the gate reaches the buried layer, and both the channel at the interface and the buried layer serve as a current path.
O8 type semiconductor device. (2) The MO3 type semiconductor device according to claim 1, characterized in that when a channel at the interface is not induced, the buried layer is depleted and does not serve as a current path. (3) The channel length is defined by the difference in lateral diffusion depth between a deep first impurity region of one conductivity type and a shallow second impurity region of two conductivity types introduced into the plate from one end of the gate,
A buried layer provided in the substrate outside the first impurity region! Claim No. 1 also characterized by
M OS of the entry and the composition! l: li semiconductor device. (4) Use the second impurity region as a source and form part of the substrate. It has a vertical structure with a drain at its bottom, and when the depletion layer extending from the first region into the substrate is approximately surrounded by a part of the depletion layer, the entire buried layer is approximately depleted. 4! When the first impurity region and the gate insulating film interface are partially depleted, a portion of the channel is depleted. MO3O3 type semiconductor device according to claim 3