JPS63284858A - Insulated-gate field-effect transistor - Google Patents
Insulated-gate field-effect transistorInfo
- Publication number
- JPS63284858A JPS63284858A JP11954387A JP11954387A JPS63284858A JP S63284858 A JPS63284858 A JP S63284858A JP 11954387 A JP11954387 A JP 11954387A JP 11954387 A JP11954387 A JP 11954387A JP S63284858 A JPS63284858 A JP S63284858A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- epitaxial
- epitaxial growth
- impurity concentration
- growth layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000000694 effects Effects 0.000 abstract description 9
- 239000010408 film Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000002265 prevention Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002109 crystal growth method Methods 0.000 description 2
- 244000292604 Salvia columbariae Species 0.000 description 1
- 235000012377 Salvia columbariae var. columbariae Nutrition 0.000 description 1
- 235000001498 Salvia hispanica Nutrition 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 235000014167 chia Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000003754 fetus Anatomy 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、高速かつ低消費電力で動作し、大規模集積回
路のスイッチング素子などに利用される絶縁ゲート電界
効果トランジスタ（以下、ＭＯＳＦＥＴと略記する）に
関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to insulated gate field effect transistors (hereinafter abbreviated as MOSFETs) that operate at high speed and with low power consumption and are used as switching elements in large-scale integrated circuits. related to)
（発明の概要〕
本発明は、高濃度基板上に単原子層オーダーの精度で、
膜厚及び不純物濃度が制御された第１のエピタキシャル
成長層を設けてチャネルとし、更に前記第１のエピタキ
シャル成長層の上に前記第１のエピタキシャル成長層よ
りも不純物濃度が高い第２のエピタキシャル成長層を設
けている。前記第１のエピタキシャル成長層は不純物濃
度が低くキャリアの移動度が高い領域となっている。他
方、前記第２のエピタキシャル成長層は、トランジスタ
のしきい電圧を制御し、更に短チヤネル効果を防止する
うえで大きな効果を有する。このような構造を有するＭ
ＯＳ Ｆ ＥＴは、高濃度基板を用いているためにう、
チアツブが起こりにくく・また短チヤネル効果を防止す
るうえで有効である。(Summary of the Invention) The present invention provides a method for forming an atomic layer on a highly concentrated substrate with an accuracy on the order of a single atomic layer.
A first epitaxially grown layer with a controlled film thickness and impurity concentration is provided as a channel, and a second epitaxially grown layer having a higher impurity concentration than the first epitaxially grown layer is further provided on the first epitaxially grown layer. There is. The first epitaxial growth layer has a low impurity concentration and a high carrier mobility. On the other hand, the second epitaxial growth layer has a great effect in controlling the threshold voltage of the transistor and further preventing short channel effects. M with such a structure
Since OS FET uses a highly concentrated substrate,
It is effective in preventing chia bulges and preventing short channel effects.
しかもチャネル領域はキャリアの移動度が高いため高速
動作を実現することができる。Moreover, since the channel region has high carrier mobility, high-speed operation can be achieved.
半導体デバイスの高速化を実現するうえで、微細化はひ
とつの有力な手段である。しかしながら、デバイス寸法
の微細化に伴って短チヤネル効果などに代表されるデバ
イスの性能上好ましくない現象が起きてしまうため、従
来から以下のような方法が採用されていた０例えば、高
濃度基板を用いて、チャネル領域をイオン注入により活
性化する方法、あるいは高濃度基板上に気相成長法を用
いてエピタキシャル成長層を設けた第４図に示すような
構造とする方法などである。Miniaturization is one effective means of achieving higher speeds in semiconductor devices. However, with the miniaturization of device dimensions, unfavorable phenomena in terms of device performance, such as the short channel effect, occur. A method of activating the channel region by ion implantation, or a method of creating a structure as shown in FIG. 4 in which an epitaxial growth layer is provided on a highly doped substrate using a vapor phase growth method.
しかしながら、高濃度基板を用いてチャネルにイオン注
入を行う場合、イオン注入による基板表面近傍のダメー
ジが生じ、これが接合リーク等の原因となってしまう、
また、エピタキシャル成長層を設けた基板を用いる場合
、従来のエピタキシャル成長が１０００℃以上の高温で
行われていたために、基板からエピタキシャル成長層へ
の不純物のオートドーピングが避けられず、第２図破線
で示す範囲の不純物濃度が限界であった。そこで、チャ
ネル領域での不純物濃度を十分低くするためには、少な
くとも数μｍ以上の膜厚を有するエピタキシャル成長層
が必要となるが、これは短チヤネル効果を防止するうえ
で高濃度基板を用いている効果を減少させるものであっ
た。However, when ion implantation is performed into a channel using a highly doped substrate, the ion implantation causes damage near the substrate surface, which can cause junction leakage, etc.
In addition, when using a substrate provided with an epitaxial growth layer, since conventional epitaxial growth was performed at a high temperature of 1000°C or higher, autodoping of impurities from the substrate to the epitaxial growth layer is unavoidable, and the range shown by the broken line in Figure 2 The impurity concentration was the limit. Therefore, in order to sufficiently reduce the impurity concentration in the channel region, an epitaxial growth layer with a thickness of at least several micrometers is required, but this is achieved by using a highly doped substrate to prevent the short channel effect. This was to reduce the effectiveness.
以上のような問題点を解決するために、本発明において
は、高濃度基板上にエピタキシャル成長温度が８５０℃
以下、膜厚の制御精度が単原子層オーダーであるような
結晶成長法を用いて、前記基板よりも不純物濃度が低い
第１のエピタキシャル成長薄膜層を設けてチャネルとし
、更に成長時に不純物導入を行う同様の結晶成長法を用
いて、前記第１のエピタキシャル成長層よりも不純物濃
度の高い第２のエピタキシャル成長層を設けた構造とす
ることにより、耐ランチアンプ性に優れた短チヤネル効
果防止に有効な構造をもつ高速ＭＯ３ＦＥＴを実現して
いる。In order to solve the above problems, in the present invention, the epitaxial growth temperature is 850°C on a high concentration substrate.
Hereinafter, a first epitaxially grown thin film layer with a lower impurity concentration than the substrate is provided as a channel using a crystal growth method whose film thickness control accuracy is on the order of a single atomic layer, and further impurities are introduced during growth. By using a similar crystal growth method and providing a second epitaxial growth layer with a higher impurity concentration than the first epitaxial growth layer, a structure that is effective in preventing the short channel effect with excellent launch amplifier resistance can be achieved. This realizes a high-speed MO3FET with
以下、実施例に基づいて本発明の詳細な説明する。第１
図は、本発明の実施例であるＭＯＳＦＥＴの構造断面図
である。高濃度基板１は不純物濃度がＩ ＸＩＯ”ｃｍ
−’のＰ型を用いている。前記高濃度基板１の上に形成
される第１エピタキシャル成長層２の膜厚は、チャネル
領域の空乏層幅と同程度となっている。第１エピタキシ
ャル成長層２の不純物濃度は、ＭＯＳ Ｆ ＥＴの相互
コンダクタンスを決める大きな要因であり、第２図の実
線で示すように、相互コンダクタンスを大きくするため
には、可能な限り第１エピタキシャル成長層２の不純物
濃度を下げねばならない、このため、第１エピタキシャ
ル成長層２を形成する際の基板温度は、８５０℃以下で
ある。その結果、第１エピタキシャル成長層の不純物濃
度は約１ ×ｌ Ｑ ｌ ２ ｃｍ−３となっている０
次に第１エピタキシャル成長層２の上に第２エピタキシ
ャル成長層３を形成するために、不純物ドーピングと結
晶成長を同時に行うことにより、第１エピタキシャル成
長層２よりも不純物濃度の高い領域を設けている。第２
エピタキシャル成長層３の膜厚はＭＯＳＦＥＴのしきい
電圧に大きく影響し、第３図に示すような傾向をもつ。Hereinafter, the present invention will be described in detail based on Examples. 1st
The figure is a structural sectional view of a MOSFET that is an embodiment of the present invention. The high concentration substrate 1 has an impurity concentration of IXIO”cm
-' P type is used. The thickness of the first epitaxial growth layer 2 formed on the high concentration substrate 1 is approximately the same as the width of the depletion layer of the channel region. The impurity concentration of the first epitaxial growth layer 2 is a major factor that determines the mutual conductance of the MOSFET, and as shown by the solid line in FIG. 2, in order to increase the mutual conductance, it is necessary to Therefore, the substrate temperature when forming the first epitaxial growth layer 2 is 850° C. or lower. As a result, the impurity concentration of the first epitaxial growth layer is approximately 1 × l Q l 2 cm-3.
Next, in order to form a second epitaxial growth layer 3 on the first epitaxial growth layer 2, a region having a higher impurity concentration than the first epitaxial growth layer 2 is provided by performing impurity doping and crystal growth simultaneously. Second
The thickness of the epitaxial growth layer 3 greatly influences the threshold voltage of the MOSFET, and has a tendency as shown in FIG.
従って、第２エピタキシャル成長層３の膜厚を単原子層
オーダーの精度で制御することにより、任意のしきい電
圧を精度良く決めることができる。Therefore, by controlling the thickness of the second epitaxial growth layer 3 with precision on the order of a single atomic layer, an arbitrary threshold voltage can be determined with high precision.
このあと、ゲート酸化膜４、ゲート５を設けた後に、イ
オン注入によりソース６及びドレイン７を形成している
。このようにして作製されたＭＯＳＦＥＴは、駆動能力
の優れたものとなる。Thereafter, after providing a gate oxide film 4 and a gate 5, a source 6 and a drain 7 are formed by ion implantation. The MOSFET manufactured in this manner has excellent driving ability.
本発明によれば、基板は低抵抗であり、ラフチアツブフ
リーを実現し、第１エピタキシャル成長層は不純物濃度
が低く高移動度を実現する。更に、第２エピタキシャル
成長層は不純物濃度が高く、短チヤネル効果等を防止す
るうえで有効となる。According to the present invention, the substrate has low resistance and is free from rough stubble, and the first epitaxial growth layer has a low impurity concentration and high mobility. Furthermore, the second epitaxial growth layer has a high impurity concentration, which is effective in preventing short channel effects and the like.
以上のように、本発明は微細ＭＯ３ＦＥＴが高速かつ低
消費電力で動作するうえで好適なデバイス構造を提供す
る。As described above, the present invention provides a device structure suitable for a fine MO3FET to operate at high speed and with low power consumption.
第１図は、本発明によるＭＯＳＦＥＴの構造断面図、第
２図は、相互コンダクタンスのチャネル不純物濃度依存
特性図、第３図は、しきい電圧の第２エピタキシャル成
長層膜厚依存特性図、第４図は、エピタキシャル成長層
を有した従来のＭＯＳＦＥＴの構造断面図である。
１・・・高濃度基板
２・・・第１エピタキシャル成長層
３・・・第２エピタキシャル成長層
４・・・ゲート酸化膜
５・・・ゲート
６・・・ソース
７・・・ドレイン
以上
出願人 セイコー電子工業株式会社
２ｖ１１１Ｌ′７千タルｂ長層
本発明１てよりｍ０５ＦＥＴのＩ造−断面図笛 １ｆ！
１
チｖ′３Ｆル毛屹倖填戻（Ｃｆｆｌ−υ半８１コン７７
９ンスのチャ序ＩＬ／ｆ１４勿濤屓榛存情十生図第 ２
旧FIG. 1 is a cross-sectional view of the structure of a MOSFET according to the present invention, FIG. 2 is a characteristic diagram of channel impurity concentration dependence of mutual conductance, FIG. 3 is a characteristic diagram of threshold voltage dependence on second epitaxial growth layer thickness, and FIG. The figure is a structural cross-sectional view of a conventional MOSFET having an epitaxially grown layer. 1...High concentration substrate 2...First epitaxial growth layer 3...Second epitaxial growth layer 4...Gate oxide film 5...Gate 6...Source 7...Drain and above Applicant Seiko Electronics Kogyo Co., Ltd. 2v111L'7,000 Tal B Long Layer Present Invention 1 From m05 FET I Construction - Cross-sectional Diagram Whistle 1f!
1 Chi v'3F Le hair 屹倖filling back (Cffl-υhalf 81 con 77
9th Cha Introduction IL/f14 Of course, the 10th life of the 2nd life
old
Claims (3)
い第１のエピタキシャル成長層と、前記第１のエピタキ
シャル成長層の上に前記第１のエピタキシャル成長層よ
りも不純物濃度が高い第２のエピタキシャル成長層を設
けたことを特徴とする絶縁ゲート電界効果トランジスタ
。(1) A first epitaxial growth layer having a lower impurity concentration than the substrate on a high concentration substrate, and a second epitaxial growth layer having a higher impurity concentration than the first epitaxial growth layer on the first epitaxial growth layer. An insulated gate field effect transistor characterized by being provided with.
Å以下であることを特徴とする特許請求の範囲第１項記
載の絶縁ゲート電界効果トランジスタ。(2) The thickness of the second epitaxial growth layer is 500 mm.
2. The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor has a thickness of Å or less.
ネル領域の空乏層幅と同程度あるいはそれ以下であるこ
とを特徴とする特許請求の範囲第１項記載の絶縁ゲート
電界効果トランジスタ。(3) The insulated gate field effect transistor according to claim 1, wherein the film thickness of the first epitaxial growth layer is approximately the same as or less than the depletion layer width of the channel region.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119543A JP2720153B2 (en) | 1987-05-15 | 1987-05-15 | Insulated gate field effect transistor and method of manufacturing the same |
| EP87311541A EP0274278B1 (en) | 1987-01-05 | 1987-12-31 | MOS field effect transistor and method of manufacturing the same |
| DE3789894T DE3789894T2 (en) | 1987-01-05 | 1987-12-31 | MOS field effect transistor and its manufacturing method. |
| US08/538,980 US6229188B1 (en) | 1987-01-05 | 1995-10-05 | MOS field effect transistor and its manufacturing method |
| US08/782,975 US5923985A (en) | 1987-01-05 | 1997-01-14 | MOS field effect transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62119543A JP2720153B2 (en) | 1987-05-15 | 1987-05-15 | Insulated gate field effect transistor and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63284858A true JPS63284858A (en) | 1988-11-22 |
| JP2720153B2 JP2720153B2 (en) | 1998-02-25 |
Family
ID=14763900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62119543A Expired - Lifetime JP2720153B2 (en) | 1987-01-05 | 1987-05-15 | Insulated gate field effect transistor and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2720153B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100308783B1 (en) * | 1998-07-08 | 2001-12-17 | 곽정소 | Semiconductor device manufacturing method |
| KR100498592B1 (en) * | 1997-12-27 | 2006-04-28 | 주식회사 하이닉스반도체 | Most transistors and manufacturing method thereof |
| KR100613294B1 (en) * | 2004-12-30 | 2006-08-21 | 동부일렉트로닉스 주식회사 | MOSFET improving the short channel effect and method of fabricating the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS59193066A (en) * | 1983-04-15 | 1984-11-01 | Matsushita Electric Ind Co Ltd | Mos semiconductor device |
| JPS62216269A (en) * | 1986-03-17 | 1987-09-22 | Nec Corp | Manufacture of mis transistor |
-
1987
- 1987-05-15 JP JP62119543A patent/JP2720153B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55117281A (en) * | 1979-03-05 | 1980-09-09 | Nippon Telegr & Teleph Corp <Ntt> | 3[5 group compound semiconductor hetero structure mosfet |
| JPS59193066A (en) * | 1983-04-15 | 1984-11-01 | Matsushita Electric Ind Co Ltd | Mos semiconductor device |
| JPS62216269A (en) * | 1986-03-17 | 1987-09-22 | Nec Corp | Manufacture of mis transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100498592B1 (en) * | 1997-12-27 | 2006-04-28 | 주식회사 하이닉스반도체 | Most transistors and manufacturing method thereof |
| KR100308783B1 (en) * | 1998-07-08 | 2001-12-17 | 곽정소 | Semiconductor device manufacturing method |
| KR100613294B1 (en) * | 2004-12-30 | 2006-08-21 | 동부일렉트로닉스 주식회사 | MOSFET improving the short channel effect and method of fabricating the same |
| US7675126B2 (en) | 2004-12-30 | 2010-03-09 | Dongbu Electronics Co., Ltd. | Metal oxide semiconductor field effect transistor and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2720153B2 (en) | 1998-02-25 |
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