JPS63142677A - Insulated-gate field-effect transistor - Google Patents
Insulated-gate field-effect transistorInfo
- Publication number
- JPS63142677A JPS63142677A JP61289163A JP28916386A JPS63142677A JP S63142677 A JPS63142677 A JP S63142677A JP 61289163 A JP61289163 A JP 61289163A JP 28916386 A JP28916386 A JP 28916386A JP S63142677 A JPS63142677 A JP S63142677A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- drain
- gate
- ion implantation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 11
- 230000000694 effects Effects 0.000 claims description 7
- 239000002052 molecular layer Substances 0.000 claims 1
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 239000012535 impurity Substances 0.000 abstract description 17
- 239000000758 substrate Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 238000009792 diffusion process Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、不純物制御されたエピタキシ中ル成長層を用
いてＬＤＤ構造を形成することによって、高速かつ低消
費電力で動作する絶縁ゲート電界効果トランジスタ（以
下ＭＯ３ＦＥＴと略す）に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an insulated gate field effect that operates at high speed and with low power consumption by forming an LDD structure using an epitaxially grown layer with controlled impurities. It relates to a transistor (hereinafter abbreviated as MO3FET).
ｍ１１１ＭＯｓトランジスタにおいて短チャネル効果を
防ぐために、イオン注入により形成されたｎ一層の上に
高濃度ｎ″領域エピタキシャル成長により形成すること
によってソース・ドレイン領域を設ける。これによりド
レイン領域の不純物濃度を下げ拡散層の深さを浅くでき
る。In order to prevent the short channel effect in the m111 MOs transistor, source/drain regions are provided by epitaxially growing a high concentration n'' region on top of the n layer formed by ion implantation.This reduces the impurity concentration in the drain region and increases the diffusion layer. The depth can be made shallower.
ＭＯＳ ＦＥＴの微細化を進めるうえで、短チャネル
効果は大きな障害となっている。これを防止するための
対策として、従来ＬＤＤ構造が採用されている。従来の
ＬＤＤ構造は第２図ｔａ＋〜（Ｃ１に示すように、低濃
度イオン注入と高濃度イオン注入を行なうことにより、
低濃度ｎ−領域と高濃度ｎ＋領領域の間にオフセット領
域を形成していた。Short channel effects are a major obstacle in the advancement of miniaturization of MOS FETs. As a measure to prevent this, a conventional LDD structure has been adopted. The conventional LDD structure is constructed by performing low-concentration ion implantation and high-concentration ion implantation, as shown in Figure 2 ta+ (C1).
An offset region was formed between the low concentration n- region and the high concentration n+ region.
しかしながら上記従来の方法は、イオン注入を用いてｎ
′層を形成するために、第２図（Ｃ１のようにｎ”ｌｌ
を形成するために、第２図ｆｃｌのようにｎ・層はｎ一
層に比べて高濃度イオン注入に伴う拡散のために、拡散
層の深さを浅くできない。そのため実効的な横方法拡散
深さが浅くできず、短チャネル効果防止のうえで十分で
ない。However, the above conventional method uses ion implantation to
' layer as shown in Figure 2 (C1).
As shown in FIG. 2 (fcl), the depth of the diffusion layer cannot be made shallower in the n-layer than in the n-layer due to diffusion associated with high-concentration ion implantation. Therefore, the effective lateral diffusion depth cannot be made shallow, which is insufficient to prevent short channel effects.
上記に述べたように従来の方法は、低ｔａＫ！ｎ一層及
び高濃度ｎ゛層はイオン注入により形成されていたため
、拡散層の接合とその深さ制御には限界が伴う。これに
対して本発明では第１図（ａ）に示すように低濃度ｎ−
領域をイオン注入により形成し、第１図（ｂｌに示すよ
うにＣＶＤで酸化膜を堆積しゲート側壁部のみを残すよ
うに酸化膜をエツチングする。As mentioned above, the conventional method has a low taK! Since the n1 layer and the high concentration n' layer are formed by ion implantation, there are limits to the junction of the diffusion layer and the control of its depth. In contrast, in the present invention, as shown in FIG. 1(a), the low concentration n-
A region is formed by ion implantation, and an oxide film is deposited by CVD as shown in FIG.
次に第１図（Ｃ１に示す高濃度ｎ゛層をｎ一層の上に成
長させてＬＤＤ構造とする。このときゲート上にはｎ゛
ポリシリコン堆積している。ＭＬＥを用いてエピタキシ
ャル成長を行なえば、ｎ″層の部分の膜厚は単原子層オ
ーダーの精度で制御できる。また単原子層オーダーの精
度で任意の不純物分布を形成することもできる。Next, a high concentration n layer shown in FIG. 1 (C1) is grown on top of the n layer to form an LDD structure. At this time, n polysilicon is deposited on the gate. For example, the film thickness of the n'' layer can be controlled with precision on the order of a monoatomic layer. It is also possible to form an arbitrary impurity distribution with precision on the order of a monoatomic layer.
以下、実施例に基づいて本発明を説明する。第１図ｔａ
ｇ、 （ｂｌにおいてＰ型シリコン基板１の表面上にゲ
ート酸化膜２．ゲート３．フィールド酸化膜４を設けた
後、イオン注入によりソース領域５及びドレイン領域６
にｎ一層を形成する。次にＣＶＤで酸化膜Ｎ７を堆積さ
せた後、ゲート３の側壁を残して酸化膜をエツチングす
る。更に第１１’Ｊ（Ｃ１に示すように、ＭＬＥを用い
てｎ一層の上にｎ゛エピタキシャル成長層８を、ゲート
３の上にｎ゛ポ９２９３フ層９設ける。以上のような方
法でＬＤＤ構造を作れば、ドレイン領域の不純物濃度は
従来のＬＤＤ構造に比べ、十分低くできる。Hereinafter, the present invention will be explained based on Examples. Figure 1 ta
g, (In BL, after providing a gate oxide film 2, a gate 3, and a field oxide film 4 on the surface of a P-type silicon substrate 1, a source region 5 and a drain region 6 are formed by ion implantation.
A single layer is formed on the surface. Next, after depositing an oxide film N7 by CVD, the oxide film is etched leaving the sidewalls of the gate 3 intact. Furthermore, as shown in the 11th J (C1), an n epitaxial growth layer 8 is formed on the n single layer using MLE, and an n po 9293 layer 9 is formed on the gate 3. By the above method, the LDD structure is formed. By creating this structure, the impurity concentration in the drain region can be made sufficiently lower than in the conventional LDD structure.
第３図（ａｌ及び（ｂｌは、本発明によるドレイン構造
における不純物濃度分布を示しており、第３図ｉａ＋は
エピタキシャル成長層の不純物濃度を一定にした場合、
第３図ｆｂｌは同じく不純物濃度をステ、プ状に変化さ
せた場合を、それぞれ表わしている。Figure 3 (al and (bl) show the impurity concentration distribution in the drain structure according to the present invention, and Figure 3 ia+ shows the impurity concentration distribution of the epitaxially grown layer when the impurity concentration is constant.
FIG. 3 fbl similarly shows the case where the impurity concentration is changed stepwise and stepwise.
このように、本発明によれば、ドレインを浅くし、かつ
任意の不純物濃度分布を設けることができる。As described above, according to the present invention, the drain can be made shallow and an arbitrary impurity concentration distribution can be provided.
従って本発明によって得られるＬＤＤ構造を有するＭＯ
Ｓ ＦＥＴでは、ドレイン不純物濃度が従来に比べて
低くなり空乏層がドレイン側に伸びる。そのため基板側
で受は持つ電圧が小さくなって電界が弱められ、単チャ
ネル効果を防ぐうえで有効な構造となっている。Therefore, an MO having an LDD structure obtained by the present invention
In SFETs, the drain impurity concentration is lower than in the past, and the depletion layer extends toward the drain side. Therefore, the voltage held by the receiver on the substrate side is reduced, weakening the electric field, making it an effective structure for preventing single-channel effects.
以上述べた様に本発明によれば、高濃度ｎ″層はイオン
注入ではなくエピタキシャル成長により作られる。ＭＬ
ＥやＭＢＥを用いた場合、エピタキシャル成長における
基板温度は８５０℃以下であるためオートドーピングも
十分に小さい。本発明を用いると、従来のイオン注入を
用いる方法では形成できないようなＬＤＤ構造が実現で
き、従来のＬＤＤ構造に比べてドレイン不純’ｊ！１１
？ｍ度をより低く、拡散層の深さをより浅くすること
ができる。As described above, according to the present invention, the high concentration n'' layer is formed not by ion implantation but by epitaxial growth.ML
When E or MBE is used, the substrate temperature during epitaxial growth is 850° C. or lower, so autodoping is sufficiently small. By using the present invention, an LDD structure that cannot be formed using conventional ion implantation methods can be realized, and drain impurity 'j! 11
? m degree can be lowered and the depth of the diffusion layer can be made shallower.
従ってＭＯＳ ＦＥＴの微細化に伴う短チャネル効果
防止のうえで著しい効果がある。Therefore, it is extremely effective in preventing short channel effects caused by miniaturization of MOS FETs.
第１図（ａｌ〜（Ｃ１は、本発明を実施するに際して製
作したＭＯＳ ＦＥＴの製造工程順断面図である。
第２図［ａｌ〜（Ｃ１は、従来の方法を用いたＩ、ＤＤ
構造を存するＭＯＳ ＦＥＴの製造工程順断面図であ
る。第３図＋ａｌは、本発明の高濃度エピタキシャル成
長によるドレイン構造において、エピタキシャル成長層
の不純物濃度を一定にした場合のドレイン領域における
深さ方向不純物濃度分布図であり、第３図ｆｂｌは、同
じくエピタキシャル成長層の不純物濃度をステップ状に
変化させた場合のドレイン領域における深さ方向不純物
１度分布図である。
１・・・Ｐ型シリコン基板
２・・・ゲート酸化膜
３・・・ゲート
４・・・フィールド酸化膜
５・・・ソース領域
６・・ ・ドレイン領域
７・・・ＣＶＤ酸化膜
８・・・ｎ０工ピタキシヤル層
９・・・ｎ９ポリシリコン
以上
出願人 セイコー電子工業株式会社
第２図Figure 1 (al ~ (C1 is a cross-sectional view of the MOS FET manufactured in the process of carrying out the present invention in the order of manufacturing steps.
FIG. 3 is a cross-sectional view showing the manufacturing process of a MOS FET having a structure. FIG. 3+al is a depth direction impurity concentration distribution diagram in the drain region when the impurity concentration of the epitaxial growth layer is kept constant in the drain structure formed by high concentration epitaxial growth of the present invention, and FIG. FIG. 3 is a depth direction impurity distribution diagram in the drain region when the impurity concentration is changed stepwise. 1...P-type silicon substrate 2...Gate oxide film 3...Gate 4...Field oxide film 5...Source region 6... -Drain region 7...CVD oxide film 8... N0 Pitaxial Layer 9...N9 Polysilicon and above Applicant: Seiko Electronic Industries Co., Ltd. Figure 2
Claims (2)
レインをイオン注入により低濃度ｎ＾−領域とした後に
ゲートを設け、更に酸化膜層を堆積した後、分子層エピ
タキシャル法を用いてソース・ドレインｎ＾−層の上に
高濃度ｎ＾＋層を選択的に成長させることにより、ＬＤ
Ｄ構造を設けたことを特徴とする絶縁ゲート電界効果ト
ランジスタ。(1) In order to prevent the short channel effect, the source and drain are made into low concentration n^- regions by ion implantation, a gate is provided, an oxide film layer is deposited, and the source and drain are formed using molecular layer epitaxial method. By selectively growing a high concentration n^+ layer on the drain n^- layer, the LD
An insulated gate field effect transistor characterized by having a D structure.
分子線エピタキシャル法あるいは気相成長法により行な
われることを特徴とする特許請求の範囲第１項記載の絶
縁ゲート電界効果トランジスタ。(2) selectively forming the high concentration n^+ layer;
2. The insulated gate field effect transistor according to claim 1, wherein the insulated gate field effect transistor is formed by a molecular beam epitaxial method or a vapor phase growth method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61289163A JP2515524B2 (en) | 1986-12-04 | 1986-12-04 | Method for manufacturing insulating gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61289163A JP2515524B2 (en) | 1986-12-04 | 1986-12-04 | Method for manufacturing insulating gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63142677A true JPS63142677A (en) | 1988-06-15 |
| JP2515524B2 JP2515524B2 (en) | 1996-07-10 |
Family
ID=17739574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61289163A Expired - Lifetime JP2515524B2 (en) | 1986-12-04 | 1986-12-04 | Method for manufacturing insulating gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2515524B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270272A (en) * | 1988-04-20 | 1989-10-27 | Fujitsu Ltd | Manufacture of mis type semiconductor device |
| US4998150A (en) * | 1988-12-22 | 1991-03-05 | Texas Instruments Incorporated | Raised source/drain transistor |
| EP0452495A4 (en) * | 1989-07-27 | 1991-08-02 | Seiko Instr Inc | Misfet and method of producing the same. |
| US5198378A (en) * | 1988-10-31 | 1993-03-30 | Texas Instruments Incorporated | Process of fabricating elevated source/drain transistor |
| US6335252B1 (en) | 1999-12-06 | 2002-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device manufacturing method |
-
1986
- 1986-12-04 JP JP61289163A patent/JP2515524B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270272A (en) * | 1988-04-20 | 1989-10-27 | Fujitsu Ltd | Manufacture of mis type semiconductor device |
| US5198378A (en) * | 1988-10-31 | 1993-03-30 | Texas Instruments Incorporated | Process of fabricating elevated source/drain transistor |
| US4998150A (en) * | 1988-12-22 | 1991-03-05 | Texas Instruments Incorporated | Raised source/drain transistor |
| EP0452495A4 (en) * | 1989-07-27 | 1991-08-02 | Seiko Instr Inc | Misfet and method of producing the same. |
| EP0452495A1 (en) * | 1989-07-27 | 1991-10-23 | Seiko Instruments Inc. | Misfet and method of producing the same |
| US6335252B1 (en) | 1999-12-06 | 2002-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2515524B2 (en) | 1996-07-10 |
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