JPH01270272A - Manufacture of mis type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the generation of hot carrier, and improve device characteristics, by forming a side wall after a source layer and a drain layer of low concentration are formed, and selectively growing a source region and a drain region of high concentration containing phosphorus. CONSTITUTION:On a semiconductor substrate 11, a gate electrode 13 coated with an insulating film 21 is formed via a gate insulating film 12; then a source layer 17 and a drain layer 18 of low concentration are formed by implanting arsenic ions or phosphorus ions; after a side wall insulating film 22 is formed on the side wall of a gate electrode 13, a source region 15 and a drain region 16 of high concentration containing phosphorus are selectively formed on the source layer 17 and the drain layer 18. Thereby, the generation of hot carrier is reduced, device characteristics such as threshold voltage and mutual conductance are stabilized, and the short channel effect is reduced.

Description

[Detailed Description of the Invention] [Summary] Among the methods for manufacturing MIS semiconductor devices, this method involves forming a gate insulating film on a semiconductor substrate in order to improve the deterioration of device characteristics due to hot carrier generation. a step of forming a gate electrode covered with an insulating film through a process, a step of implanting arsenic ions or phosphorus ions to form a low concentration source layer and a drain layer, and then a step of forming a low concentration source layer and a drain layer on the sides of the gate electrode. The method is characterized by comprising a step of forming a sidewall insulating film (sidewall), and then a step of selectively forming a source region and a drain region containing high concentration of phosphorus on the source layer and drain layer. .

[Industrial Application Field] The present invention relates to a method for manufacturing an MIS type semiconductor device (MISFET), and particularly to a method for manufacturing an MIS type semiconductor device (MISFET).
rc and drain) structure.

MISIG, which is composed of MTSFETs, can be highly integrated compared to bipolar ICs, so it is
It is widely used in memory circuits such as OM and other electronic circuits, but as integration and miniaturization progress further,
Device characteristics tend to deteriorate in inverse proportion to this, and therefore,
A forming method that does not cause deterioration of characteristics is desired.

[Problems to be solved by conventional technology and invention] Figure 3 (
al to (d) show cross-sectional schematic diagrams of conventional MISFETs (old S field effect transistors), in which (a) is a MISFET with a normal structure, and (b) is a MISFET with an LDD structure (7
) MrSFET, (C) is a MISFE with SSD structure.
T, same figure (dl is a composite SSD incorporating an LDD structure)
This is a MISFET structure. The symbols in these figures are the same, ■ is a p-type silicon substrate, 2 is a gate insulating film,
3 is a gate electrode, 4 is a field insulating film, and 5 is an n+ type (
(high concentration) source region, 6 is n+ type drain region, 7 is n
- type (low concentration) source layer, and 8 indicates an n- type drain layer.

The basic manufacturing method for the normal MISFET shown in FIG.
The gate electrode 3 is first formed, and the source/drain regions 5.6 are formed using it and the field insulating film 4 as a mask.
In this method, the area is defined by ion implantation.

However, as miniaturization progresses, so-called hot carriers are generated due to concentration of electric field near the drain, and these hot carriers invade the gate insulating film, causing a shift in threshold voltage vth and a decrease in mutual conductance gm. There are drawbacks such as deterioration of device characteristics.

Therefore, LDD (Light
ly Doped Drain) structure has been proposed. In this structure, an n-type source layer 7 and drain layer 8 are provided close to the gate insulating film.The existence of this low concentration drain layer 8 relieves the electric field concentration near the drain and prevents the generation of hot carriers. suppressed.

However, even if these n-type source and drain layers are provided, as miniaturization progresses, the source and drain will become closer together (therefore, a short channel effect will appear, causing problems such as a decrease in the withstand voltage of the source and drain). .

Therefore, in order to improve this, the SS shown in Figure 3 (C1)
D-structure MISFETs have been proposed. In this SSD structure FET, a gate insulating film and a gate electrode are first produced, and the source and drain regions are selectively grown epitaxially using this and the field insulating film 4 as growth blocking films.
Furthermore, ions are implanted to make it an n+ type. In such a structure, the junction depth of the source and drain can be effectively made shallow, so that the drop in breakdown voltage can be reduced.

However, as layer miniaturization progresses and the power supply voltage remains constant (currently constant at around 5V), the electric field strength becomes even higher, even in the LDD structure shown in Figure 3(b). A problem arises in which hot carriers are generated at the end (indicated by an arrow) of a high concentration n+ type drain region. Therefore, the third
A MISFET with a composite SSD structure as shown in Figure Td) has been devised.

However, this composite MISFET shown in Figure 3 (dl)
The device characteristics are greatly influenced by the formation method, and the problem of carrier generation at the edge of the high concentration region has not been completely solved.

Therefore, the present invention proposes a forming method aimed at alleviating this problem and improving the deterioration of device characteristics due to hot carrier generation.

[Means for solving the problem] The purpose is to form a gate electrode covered with an insulating film on a semiconductor substrate via a gate insulating film, and then implant arsenic ions or phosphorus ions to form a low concentration a step of forming a source layer and a drain layer, a step of forming a sidewall insulating film (sidewall) on the side of the gate electrode, and a step of forming a high concentration source containing phosphorus on the source layer and the drain layer. This is accomplished by a manufacturing method that includes selectively forming regions and drain regions.

[Operation] That is, the present invention is a method of forming a low concentration source layer and a drain layer, then forming a sidewall, and then selectively growing a high concentration source region and a drain region containing phosphorus.

Conventionally, the highly doped source and drain regions in an LDD structure contain arsenic, but the method of forming them according to the present invention allows them to contain phosphorus. In the conventional LDD structure, when phosphorus is contained in the high concentration region, phosphorus with a large diffusion coefficient diffuses to the low concentration layer, making it difficult to construct an LDD structure. The region can contain phosphorus to form an LDD structure, and the concentration gradient at the edge of the high concentration region (at the boundary between the high concentration region and the low concentration layer) is relaxed, and the generation of hot carriers can be reduced. It is. Thus, device characteristics are improved and stabilized.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

FIGS. 1(a) to ffl show step-by-step cross-sectional views of the forming method according to the present invention, and will be explained step by step.

Refer to FIG. 1(a): First, after forming the field insulating film 14 on the p-type silicon substrate 11 by the LOCOS method,
Thermal oxidation to form gate insulating film 12 (film thickness: 100 to 200 layers)
Then, a polycrystalline silicon film 13 doped with phosphorus (thickness 2000~
A 5i02 (silicon oxide) film 21 (thickness 1
000-3000 people). Next, this SiO
The two layers of the two-layer film 21 and the single-crystalline silicon film 13 are formed into the shape of a gate electrode (electrode width of about 0.5 to 1 μm) using photolithography and etching techniques.

Note that the polycrystalline silicon film that will become the gate electrode 13 is made by CVD.
After a non-doped polycrystalline silicon film is grown by a method, phosphorus may be diffused to form a doped polycrystalline silicon film.

Refer to FIG. 1('b); Next, arsenic ions are implanted through the gate insulating film 12 to form a low concentration n-type source layer 17 and drain layer 18. At this time, the dose is about 1013/ad, but phosphorus ions may be implanted instead of arsenic ions. Further, the activation heat treatment of the source layer 17 and the drain layer 18 may be performed at the same time as the activation heat treatment of the highly doped source and drain regions in a later step, for example.

See Figure 1(C); Next, the entire surface is coated with 5
Depositing i02 film 22 (thickness 1000 to 3000),
5 using reactive ion etching (RIE) method
The i02 film 22 is vertically anisotropically etched to form a sidewall insulating film 22 only on the sides of the gate electrode 13+5102 film 21.
(side walls) are formed, and the source layer 17 and drain layer 18 are exposed.

See FIG. 1+d); then, the 5i02 film 21. Gate electrode 13, sidewall insulating film 22, and field insulating film 14
and the source region 15 and the drain region 16 (all film thicknesses of 3,000 to 6,000 wafers) are selectively used as a growth prevention film.
is grown epitaxially (crystal growth).

FIG. 1 (see el; next, phosphorus ions are implanted into the source region 15 and drain region 16 at a dose of about 10/cJ, and then an activation heat treatment is performed at 800 to 1000°C.
The source region 15 and drain region 16 are formed to be n+ type with high concentration. Although this activation heat treatment may also be used as a post-process, the amount of phosphorus-containing impurities becomes approximately 10 /d due to this activation. In addition, since phosphorus ions have a smaller mass and a larger diffusion coefficient than arsenic ions, they partially diffuse into the n-type source layer 17 and drain layer 18, resulting in a concentration gradient at the ends of the highly concentrated source region 15 and drain region 16. decreases. Note that 23 in the figure indicates a 5i02 film formed on the surface during the activation heat treatment.

See Figure 1(f); finally, phosphorus silicate glass (PS
G) Deposit film 24, open contact holes, and pattern aluminum wiring 25 to complete the device.

The above is an embodiment of the formation method according to the present invention, and such an SSD structure has a highly doped n+ type source region 15.
Since the drain region 16 has a laminated structure in which the upper surface is higher than the gate insulating film, even if a high concentration impurity region is formed by containing phosphorus with a large diffusion coefficient, the region is maintained and the low concentration impurity region is formed. Disappearance of the concentrated impurity layer can also be avoided.

In addition, in the process explained in FIG. 1(dl), as another method, a method of selectively growing the n+ type source region 15 and drain region 16 containing phosphorus can also be adopted.

Moreover, the gate electrode 13 is not only made of polycrystalline silicon film, but also
It may be formed of a metal film, a metal silicide film, or a composite film thereof, and the sidewall insulating film 22 (sidewall) may be formed of silicon nitride (SiO2) in addition to the SiO2 film.
3Na) film may also be used.

According to the above-described formation method, the generation of hot carriers is reduced, thereby stabilizing device characteristics such as Vth (threshold voltage) and gm (mutual conductance). In addition, the effective length of the channel is increased and the short channel effect is suppressed, and the method for forming it is relatively easy.

The following Figure 2 shows a relationship diagram between gate length and lifetime, and the gm of the conventional LDD structure (see Figure 3 (b)) and the composite SSD structure according to the present invention is reduced by 10%. It is clear from this figure that the structure according to the present invention is improved.

[Effect of the invention] As can be seen from the description of the above embodiments, M according to the present invention
ISFETs have the effect of reducing the generation of hot carriers, stabilizing device characteristics such as threshold voltage and mutual conductance, and reducing short channel effects similar to conventional SSD structures.

Therefore, MI constituted by MISFET according to the present invention
Src contributes to high performance.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views in the order of steps of the formation method according to the present invention, FIG. 2 is a relationship diagram between gate length and lifetime, and FIGS. 3(a), (b), (c). ) and (d) are cross-sectional schematic diagrams of a conventional MISFET. In the figure, 1.11 is a p-type silicon substrate, 2.12 is a gate insulating film, 3.13 is a gate electrode (polycrystalline silicon film), and 4.14
is a field insulating film, 5.15 is a heavily doped n++ source region, 6.16 is a heavily doped n+ drain region, 7.17 is a lightly doped n-type source layer, and 8.18 is a lightly doped n-type Drain layers, 21 and 23 are 5
22 is a sidewall insulating film, 24 is a PSG film, and 25 is an aluminum wiring. Figure 1 (Object L) IOO￥o t = F -- Ij'y Wise Buddha's Writings

Claims (1)

[Claims] A step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate insulating film, and then implanting arsenic ions or phosphorous ions to form a low concentration source layer and a drain layer. Next, forming a sidewall insulating film (sidewall) on the side of the gate electrode. Next, selectively forming a high concentration source region and a drain region containing phosphorus on the source layer and drain layer. 1. A method for manufacturing an MIS type semiconductor device, comprising a step of forming a semiconductor device.