JPH02139965A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of characteristics of a transistor by forming P-type and N-type MOS transistors so that their sidewall insulating films may be different in width. CONSTITUTION:As to a silicon oxide film 16 which is formed with vapor growth in order to form sidewall insulating films, a region where a P-type transistor is formed is covered with a photoresist 17 and the silicon oxide film 16 is etched with a reactive ion etching process and further, removal of the resist 17 allows the sidewall insulating films 19 to be formed on both side faces of a gate electrode 13 in an N-type MOS transistor and the films 19 are covered with a resist 110. The silicon oxide film 16 which still remains on an N-type well is removed with the reactive ion etching process to form the sidewall insulating films on both sides of a gate electrode in a P-type MOS transistor. The sidewall insulating films in N-type and P-type MOS transistors are formed into different sizes W1 and W2 in width; however, W2 gets larger than W1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a semiconductor device.

[Summary of the invention]

In a method for manufacturing metal-insulating-film-semiconductor transistors (hereinafter referred to as MIS transistors) on the same semiconductor substrate, an insulating film is formed on both sides or one side in the length direction of a gate electrode, and the insulating film is used as a mask to remove impurities. In the step of forming the source and drain by ion implantation or impurity diffusion, the length of the insulating film in the gate electrode length direction is made different for the P-type Mis transistor and the N-type MIS transistor. .

Boron or boron dihydride BFt is generally used for the source and drain of a P-type MIS transistor. Due to the large diffusion coefficient of boron, the source and drain of a P-type MISI transistor are easily diffused both in the depth direction and in the lateral direction. channel effect,
The drain breakdown voltage deteriorates significantly. When an insulating film is provided on both sides or one side in the length direction of the gate electrode and the source and drain are formed by ion implantation, the length of the insulating film is longer in a P-type MIS transistor than in an N-type MIS transistor.

In this way, even if the lateral diffusion of boron due to the thermal process after ion implantation is large to some extent, the effective channel length will not become so small, and the short channel effect and drain breakdown voltage will be reduced to the same level as an N-type MIS transistor. Comes to have excellent properties. Since the gate electrode length of the P-type M*S transistor is not made longer than that of the N-type MIS transistor, it also has the advantage of maintaining a high degree of integration.

[Conventional technology]

FIG. 2 (al~+
The conventional technology will be explained with reference to FIGS. This will be explained by taking a metal/oxide film/semiconductor transistor (hereinafter referred to as a MOS transistor) as an example.

Figure 2 1dl shows an N-type MO on the same semiconductor silicon substrate.
FIG. 3 is a cross-sectional view showing an intermediate step among the steps of forming three transistors and a P-type MOS transistor.

21 is a P-type silicon substrate, 22 is a gate oxide film, 23 is a thick oxide film for separating the N-type MOS transistor and P-type MO3 transistor, 24 is a polycrystalline silicon film that becomes a gate electrode, 25 is an N-type A part of the source and drain of the MOS transistor is filled with N-type impurity (for example, phosphorus) with a low concentration. 26 is a well formed with N-type impurity for forming a PMO3 transistor therein. (Hereinafter referred to as N-well) FIG. 2 (bl) is a cross-sectional view of a semiconductor device showing a process in which an oxide film 27 with a thickness of several thousand angstroms is deposited by vapor phase growth.

Figure 2 10) is reactive ion etching (hereinafter referred to as RIE).
A semiconductor device showing the process of etching the oxide film 27 grown in a vapor phase using a method (hereinafter referred to as a sidewall insulating film) to leave an oxide film with a width W on both sides of the gate electrode (hereinafter, this insulating film will be referred to as a sidewall insulating film). FIG. 2 is a cross-sectional view of the device.

The sidewall insulating films 28 and 29 are formed on both sides of the gate electrodes of the N-type MO5 transistor and the P-type MO3I-transistor, respectively, and have the same width dimension W.

1dl in FIG. 2 shows that a resist 210 is placed over the top of the N-well where a P-type MOS transistor is formed, and a high concentration of N is applied.
FIG. 2 is a cross-sectional view of a semiconductor device showing a step of ion-implanting a type impurity (for example, arsenic).

High concentration N-type MO3 transistor source electrode 212
and a drain electrode 213 are formed.

FIG. 2 1dl shows a step in which the upper part of the side where the N-type MOS transistor is formed is covered with a resist 214, and a high concentration of P-type impurity (for example, boron or boron dihydride) 215 is ion-implanted. FIG. 2 is a cross-sectional view of a semiconductor device. A source electrode 216 and a drain electrode 217 of a high concentration P-type MO3 transistor are formed.

FIG. 3 1al and FIG. 3 1bl separately show cross sections of the N-type MO3 transistor and the P-type MOS transistor shown in FIG. 2(e). Gate electrodes 31 and 36 made of polycrystalline silicon have lengths.

In order to make the source electrode and drain electrode function as electrodes, a high temperature thermal process is applied after impurity ions are implanted.

At this time, impurities forming the source and drain diffuse not only in the depth direction of the silicon semiconductor but also in the lateral direction parallel to the silicon surface.

In an N-type MOS transistor, the source electrode 33. is formed with a low concentration of N-type impurity. A drain electrode 34 and a source electrode 32 formed of a high concentration of N-type impurity. Which of the drain electrodes 35 undergoes greater lateral diffusion due to the thermal process depends on the amount of impurity implanted, the type of impurity, and the conditions of the thermal process.

In the case of FIG. 3 1al, the lateral diffusion is larger in the source electrode 33 and the drain electrode 34 having a lower concentration than in the source electrode 32 and the drain electrode 35 having a higher concentration. At this time, the effective length between the source electrode and the drain electrode is represented by Leff.

In the P-type MOS transistor shown in FIG. This is done by ion implantation.Boron has a very large diffusion due to the thermal process, and also has a large spread in the lateral direction.Even if the length W of the insulator formed on the side surface in the longitudinal direction of the gate wire is the same, the P-type MO3 transistor The length Lef between the source and drain electrodes of
f is usually the length between the source and drain electrodes of an N-type MOS transistor and is smaller than off.

For this reason, especially in P-type MO3 transistors, the effective length Leff between the source and drain electrodes is short, and when a voltage is applied between the drain and the source, an abnormally large current begins to flow.The drain voltage (bunch voltage) is extremely low. the gate voltage (threshold voltage) when current starts to flow between the source and drain is very small, or the effective length Le4 between the source and drain
A short channel effect occurs in which the value of the threshold voltage tends to change greatly due to a slight change in f, resulting in poor transistor characteristics.

(Problem to be solved by the invention) In the conventional technology, normally an N-type MO3 transistor and a P-type MO3 transistor are used.
The width dimensions of the sidewall insulating films formed on the side surfaces of the gate electrodes of the O3 transistors were the same. For this reason, in P-type MO3) transistors that use boron, which has a particularly high thermal diffusion, as the source and drain electrodes, the effective length between the source and drain electrodes becomes short, resulting in the aforementioned drop in punch-through voltage and short channel effect. It was easy. The present invention is particularly intended to improve the drawbacks of this P-type MO3 transistor.

[Means to solve the problem]

Sidewall insulating films of a P-type MOS transistor and an N-type MOS transistor are formed to have different width dimensions.

In particular, in order to prevent deterioration of transistor characteristics due to lateral diffusion of boron used in the source and drain electrodes of P-type MOS transistors, P-type MO3! - The width of the sidewall insulating film of the transistor is made longer than that of the N-type MOS transistor.

[Effect]

The width dimension of the sidewall insulating film of a P-type MOS transistor is
If it is made larger than that of an OS transistor, even if the lateral diffusion of boron due to heat is increased to some extent, the substantial length between the source electrode and the drain electrode is prevented from becoming short.

[Embodiment] FIG. 1 is a step-by-step sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. This will be explained with reference to FIG.

FIG. 1 [al] is a cross-sectional view of a semiconductor device showing a step before forming sidewall insulating films on both sides of a gate electrode of an N-type MOS transistor. 1) is a P-type silicon substrate, 12
．． 12° is a gate oxide film, 13.13° is a gate electrode made of polycrystalline silicon, 14 is an N-well made of N-type impurity that forms a P-type MO5 transistor therein, 1
5 is a thick oxide film for electrically separating the N-type MOS transistor and P-type MO3I- transistor, 16 is a silicon oxide film formed by vapor phase growth to form a sidewall insulating film, and 17 is P-type MO3I- The photoresists 18 and 18' covering the regions where the transistors are to be formed respectively indicate the source and drain voltages 1 of the N-type MO5 transistors, each consisting of a thin concentration of N-type impurities.

FIG. 1 fbl shows that after the process of FIG. 1 (al), the silicon oxide film 16 is etched by reactive ion etching,
Furthermore, a cross-sectional view of the semiconductor device after the step of removing the resist 17 is shown. Here, sidewall insulation 1#19 is formed on both sides of the gate electrode 13 of the N-type MOS transistor. After this, a resist 1)0 is placed over the region where the N-type MO3 transistor is to be formed.

FIG. 1 fC1 shows a cross-sectional view of the semiconductor device after the step of removing the silicon oxide film 16 remaining on the N-well by reactive ion etching.

Here, sidewall insulating films 1) 1 are formed on both sides of the gate electrode of the P-type MO3 transistor. Here, the width dimension W of the sidewall insulating film of the N-type MO5 transistor,...! : The width dimension W2 of the sidewall insulating film of the P-type MO3 transistor is different. - For boat fishing, make W2 larger than Wl.

In order to make W and W2 different values, for example, the etching time of the silicon oxide film may be changed.

Figure 1 (dl is a P-type MO3 transistor.
FIG. 3 is a cross-sectional view of a semiconductor device showing a step of covering a region with a photoresist 12; In this state, a high concentration of N-type M
Source electrode 1) 3 and drain electrode 1 of OS transistor
)3'' is formed by ion implantation.

FIG. 1 (tel) is a cross-sectional view of a semiconductor device showing the step of covering the region where the N-type MOS transistor is formed with photoresist (1) 4. In this state, a source electrode 1) 5 and a drain electrode 1) 5' of a P-type MOS transistor are formed by ion implantation.

Figure 1(f) shows the photoresist 1]4 of Figure 1fe).
The width dimension W of the sidewall insulating film 19 of the N-type MOS transistor and the width dimension Wz of the sidewall insulating film of the P-type MO5 transistor are shown in the process of forming an N-type MOS transistor and a P-type MOS transistor after removing It's different.

FIG. 4 shows a cross-sectional view of a semiconductor device formed by the manufacturing method of the present invention. The functions of each part in Figure 4,
The names are exactly the same as in the case of FIG. 1 (al to ffl).

The difference between FIG. 4 and FIG. 1 ffl is that the sidewall insulating film is formed only on the drain side of the gate electrode in both the N-type MOS transistor and the P-type MOS transistor. 41 and 42 represent sidewall insulating films of an N-type MOS transistor and a P-type MOS transistor, respectively. N! ! ! In the MOS transistor, an electrode 44 made of a thinly concentrated N-type impurity is formed only on the drain side. 43 and 45 represent a high concentration source electrode and a drain electrode, respectively. 46 and 47 represent the source electrode and drain electrode of a P-type MOS transistor, respectively. Here, the width dimension W of the sidewall insulating film of the N-type MOS transistor is different from the width dimension W4 of the sidewall insulating film of the P-type MO5 transistor.

〔Effect of the invention〕

As explained in detail above, in the semiconductor device formed by the semiconductor device manufacturing method of the present invention, the lateral diffusion of impurities forming the source and drain electrodes can be increased without reducing the degree of integration of the semiconductor integrated circuit. Tomo, M.O.
This has the effect of not reducing the effective channel length of the S transistor. That is, even if the gate electrode length of the MOS transistor is shortened, it has the effect of suppressing the short channel effect, reduction in punch-through voltage, and the like. In particular, the effect of the present invention is particularly excellent in preventing characteristic deterioration of the P-type MO3 transistor by making the width dimension of the sidewall insulating film of the P-type MOS transistor longer than that of the N-type MOS transistor.

[Brief explanation of the drawing]

1+a+ to (') are step-by-step sectional views of the semiconductor device manufacturing method of the present invention, FIG. 2 (al to tel are step-by-step sectional views of the conventional semiconductor device manufacturing method, and FIG. Figure 3 is a cross-sectional view of the structure of an N-type MOS transistor manufactured using the conventional manufacturing method (bl is a cross-sectional view of the P-type MOS transistor manufactured using the conventional manufacturing method).
FIG. 4 is a structural cross-sectional view of an S transistor, and FIG. 4 is a structural cross-sectional view of another semiconductor device formed by the manufacturing method of the present invention. 1) ・ ・ ・ ・ ・ ・ ・ 12, 12° ・ ・ ・ ・ 13, 13' ・ ・ ・ 14・ ・ ・ ・ ・ ・ 19.1) 1,41.42 W+, Wz, W3. Wa 18, 44 ・ ・ ・ ・ 1) 3.43. 45. ・ 1) 5.46. 47. ・P-type semiconductor substrate・Gate oxide film・Gate electrode・N-well・Side wall insulating film・Width dimension of side wall insulating film・Low concentration N-type source/drain electrode・High concentration N-type source・Drain electrode, high concentration P-type source, drain electrode and above Applicant Keinosuke Hayashi, Patent Attorney, Seiko Electronics Co., Ltd.

Claims (2)

[Claims] (1) N-type MIS transistor and P-type on the same semiconductor substrate
In a method for manufacturing a semiconductor device that forms a type MIS transistor, when an insulator is provided at the longitudinal end of the gate electrode and then an impurity is formed by ion implantation or impurity diffusion, the length of the gate electrode of the insulator is A method of manufacturing a semiconductor device, characterized in that the N-type MIS transistor and the P-type MIS transistor are formed to have different lengths in the width direction. (2) The gate electrode of the insulator is formed so that the length in the longitudinal direction of the P-type MIS transistor is longer than that of the N-type MIS transistor. A method for manufacturing a semiconductor device.