JPS6017946A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6017946A JPS6017946A JP58126631A JP12663183A JPS6017946A JP S6017946 A JPS6017946 A JP S6017946A JP 58126631 A JP58126631 A JP 58126631A JP 12663183 A JP12663183 A JP 12663183A JP S6017946 A JPS6017946 A JP S6017946A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- type
- boron
- arsenic
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
Description
【発明の詳細な説明】
本発明は、高速動作を目的とするＣＭＯ８半導体素子に
関する。ＭＯ８型トランジスタでスイッチング特性を決
める要素として、
（１） 閾値電圧（ｖｔｈ ）
（２）電流増巾率（β）
（３）寄生容量（ＯＬ）
等があり、さらに、容量に対しては、次段のトランジス
タの負荷容量がある。ｖｔｈは、使用上の制約があり、
電源電圧によりほぼ決められる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a CMO8 semiconductor device intended for high-speed operation. The factors that determine the switching characteristics of MO8 type transistors include (1) threshold voltage (vth), (2) current amplification rate (β), and (3) parasitic capacitance (OL). There is a load capacitance of each stage transistor. vth has usage restrictions,
It is almost determined by the power supply voltage.
そこで、ＭＯＳ）ランジスタを高速化する一般的な方法
としては、βを大きくし、Ｃ１を小さくすることが考え
られる。そこで、本発明は、βを大きくシ、シかもＯＬ
を低減することを可能とするものであり、さらに、０Ｍ
０Ｅｌｉ素子固有の問題である、寄生サイリスタ構造か
ら生じるラッチアップ現象にも強いものとなる。Therefore, a general method for increasing the speed of a MOS transistor is to increase β and decrease C1. Therefore, in the present invention, β can be increased, and OL
It is possible to reduce the 0M
It is also resistant to the latch-up phenomenon caused by the parasitic thyristor structure, which is a problem specific to OEli devices.
第一図が、本発明の実施例の工程断面図である。ここで
は、Ｎ型シリコン基板を例にして説明するがＰ型シリコ
ン基板でも同様に行なえる。Ｎ型シリコン基板１０１上
に、２ないし２０μ常程度の溝を形成後、Ｐ型エピタキ
シャルシリコン層１０２を形成し、上記溝をエビタキシ
ャルシリコン層で埋める。次に、チャネルストッパー１
０３及び１０４を不純物拡散により形成後、素子分周［
鮮として、シリコン酸化膜１０５を形成し、ゲート酸化
膜１０６を熱酸化により形成する。次に、チャネル部を
形成するようＮ型基板１０１領域に、リン、ヒ素等Ｎ型
不純物１０８を、Ｐ型エピ１０２領域に、ボロン等Ｐ型
不純物１０７を各々浅くイオン打込み形成する。この時
、この不純物により、目的とするｖｔｈに合せる。次に
、ゲート電極１０９を形成する。本実施例では、ゲート
電極１０９の材料として、モリブデン珪化物を用いた。FIG. 1 is a process sectional view of an embodiment of the present invention. Here, an explanation will be given using an N-type silicon substrate as an example, but the same process can be performed with a P-type silicon substrate. After forming a groove of about 2 to 20 μm on an N-type silicon substrate 101, a P-type epitaxial silicon layer 102 is formed and the groove is filled with the epitaxial silicon layer. Next, channel stopper 1
After forming 03 and 104 by impurity diffusion, element frequency division [
First, a silicon oxide film 105 is formed, and a gate oxide film 106 is formed by thermal oxidation. Next, an N-type impurity 108 such as phosphorus or arsenic is ion-implanted into the N-type substrate 101 region, and a P-type impurity 107 such as boron is formed into the P-type epitaxial region 102 by shallow ion implantation to form a channel portion. At this time, this impurity adjusts the target vth. Next, a gate electrode 109 is formed. In this example, molybdenum silicide was used as the material for the gate electrode 109.
さらに、イオン打込みにより、上記ゲート電極１０９の
自己整合により、ボロン拡散Ｎ１１１及び、ヒ素拡散Ｍ
１１０を、各々、Ｐチャネル領域及びＮチャネル領域に
、拡散形成を行なう。このとき、上記のＰ型不純物層１
０８及びＮ型不純物層１０７と同じ、もしくは深くなる
ようボロン及びヒ素を拡散する。この後、ＰＥＧをデボ
後、コンタクトホールを形成し、金属配線を行ない、パ
ッシベーションＭ莫をデボし、ポンディングパッドを（
３）
作る。次に、本発明のＣＭＯ８半導体素子の特徴につい
て述べる。Further, by ion implantation, self-alignment of the gate electrode 109 results in boron diffusion N111 and arsenic diffusion M.
110 is diffused into the P-channel region and the N-channel region, respectively. At this time, the above P-type impurity layer 1
Boron and arsenic are diffused so as to be the same as or deeper than the N-type impurity layer 107 and the impurity layer 107. After this, after debossing the PEG, forming contact holes, performing metal wiring, debossing the passivation layer, and bonding pads (
3) Make. Next, the characteristics of the CMO8 semiconductor device of the present invention will be described.
（１）Ｐチャネル及びＮチャネルトランジスタともに、
ゲート電極下のチャネル部のみ、拡散層が浅く形成され
ている。尚ｖｔｈはこの拡散層の表面近傍（１０００〜
５ｏｏｏＸ）の濃度により決められている。よって、ド
レインと接触する領域の全んどが、Ｎ型基板及びエビ層
であり、ドレイン−サブ間のジャンクション容量は、Ｐ
及びＮチャネルとも、Ｎ型基板及びエビ層の不純物濃度
により決定される。そこで、これらの不純物濃度を低く
設定することにより、ドレイン容量は、低減出来る。(1) Both P-channel and N-channel transistors,
A shallow diffusion layer is formed only in the channel portion under the gate electrode. Note that vth is near the surface of this diffusion layer (1000~
5oooX). Therefore, the entire region in contact with the drain is the N-type substrate and the shrimp layer, and the junction capacitance between the drain and the sub is P
Both the N channel and the N channel are determined by the impurity concentration of the N type substrate and the shrimp layer. Therefore, by setting the concentration of these impurities low, the drain capacitance can be reduced.
（２）一般に、基板濃度を低くシ、拡散層を浅くすると
、寄生サイリスク構造から起こる、ラッチアップ現象に
弱くなるが、本発明の゛ように、Ｎチャネル部をエビ層
上に形成することにより、回避できる。(2) Generally, when the substrate concentration is low and the diffusion layer is shallow, it becomes vulnerable to latch-up phenomenon caused by the parasitic silicon risk structure, but as in the present invention, by forming the N-channel part on the shrimp layer, , can be avoided.
（３）本発明の方法は、短チヤネル化にマツチして構造
であり、（１）とともに、高速化を目的とする（４）
０ＭＯ８構造となる。(3) The method of the present invention has a structure that is suitable for shortening the channel, and in addition to (1), it has a 0MO8 structure that is aimed at increasing speed.
第１図（（Ｌ）ｅ Ｃｂ）、ＣＣ）は、本発明の工程断
面図である。
１０２は、エピタキシャルシリコンＪｉ、１０７及び１
０８が、イオン打込みにより形成された浅いチャネル部
である。
以 上
第１巨FIG. 1 ((L)e Cb), CC) is a process sectional view of the present invention. 102 is epitaxial silicon Ji, 107 and 1
08 is a shallow channel portion formed by ion implantation. The first giant
Claims (1)
０μ情の溝が形成されていること、該シリコン基板と異
なる型の、エピタキシャル成長による単結晶シリコン層
が、該溝の中に形成されていること、該シリコン基板上
及び該エピタキシャルシリコン層上に異なるチャネルの
ＭＯＳ ）ランジスタが形成され０Ｍ０８構造となるこ
と、Ｐ及びＮチャネルトランジスタともに、チャネル部
が、ソース・ドレイン拡散層より浅い拡散層よりなるこ
とを特徴とする半導体装置。2 or 2 on a part of the N-type or P-type silicon substrate.
A groove with a thickness of 0μ is formed, a single crystal silicon layer of a type different from the silicon substrate and epitaxially grown is formed in the groove, and a different type is formed on the silicon substrate and on the epitaxial silicon layer. Channel MOS) A semiconductor device characterized in that a transistor is formed to have an 0M08 structure, and that the channel portions of both P and N channel transistors are made of a diffusion layer shallower than a source/drain diffusion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126631A JPS6017946A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58126631A JPS6017946A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6017946A true JPS6017946A (en) | 1985-01-29 |
Family
ID=14939964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58126631A Pending JPS6017946A (en) | 1983-07-12 | 1983-07-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6017946A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02235345A (en) * | 1989-03-08 | 1990-09-18 | Rohm Co Ltd | Manufacture of semiconductor device |
| US5086006A (en) * | 1984-12-11 | 1992-02-04 | Seiko Epson Corporation | Semiconductor device and method of production |
| JPH0486794U (en) * | 1990-12-03 | 1992-07-28 | ||
| US5190886A (en) * | 1984-12-11 | 1993-03-02 | Seiko Epson Corporation | Semiconductor device and method of production |
-
1983
- 1983-07-12 JP JP58126631A patent/JPS6017946A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5086006A (en) * | 1984-12-11 | 1992-02-04 | Seiko Epson Corporation | Semiconductor device and method of production |
| US5190886A (en) * | 1984-12-11 | 1993-03-02 | Seiko Epson Corporation | Semiconductor device and method of production |
| JPH02235345A (en) * | 1989-03-08 | 1990-09-18 | Rohm Co Ltd | Manufacture of semiconductor device |
| JPH0486794U (en) * | 1990-12-03 | 1992-07-28 |
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