JPS63204651A - Insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance, to prevent short-channel effect and to improve carrier mobility, by providing three epitaxial layers. CONSTITUTION:Junction capacitance between a substrate 1 and source/drain 5, 6 is reduced by providing a first low-concentration epitaxial layer 2 on the substrate 1, while short-channel effect is prevented by providing a second high- concentration epitaxial layer 3 on the first epitaxial layer 2. Then, a third low-concentration epitaxial layer 4 is provided as a channel region. A field-effect transistor thus constructed is allowed to have desirable resistance to latch-up. Further, the short-channel effect can be prevented and the effective mobility of carriers can be improved.

Description

[Detailed description of the invention] [Industrial application] The present invention has a structure in which three types of epitaxial growth layers with different film thicknesses and impurity concentrations are provided on a high concentration substrate.
The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated as MOS FET) that operates at high speed and with low power consumption.

[Summary of the invention]

The present invention reduces the junction capacitance between the substrate and the source/drain by a first epitaxial growth layer with a low concentration provided on the substrate, and shortens the junction capacitance between the substrate and the source/drain by a second epitaxial growth layer with a high concentration provided on the first epitaxial growth layer. The structure prevents the channel effect and further provides a third epitaxial growth layer with a low concentration on the second epitaxial growth layer to form a channel region, which has a great effect in increasing the speed.

[Conventional technology]

In order to prevent phenomena such as short channel effects and latch-up that occur with the miniaturization of semiconductor devices,
As shown in FIG. 3, an epitaxially grown layer with a thickness of several μm was provided on a highly concentrated substrate. However, in the past, the substrate temperature during epitaxial growth was too high, which caused the influence of autodoping to be large and the source
It has been impossible to form a device structure having a steep impurity concentration distribution in a region shallower than the drain diffusion depth. FIG. 4 is a diagram of the impurity concentration distribution in the depth direction in the channel region of the MOSFET shown in FIG. 3, and the steep impurity concentration distribution described above is not formed in the channel region.

[Problem that the invention seeks to solve]

One of the factors that determines the operating speed of a device is carrier mobility, which is greatly influenced by the impurity concentration in the channel region. As described above, in the conventional technology, in order to sufficiently lower the impurity concentration in the channel region, it was necessary to provide an epitaxially grown layer having a thickness of several μm or more in consideration of autodoping. Furthermore, the impurity concentration of the epitaxially grown layer decreases as it approaches the surface, so punch-through and the like tend to occur.

Conventionally, in order to avoid this, ions were implanted into the channel region, but there was a problem in that the ion implantation reduced the crystallinity of the channel region and did not effectively increase carrier mobility.

Control accuracy of impurity concentration was also not sufficient.

[Means for solving problems]

In order to overcome the drawbacks of the above-mentioned conventional methods, the present invention forms three types of epitaxial growth layers with different impurity concentrations and film thicknesses under the conditions that the substrate temperature is 850°C or less and the film thickness control accuracy is on the order of a single atomic layer. The structure is provided on a high concentration substrate. Therefore, the device structure has excellent launch-up resistance, can prevent short channel effects, and further improves the effective mobility of carriers.

〔Example〕

Hereinafter, the present invention will be described in detail based on Examples. FIG. 1 is a structural sectional view of a MOSFET that is an embodiment of the present invention. In FIG. 1, a substrate 1 has an impurity concentration of 1. O
Xl0I? The first epitaxial growth layer 2 of the P° type of Row 3 has a film thickness of 1500 nm and an impurity concentration of 1. OX
The second epitaxial growth layer 3, which is 1015 cm-' P- type, has a film thickness of 2500 cm and an impurity concentration of 1. Q
P degree type of
It is a P-type of l0I4e11 arch. Further, in FIG. 1, the diffusion depths of the source 5 and drain 6 are both about 3000. Figure 2 shows the MOS FET shown in Figure 1.
3 shows a diagram of the impurity concentration distribution in the depth direction in the channel region of FIG. In FIG. 2, the horizontal axis X takes the channel surface as 0 and points downward as positive.

As is clear from FIG. 2, the present invention has a structure in which a very steep impurity concentration distribution is formed in the channel region. The first epitaxial growth layer 2 in FIG. 1 has a low concentration, so the junction capacitance between the source/drain and the substrate is small, and the second epitaxial growth layer 3 has a high concentration, so it can be used to prevent short channel effects. It is a valid structure. Furthermore, the third epitaxially grown layer is a pure, low-concentration grown layer that is completely unaffected by implantation and annealing, and is a region with little scattering by impurity atoms and high effective carrier mobility.

〔Effect of the invention〕

As described above, the MOSFET according to the present invention has a structure in which parasitics are small, short channel effects can be prevented, and carrier mobility is high. Furthermore, since the crystal growth temperature is 850°C or less, the thickness of the epitaxial growth layer formed on the high concentration substrate can be reduced to about 1710 mm compared to conventional MOSFETs. Needless to say, it is excellent as a lunch stop. In this way, the MOS FET of the present invention achieves high performance in its static and dynamic characteristics that is not found in conventional MOS FETs.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the structure of a MOSFET according to an embodiment of the present invention, and FIG. 2 is a diagram showing the impurity concentration distribution in the depth direction in the channel region of the MOSFET shown in FIG. Figure 3 is a cross-sectional view of the structure of a conventional MOS FET, and Figure 4 is a cross-sectional view of the structure of a conventional MOS FET.
FIG. 3 is an impurity concentration distribution diagram in the depth direction in the channel region of the M'OS FET shown in the figure. l...Substrate 2...First epitaxial growth layer 3...Second epitaxial growth layer 4...Third epitaxial growth layer 5...Source 6...Drain 7...Gate oxidation 8...・Gate or higher

Claims (1)

[Claims] A first epitaxial growth layer having an impurity concentration lower than that of the substrate is formed on a high concentration substrate, and a source/drain diffusion layer having an impurity concentration higher than that of the first epitaxial growth layer is formed on the first epitaxial growth layer. A second epitaxial growth layer having a depth of about the same level or less, and a third epitaxial growth layer on the second epitaxial growth layer having a lower impurity concentration than the second epitaxial growth layer and a film thickness of 500 Å or less. Insulated gate field effect transistor.