KR940004852A - Most transistor structure and manufacturing method - Google Patents

Most transistor structure and manufacturing method Download PDF

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Publication number
KR940004852A
KR940004852A KR1019920014436A KR920014436A KR940004852A KR 940004852 A KR940004852 A KR 940004852A KR 1019920014436 A KR1019920014436 A KR 1019920014436A KR 920014436 A KR920014436 A KR 920014436A KR 940004852 A KR940004852 A KR 940004852A
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South Korea
Prior art keywords
mos transistor
region
transistor structure
channel
manufacturing
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KR1019920014436A
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Korean (ko)
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KR950011022B1 (en
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정원영
신동진
이준성
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문정환
금성일렉트론 주식회사
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Priority to KR1019920014436A priority Critical patent/KR950011022B1/en
Publication of KR940004852A publication Critical patent/KR940004852A/en
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Publication of KR950011022B1 publication Critical patent/KR950011022B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스트랜지스터 구조 및 제조방법에 관한것으로 종래에는 수평채널의 브이 모스트랜지스터 구조로 제조하여 공정시 에피택시 성장과 이방성 식각을 하여야 하므로 제조시 공정이 복잡하고 수평채널 구조로 인해 집적도를 저하시키고 면방향(111)으로 채널이 형성되 캐리어의 이동도와 스위칭속도의 저하로 소자의 특성을 저하시키는 문제점이 있었다.The present invention relates to a structure and a manufacturing method of the MOS transistor conventionally manufactured by the V-MOS transistor structure of the horizontal channel has to be epitaxy growth and anisotropic etching during the process is complicated during the manufacturing process, and the integration density is reduced due to the horizontal channel structure There is a problem in that the channel is formed in the plane direction 111 and the characteristics of the device are deteriorated due to the decrease in mobility and switching speed of the carrier.

본 발명은 소스, 드레인 사이에 형성하여 제조시 에피택시 공정과 이방성 식각 공정을 제거하여 공정을 간단하게 하고 수직게이트에 의해 수직채널을 형성하여 소자의 스위칭속도, 집적도등을 향상하여 소자의 특성을 개선하는 효과가 있다.The present invention simplifies the process by removing the epitaxial process and the anisotropic etching process during the formation between the source and the drain, and forms the vertical channel by the vertical gate to improve the switching speed, integration degree, etc. of the device. There is an effect to improve.

Description

모스트랜지스터 구조 및 제조방법Most transistor structure and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가) 내지 (라)는 본 발명의 모스트랜지스터 제조 공정도를 보인 단면도.(A) to (D) of Figure 2 is a cross-sectional view showing a manufacturing process diagram of the MOS transistor of the present invention.

Claims (6)

기판(1)에 우물영역(10) 및 소스영역(5)이 형성되고, 그 소스영역(5)에 벌크(7)와 드레인영역(7)이 형성되며, 상기 소스영역(5), 벌크(6) 및 드레인영역(7)에 산화막(4) 및 게이트(8)가 구비된 구조의 모스 트랜지스터구조.A well region 10 and a source region 5 are formed in the substrate 1, and a bulk 7 and a drain region 7 are formed in the source region 5, and the source region 5 and the bulk ( 6) and a MOS transistor structure having an oxide film 4 and a gate 8 provided in the drain region 7. 제1에 있어서, 게이트(8)에 의해 수직 채널이 형성되는 모스트랜지스터구조.The MOS transistor structure according to claim 1, wherein a vertical channel is formed by a gate (8). 제1항에 있어서, 게이트(8)에 의해 면방향(010) 또는 (001) 방향으로 채널이 형성되는 모스트랜지스터구조.The MOS transistor structure according to claim 1, wherein a channel is formed in the plane direction (010) or (001) direction by the gate (8). 제1항에 있어서, 게이트(8)에 소스영역(6)(5′) 및 드레인영역(7)(7′)이 쌍으로 형성된 모스트랜지스터구조.The MOS transistor structure according to claim 1, wherein a source region (6) (5 ') and a drain region (7) (7') are formed in pairs in the gate (8). 기판(1)에 우물영역(10), 소스영역(5)과 벌크(6) 및 드레인영역(7)을 형 성한 다음 트랜치 영역(11)을 형성한 후 게이트(8)를 형성하여 제조하는 모스트랜지스터 제조방법.Moss is formed by forming a well region 10, a source region 5, a bulk 6, and a drain region 7 in the substrate 1, forming a trench region 11, and then forming a gate 8. Transistor manufacturing method. 제5항에 있어서, 소스영역(5), 벌크(6), 드레인영역(7) 제조시 이온주입 공정으로 제조하는 모스트랜지스터 제조방법.6. The method of claim 5, wherein the source transistor (5), bulk (6), drain region (7) are manufactured by an ion implantation process.
KR1019920014436A 1992-08-11 1992-08-11 Mosfet and its making method KR950011022B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920014436A KR950011022B1 (en) 1992-08-11 1992-08-11 Mosfet and its making method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920014436A KR950011022B1 (en) 1992-08-11 1992-08-11 Mosfet and its making method

Publications (2)

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KR940004852A true KR940004852A (en) 1994-03-16
KR950011022B1 KR950011022B1 (en) 1995-09-27

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KR1019920014436A KR950011022B1 (en) 1992-08-11 1992-08-11 Mosfet and its making method

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337613B1 (en) * 1994-12-29 2002-11-23 주식회사 엘지씨아이 Process for producing gloss-controlling resin
KR100385721B1 (en) * 2000-02-16 2003-05-27 주식회사 엘지화학 Non-glossy thermoplastic resin having heat resistance and method for preparing the same
KR100382390B1 (en) * 1997-11-26 2003-07-18 제일모직주식회사 Thermoplastic resin composition with excellent appearance and impact resistance
KR100398737B1 (en) * 1998-02-05 2003-12-31 주식회사 엘지화학 Preparation method of vinyl chloride-based resin with excellent impact resistance
KR100552379B1 (en) * 1999-02-04 2006-02-20 제일모직주식회사 Styrenic resin composition for fatigue strength
KR100594218B1 (en) * 2000-05-30 2006-07-03 삼성전자주식회사 A method for forming vertical channel of MOS transistor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100337613B1 (en) * 1994-12-29 2002-11-23 주식회사 엘지씨아이 Process for producing gloss-controlling resin
KR100382390B1 (en) * 1997-11-26 2003-07-18 제일모직주식회사 Thermoplastic resin composition with excellent appearance and impact resistance
KR100398737B1 (en) * 1998-02-05 2003-12-31 주식회사 엘지화학 Preparation method of vinyl chloride-based resin with excellent impact resistance
KR100552379B1 (en) * 1999-02-04 2006-02-20 제일모직주식회사 Styrenic resin composition for fatigue strength
KR100385721B1 (en) * 2000-02-16 2003-05-27 주식회사 엘지화학 Non-glossy thermoplastic resin having heat resistance and method for preparing the same
KR100594218B1 (en) * 2000-05-30 2006-07-03 삼성전자주식회사 A method for forming vertical channel of MOS transistor

Also Published As

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KR950011022B1 (en) 1995-09-27

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