KR0172814B1 - Method of fabricating soi using silicon growth - Google Patents
Method of fabricating soi using silicon growth Download PDFInfo
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- KR0172814B1 KR0172814B1 KR1019910002366A KR910002366A KR0172814B1 KR 0172814 B1 KR0172814 B1 KR 0172814B1 KR 1019910002366 A KR1019910002366 A KR 1019910002366A KR 910002366 A KR910002366 A KR 910002366A KR 0172814 B1 KR0172814 B1 KR 0172814B1
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- South Korea
- Prior art keywords
- soi
- manufacturing
- silicon
- terminals
- forming
- Prior art date
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 24
- 239000010703 silicon Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 9
- 239000012212 insulator Substances 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 235000014653 Carica parviflora Nutrition 0.000 description 1
- 241000243321 Cnidaria Species 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명의 반도체인 SOI공정에 관한 것으로, 특히 메모리 셀의 모스트랜지스터 구조와 비슷하면서 SOI의 특성에 적당하도록 실리콘 성장을 이용한 SOI의 제조방법에 관한 것이다.The present invention relates to an SOI process, which is a semiconductor of the present invention, and more particularly, to a method of manufacturing an SOI using silicon growth similar to a morph transistor structure of a memory cell and suitable for SOI characteristics.
종래의 SOI구조는 절연체 기판위에 실리콘을 증착시키고, 모스 트랜지스터 구조를 갖도록 하였다.The conventional SOI structure deposits silicon on an insulator substrate and has a MOS transistor structure.
따라서 절연체 기판에는 단자를 갖지 않고 단지 드레인, 게이트, 소오스의 3단자만으로 구성되어 있으므로, 단결정 형성이 잘 되지 않아서 특성이 좋지 않고, 3단자이므로 벌크의 영향을 고려할 수 없는 단점이 있다.Therefore, since the insulator substrate has no terminals and is composed of only three terminals of drain, gate, and source, single crystals are not well formed, so characteristics are not good, and three terminals have disadvantages in that bulk effects cannot be considered.
이에 따라 본 발명은 상기한 단점을 해결하기 위한 새로운 구조의 SOI제조방법으로서 일반적인 모스 트랜지스터 구조와 비슷하며 채널 밑에 산화막을 형성하고, 상기 산화막 상부를 덮도록 실리콘 에피텍셜층을 형성시킨 후 각각의 모스단자를 형성하기 위해 이온을 주입하여 소오스와 드레인 및 게이트를 만들어 주므로써 벌크단자를 포함한 4단자를 갖는 모스 구조와 같다.Accordingly, the present invention is a method of manufacturing a SOI of a new structure to solve the above disadvantages, similar to the general MOS transistor structure, forming an oxide film under the channel, and after forming a silicon epitaxial layer to cover the oxide film, each MOS Ions are implanted to form terminals to form sources, drains and gates.
이와 같은 본 발명은 일반적인 모스 제조방법에 의하여 SOI공정이 쉽고, 또한 SOI이면서 일반적인 모스특성을 갖고 있으며 벌크단을 형성하여 전압(Vt)을 조절할 수 있는 실리콘 성장을 이용한 SOI의 제조방법에 관한 것이다.As described above, the present invention relates to a method of manufacturing SOI using silicon growth, in which an SOI process is easy by a general Mohs manufacturing method, and also has SOS and general Mohs characteristics, thereby forming a bulk stage to control voltage (Vt).
Description
제1도는 종래 SOI의 구성도.1 is a block diagram of a conventional SOI.
제2도는 제1도에 있어서 프로세스 공정도.2 is a process flow diagram in FIG.
제3도는 본 발명의 실리콘 성장을 이용한 SOI의 구성도.3 is a schematic diagram of SOI utilizing silicon growth of the present invention.
제4도는 제3도에 있어서 프로세스 공정도.4 is a process flow diagram in FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2, 4, 12, 15 : 산화막1: silicon substrate 2, 4, 12, 15: oxide film
3, 14 : 포토레지스트 5, 16 : 폴리실리콘층3, 14 photoresist 5, 16 polysilicon layer
6, 17 : 콘택 7, 18 : 알루미늄6, 17: contact 7, 18: aluminum
13 : 실리콘에피택셜층13: silicon epitaxial layer
본 발명은 반도체의 SOI(Silicon On Insulator) 공정에 관한 것으로, 특히 메모리 셀의 모스(MOS) 트랜지스터 구조와 비슷하면서 SOI의 특성에 적당하도록 실리콘 성장을 이용한 SOI의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon on insulator (SOI) process of a semiconductor, and more particularly, to a method of manufacturing an SOI using silicon growth similar to that of a MOS transistor of a memory cell and suitable for SOI characteristics.
종래의 SOI구조는 제1도에 도시된 바와 같이 절연체 기판 위에 실리콘(Silicon)을 증착시키고 상기 실리콘에는 모스트랜지스터 구조를 갖도록 하였다.In the conventional SOI structure, silicon is deposited on an insulator substrate as shown in FIG. 1, and the silicon has a MOS transistor structure.
또한 종래 SOI의 절연체 기판에는 단자를 갖지 않고 단지 드레인(Drain), 게이트(Gate), 소오스(Source)의 3단자만으로 구성되어 있다.In addition, the insulator substrate of the conventional SOI does not have a terminal and is composed of only three terminals of a drain, a gate, and a source.
따라서 상기한 종래의 SOI의 제조방법은 제2도 (a)~(c)에 도시된 바와 같이 절연체 기판(1) 위에 실리콘(2)을 증착시킨 후 포토레지스터(3)를 패턴(Pattern)하여 드레인(D)과 소오스(S) 이온을 주입한다.Therefore, in the conventional SOI manufacturing method, as shown in FIGS. 2A to 2C, after the silicon 2 is deposited on the insulator substrate 1, the photoresist 3 is patterned. Drain (D) and source (S) ions are implanted.
상기 공정후 제2도 (d)~(e)에 도시된 바와 같이 선택적 산화에 의해 게이트 산호막(4)을 형성하고 폴리 실리콘층(5)을 증착시킨 후 콘택(Contact)(6)을 형성하여 콘택홈을 뚫고 알루미늄(Al)(7)금속을 증착시킨다.After the process, the gate coral film 4 is formed by selective oxidation, the polysilicon layer 5 is deposited, and the contact 6 is formed as shown in FIGS. Through the contact grooves to deposit aluminum (Al) (7) metal.
이와 같이 종래의 SOI제조방법은 절연체 기판위에 실리콘을 성장시키므로 단결정 형성이 잘 되지 않아서 특성이 좋지 않고, 3단자이므로 벌크(Bulk)의 영향을 고려할 수 없는 단점이 있다.As described above, the conventional SOI manufacturing method grows silicon on an insulator substrate, so that single crystals are not well formed, so characteristics thereof are not good, and since three terminals are used, the effect of bulk cannot be considered.
이에 따라 본 발명의 상기한 단점을 해결하기 위한 새로운 구조의 SOI제조방법으로써, 우선 제3도에 도시된 바와 같이 일반적인 모스(MOS) 구조와 비슷하며 채널(Channel)밑에 산화막(12)을 형성하고, 상기 산화막(12) 상부를 덮도록 실리콘 에피텍셜(siliconEpitaxal)층(13)을 형성한 후 각각의 모스 단자를 형성하기 위해 이온을 주입하여 소오스(S)와 드레인(D) 및 게이트(G)를 만들어 주므로서 벌크단자를 포함한 4단자를 갖는 모스 구조와 같다.Accordingly, as a method of manufacturing a SOI having a new structure to solve the above disadvantages of the present invention, first, the oxide film 12 is formed under a channel, similar to a general MOS structure, as shown in FIG. After forming the silicon epitaxial layer 13 to cover the oxide layer 12, ions are implanted to form respective MOS terminals, so that the source S, the drain D, and the gate G are formed. It is like a Morse structure having 4 terminals including bulk terminals by making.
이하, 상기한 본 발명의 실리콘 성장을 이용한 SOI의 제조방법은 제4도 (a)~(c)에 도시된 바와 같이 P형 실리콘 기판(11)위에 선택적 산화에 의해 산화막(12)을 형성시킨 후 산화막(12) 양측의 실리콘기판(11)을 에피성 장점으로 하여 상기 산화막(12) 상부를 덮을 때까지 시간을 조절을 통하여 실리콘 에피텍셜층(13)을 성장시킨다.Hereinafter, in the method of manufacturing SOI using the silicon growth of the present invention, the oxide film 12 is formed by selective oxidation on the P-type silicon substrate 11 as shown in FIGS. 4A to 4C. Afterwards, the silicon epitaxial layer 13 is grown by controlling the time until the silicon substrate 11 on both sides of the oxide film 12 is covered with an epitaxial advantage until the top surface of the oxide film 12 is covered.
상기 공정후 제4도 (d)~(e)에 도시된 바와 같이 채널 이온 주입을 실시하며 포토레지스터(Photo Resist)(14)를 패턴하여 소오스(S) 및 드레인(D)을 형성하기 위해 N+이온을 주입한다.After the process, as shown in FIGS. 4 (d) to (e), N + is implanted to form a source (S) and a drain (D) by patterning the photoresist (14). Implant ions.
또한, 상기 공정후 제4도 (f)~(g)에 도시된 바와 같이 선택적 산화에 의해 게이트 산화막(15)과 폴리실리콘층(16)을 형성한 후 폴리실리콘층(16)과 소오스 및 드레인 영역상에 콘택(Contact)(17)을 형성하여 상기 콘택을 통하여 폴리실리콘층(16)과 소오스(S) 및 드레인(D)에 각각 콘택되도록 알루미늄(Al)(18) 배선을 형성시킨다.In addition, after the process, as shown in FIGS. 4 (f) to (g), the gate oxide film 15 and the polysilicon layer 16 are formed by selective oxidation, and then the polysilicon layer 16, the source and the drain are formed. A contact 17 is formed on the region to form the aluminum (Al) 18 wiring so as to contact the polysilicon layer 16, the source S, and the drain D, respectively, through the contact.
이와 같이 본 발명의 실리콘 성장을 이용한 SOI의 제조방법은 일반적인 모스제조방법에 의하여 SOI고정이 쉽고, 또한 SOI이면서 일반적인 모스 특성을 갖고 있으며 벌크단에 의하여 전압(Vt)을 조절할 수 있는 효과가 있다.As described above, the method for manufacturing SOI using silicon growth of the present invention is easy to fix SOI by a general Mohs manufacturing method, and also has SOI and general Mohs characteristics, and has the effect of adjusting the voltage Vt by the bulk stage.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910002366A KR0172814B1 (en) | 1991-02-12 | 1991-02-12 | Method of fabricating soi using silicon growth |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910002366A KR0172814B1 (en) | 1991-02-12 | 1991-02-12 | Method of fabricating soi using silicon growth |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920017215A KR920017215A (en) | 1992-09-26 |
| KR0172814B1 true KR0172814B1 (en) | 1999-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910002366A KR0172814B1 (en) | 1991-02-12 | 1991-02-12 | Method of fabricating soi using silicon growth |
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| Country | Link |
|---|---|
| KR (1) | KR0172814B1 (en) |
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1991
- 1991-02-12 KR KR1019910002366A patent/KR0172814B1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR920017215A (en) | 1992-09-26 |
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