JPS62244163A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device adapted for a high density by composing a field plate separating portion of a thin insulating film of the same degree as a gate insulating film, a silicon nitride film and an N-type polycrystalline silicon as a field plate electrode to form an active region and a field region in a self-aligning manner. CONSTITUTION:In a MIS field effect semiconductor integrated circuit formed on a semiconductor substrate 1 of one conductivity type, a channel stopper P<+> type diffused layer 4 is provided to separate the elements of at least N- channel element region, an entire element separating region is formed in contact with an active region, the configuration is formed of an insulating film of the thickness of the same degree as a gate insulating film 8, a silicon nitride film 5 and N-type polycrystalline silicons 6, 6', and an element separating method in which the silicons 6, 6' are the same potential as the semiconductor surface directly thereunder is used. For example, after the N-type polycrystalline silicon formed on the film 5 is selectively etched, it is thermally oxidized, a thick silicon oxide film 7 is grown on the silicons 6, 6' by thermal oxidizing, and then the film 5 of the portion to become an active region and a thin silicon oxide film 2 of the lower layer is removed by etching.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a field effect semiconductor integrated circuit device, and in particular, an insulating film as thin as a gate insulating film and a field electrode having the same potential as a substrate are used to reduce the distance between elements. This invention relates to an improved structure of so-called field plate separation for performing separation and a method of manufacturing the same.

[Conventional technology]

Element isolation in field effect semiconductor integrated circuit devices includes selective oxidation isolation shown in FIG. 5 and field plate isolation shown in FIG. 6. Current isolation methods used in integrated circuit devices often use selective oxidation isolation in which the active region and field region are formed in self-alignment.The latter type of field plate isolation is not self-aligned, and Due to the difficulty of the method, it has never been put into practical use.

[Problem that the invention seeks to solve]

Traditional field plate isolation methods
S) Because transistors, diffusion layers, etc.) and regions other than the active region (hereinafter referred to as field regions) are not formed in self-alignment, the field region and active region are processed using different mask patterns, so that they do not overlap with each other. , it is necessary to provide an alignment margin of about 1 to 2 μm, which is an obstacle to increasing the density of large-scale integrated circuits.

Furthermore, in order to reduce the capacitance between the field plate conductor and the respective wiring conductors provided on its sides and top, it is necessary to cover the field plate surface with an insulating film of an appropriate thickness, but the manufacturing process is difficult. Moreover, a similarly thick insulating film will grow in the above-mentioned alignment margin area. This thick insulating film has radiation resistance due to the generation of interface states at the insulating film-substrate interface and the generation of many electron-hole pairs in the insulating film.
This has the disadvantage of increasing inter-board leakage current. In addition, in order to prevent source-drain channel leakage current, it is necessary to overlap the gate electrode with the field region, but the capacitance with the substrate increases by the amount of overlap, which reduces the operating speed of the circuit, etc. There are many drawbacks.

[Means for solving problems]

The configuration of the field plate separation portion of the present invention is based on the MI
It consists of an insulating film as thin as the gate insulating film which is a component of an S-type field effect transistor, a silicon nitride film, and an N-type polycrystalline silicon as a field plate electrode. Further, the field region including the N-channel MIS transistor is provided with a P-type diffusion layer for a channel stopper in order to increase the threshold voltage of the parasitic MIS transistor.

The method of forming the field plate isolation of the present invention in self-alignment with the active region is as follows.

That is, after selectively etching the N-type polycrystalline silicon formed on the silicon nitride film, thermal oxidation is performed to grow a thick silicon oxide film on the surface of the polycrystalline silicon, and then the active region is etched. The silicon nitride film and the thin silicon oxide film underlying it are removed by etching. Thereafter, according to the conventional technique, a gate insulating film is grown by thermal oxidation to form a gate electrode, and then a diffusion layer such as a source/drain is formed in self-alignment with the gate electrode to form an integrated circuit device of the present invention. is formed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

From FIG. 1, the fourth circuit is a step-by-step cross-sectional view of forming a complementary MO8 integrated circuit using the field plate isolation of the present invention.

First, in Figure 1, 500A is applied to the surface of a P-type silicon substrate l.
A silicon oxide film 2 of about 100 mL is grown by thermal oxidation, and then ion implantation of phosphorus as an N-type impurity is performed in the region where a P-channel MOS transistor is to be formed, using a 7 photoresist as a mask to form an N-well 3. Furthermore, N channel MO8)
A Pfi impurity for a channel stopper, such as boron, is similarly formed by ion implantation in the field region 4 in the region where the transistor is to be formed. In FIG. 2, a silicon nitride film 5 of about 500 A is grown on the entire surface by vapor phase growth.
Furthermore, after selectively forming N-type polycrystalline silicon 6.6' with a thickness of about 1 μm, thermal oxidation is performed to the extent that a silicon oxide film 7 of about 1 μm is grown on the surface of polycrystalline silicon 6.6′. . At the time of heating, the exposed silicon nitride film 5 has
Only a silicon oxide film with a height of about 100A grows. Next, in FIG. 3, after etching the exposed silicon nitride film 5 and the underlying silicon oxide film 2 using the silicon oxide film 7 as a mask, a silicon oxide film 8 of about 300A is grown by thermal oxidation. is the gate oxide film. After the gate oxide film is grown, ion implantation for controlling the threshold voltage of P-channel and N-channel transistors is performed as necessary, and then N-type polycrystalline silicon 9 is selectively formed as a gate electrode and a wiring conductor. Furthermore, arsenic ions were implanted as the source and drain 10 of the N-channel transistor region and the diffusion JmlO' for taking out the N-well potential.
Boron ions are implanted using aluminum as a mask to form the source and drain 11 of the P-channel transistor region and the diffusion layer 11' for taking out the potential of the P-type silicon substrate. Fourth
In the figure, a PSG film 1 formed by vapor phase growth is used as an interlayer insulating film.
After depositing aluminum 13 with a thickness of about 1 μm, a contact hole is opened, and then aluminum 13 with a thickness of about 1/a is deposited as a wiring conductor.
．． 13' and 13'' are selectively attached, so that the aluminum 13' and the P-type substrate 1 and the shield plate 6 are at the same potential.Also, the aluminum 131 makes the shield plate 13' and the N-well 3 have the same potential,
Insulation by the parasitic MOS transistors between the N-channel transistors and between the P-channel transistors is ensured.

〔Effect of the invention〕

As explained above, the field plate isolation method of the present invention allows the active region and the field region to be formed in self-alignment, so that the element spacing can be reduced, and is a technique suitable for large-scale integrated circuits due to high density.

Because the field region and active region are formed in self-alignment,
The alignment margin between the field region and the active region, which was a problem with the conventional field/plate separation method, is no longer required, and the degradation of radiation resistance and increase in gate-to-substrate capacitance caused by the alignment margin can be ignored. Become.

Furthermore, according to the present invention, when miniaturization is advanced by selective oxidation separation, the thinning of the active region due to bird's beak, which is a problem, is eliminated, and an active region with the same shape as the mask pattern can be realized, making the device suitable for miniaturization. It is a separation method.

[Brief explanation of drawings]

1 to 4 are cross-sectional views showing each manufacturing process of a complementary field effect semiconductor integrated circuit using field plate separation using self-alignment according to the present invention. Further, FIGS. 5 and 6 are cross-sectional views of the same integrated circuit using conventional element isolation, in comparison with FIG. 3, and show cases of selective isolation and non-self-aligned field plate isolation, respectively. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Silicon nitride R film, 3... N Fell region, 4...
...P-type diffusion layer for N channel, channel stopper, 5...Silicon nitride [j4,6.6'・-
...N+ type polycrystalline silicon for field plate, 7...Silicon oxide film, 8...Gate isolation &
t Silicon oxide film as Ha, 9...N-type polycrystalline silicon for gate electrode, 10.10'...
...N diffusion layer, 11.11'...P diffusion layer, 12...PSG film, 13.13', 13"
...Aluminum wiring. Agent Patent Attorney Uchihara 1 Shiro 1 ・ Houki , 5''' Diagram? Kishi Otsu p4

Claims (1)

[Claims] In a MIS type field effect semiconductor integrated circuit formed on a semiconductor substrate of one conductivity type, at least a P^+ diffusion layer for a channel stopper is provided in the device isolation of the N-channel type device region, and a P^+ diffusion layer is provided for the device isolation in the entire device isolation region. is formed in contact with the active region, and consists of an insulating film with a thickness similar to that of the gate insulating film, a silicon nitride film, and N-type polycrystalline silicon, and the N-type polycrystalline silicon is in contact with the semiconductor directly below. A semiconductor device using an element isolation method that is characterized by having the same potential as the surface.