JPH0471236A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To restrain the area of a source drain diffusion layer to minimum, by opening a contact hole to be made for the source drain of an MOS transistor, for high melting point metal led-out on a field oxide film from the source drain. CONSTITUTION:After a field oxide film 2 and a gate oxide film 3 are formed on a substrate 1, impurities of a conductivity type opposite to the substrate are implanted by using a gate electrode 4 formed on the film 3 as a mask, and a low temperature diffusion layer 6 is formed. A second oxide film 7 grown on the substrate is etched back, the substrate surface us exposed, and at the same time, the oxide film 7 is left only on the electrode side wall part. By using this as a mask, impurities of a conductivity type opposite to the substrate are ion-implanted, and a high concentration diffusion layer 8 is formed. A thin polycrystalline silicon layer 9 is grown, imputities are thermally diffused, and anisotropic etching is performed by using photo resist 11 as a mask. High melting point metal 12 is grown on the exposed diffusion layer 8. After an interlayer insulating film 13 is grown, a contact hole is opened on the metal 12, and silicide 14 is buried, thereon a metal wiring 15 is formed, and electric connection is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a source/drain diffusion layer of an MO8 type semiconductor device and its lead wiring.

[Conventional technology]

A method of forming a connection between a source/drain diffusion layer and an upper metal latitude line of a conventional MO8 type semiconductor device will be described with reference to the drawings.

FIGS. 5(a) to 5(e) are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. FIG. 6 is a plan view of a semiconductor device manufactured by the manufacturing method shown in FIG.
Figure (e) is a sectional view taken along the line DD' in Figure 6.

The steps will be explained below in order.

As shown in FIG. 5(a), after forming a field oxide film 2 and a gate oxide film 3 on a semiconductor substrate 1, approximately 2000
Growing polycrystalline silicon with a thickness of about 1000 nm, then growing a first oxide film 5 with a thickness of about 1000 nm, and simultaneously patterning the polycrystalline silicon and the first oxide film 5 into a predetermined pattern, The gate t[+
Using 4 as a mask, a first impurity of a conductivity type opposite to that of the semiconductor substrate (for example, phosphorus in the case of a P-type substrate) is ion-implanted, and 1
A low concentration diffusion layer 6 of approximately 01018a' to 1019CXI-' is formed.

As shown in FIG. 5(b), a second oxide film 7 of 2,000 to 3,000 layers is grown on the semiconductor substrate by the CVD method.

As shown in FIG. 5(C), the second oxide WA 7 is etched back by anisotropic etching to expose the surface of the semiconductor substrate, and at the same time a second oxide film 7 is formed only on the side walls of the gate electrode 4. Using the remaining 0th order gate $41!4 and second oxidized WA7 as a mask, a second impurity of a conductivity type opposite to that of the semiconductor substrate (for example, arsenic in the case of a P-type substrate) is ion-implanted, and 1020 to 11021a''- A high concentration diffusion 18 of about 3 is formed.

Next, a titanium layer 16 of approximately 1000 layers is formed on the surface of the semiconductor substrate.

As shown in FIG. 5(d), a titanium silicide layer 17 is formed on the exposed surface of the semiconductor substrate by heat treatment. Unreacted titanium is removed by etching with hydrogen peroxide solution.

As shown in FIG.
After embedding 4, metal wiring 15 is formed on top of it,
Electrical connection is made between titanium silicide layer 17 and metal wiring 15.

FIG. 5 (1B) is a sectional view of the final process when manufactured by the conventional manufacturing method.

[Sequence of problems to be solved by the invention]

In this conventional manufacturing method, the contact hole must necessarily be formed on the titanium silicide layer formed on the high concentration spreading layer. Therefore, the area of the diffusion layer becomes a size including the size of the contact hole and the alignment margin between the end of the contact hole, the end of the gate electrode, and the field width (diffusion layer #A).

Therefore, there is a problem that the junction capacitance between the semiconductor substrate and the diffusion layer increases. This junction capacitance is important when achieving a short gate length that improves the current drive capability of a transistor.
This increases if the impurity concentration of the semiconductor substrate is increased to prevent punch-through between the source and drain.

Therefore, there is a problem in that even if the gate length of the MOS transistor is reduced, an integrated circuit device that operates at high speed cannot be manufactured. Furthermore, since the contact hole is formed on the titanium silicide on the heavily doped diffusion layer, the above-mentioned area is required, and there is a problem in that high-density MOS transistors cannot be arranged.

An object of the present invention is to provide a method for manufacturing a semiconductor device that significantly reduces the junction capacitance between a semiconductor substrate and a drain diffusion layer and enables high-speed operation of an integrated circuit device.

[Means to solve the problem]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a gate oxide film forming step, a gate electrode and oxide film forming step, a low concentration impurity diffusion layer forming step, a substrate surface exposing step, A method for manufacturing a semiconductor device comprising a high concentration diffusion layer formation process, an impurity diffusion process, a patterning process, a growth process, and a wiring process, wherein the gate oxide film formation process is performed on a semiconductor substrate having one conductivity type. A field region and an active region are formed on the active region, and a gate oxide film is formed on the active region. In the gate electrode and oxide film forming process, the gate electrode and the same pattern as the gate electrode are formed on the gate oxide film in a predetermined pattern. In the step of forming a low concentration impurity diffusion layer, a first impurity of a conductivity type opposite to that of the semiconductor substrate is ionized into the semiconductor substrate in a self-aligned manner using the gate electrode as a mask. In the substrate surface exposure step, a second oxide film is grown on the semiconductor substrate, and anisotropic etching is performed to form a low concentration impurity diffusion layer.
The second oxide film is left only on the i-side wall portion, and at the same time, the surface of the semiconductor substrate other than the gate electrode and field region is exposed. The impurity is ion-implanted into the semiconductor substrate in a self-aligned manner using the gate electrode and the second oxide film on the sidewalls as a mask to form a highly concentrated impurity diffusion layer. After growing the polycrystalline silicon layer, heat treatment is performed to diffuse the second impurity from the high concentration conversion layer into the polycrystalline silicon layer connected to the high concentration diffusion layer, and the patterning step is performed using a predetermined method. patterning the polycrystalline silicon layer in a shape,
In the growth process, a high melting point metal is selectively grown by CVD on a polycrystalline silicon layer patterned into a predetermined shape and on a high concentration diffusion layer exposed by removing the polycrystalline silicon layer. In the wiring step, an interlayer insulating film is grown, a contact hole is formed in the interlayer insulating film on the high melting point metal, and electrical connection is made to the upper metal wiring.

Further, the present invention includes a doping step, in which the second oxide film is etched by anisotropic etching to expose the surface of the semiconductor substrate, and then the second oxide film is etched by anisotropic etching.
A thin polycrystalline silicon layer is grown, and then a second impurity of a conductivity type opposite to that of the semiconductor substrate is ion-implanted through the polycrystalline silicon to form a highly concentrated diffusion layer, and at the same time the second impurity is implanted into the polycrystalline silicon. It is a doping method.

[Effect]

Contact holes to be opened to the source and drain of the MOS transistor are opened to the high melting point metal drawn out from the source train onto the field oxide film. This makes it possible to minimize the area of the source/drain diffusion layer as much as possible.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(Example 1) FIGS. 1(a) to 1(f) are cross-sectional views showing the method of manufacturing a semiconductor device of the present invention in order of steps. FIG. 2 is a plan view of a semiconductor device manufactured by the manufacturing method shown in FIG. 1, and FIG. 1(f) is a sectional view taken along line A-A' in FIG.

The steps will be explained below in order.

As shown in FIG. 1(a), after forming a field oxide film 2 and a gate oxide film 1!13 on a semiconductor substrate 1, approximately 2
Grow polycrystalline silicon to a thickness of about 100 µm, then about 100 µm thick.
simultaneously patterning the first oxide film 5 with a thickness of 0.
Forming the gate electrode 4 Next, using the gate electrode 4 as a mask, a first impurity of the conductivity type opposite to that of the semiconductor substrate (for example, phosphorus in the case of a P-type substrate) is implanted.
A low concentration diffusion layer 6 of approximately "cs-3 to 10">-' is formed.

As shown in FIG. 1(b), a second oxide film 7 of 2,000 to 3,000 layers is grown on the semiconductor substrate by the CVD method.

As shown in FIG. 1(C), the second oxidized WA 7 is etched by anisotropic etching to expose the surface of the semiconductor substrate and at the same time remove the gate electrode. The second oxidation film 7 is left only on the sidewalls. At this time, the surface of the gate electrode 4 is not exposed because the first oxide film 5 is present on the gate electrode 4.

Next, using the gate electrode 4 and the second oxidized WA 7 as masks, a second impurity of a conductivity type opposite to that of the semiconductor substrate (for example, As in the case of a P-type substrate) is ion-implanted.
A high concentration diffusion layer 8 of about 4 in Japan is formed.

Next, a thin polycrystalline silicon layer (e.g. 200-500 people)
Grow 9.

As shown in Fig. 1 16), heat treatment (e.g. 900°C
(for about 20 minutes) to diffuse the second impurity into the polycrystalline silicon layer connected to the high concentration diffusion layer.

Next, photoresist 11 is applied to polycrystalline silicon in a predetermined shape.
At this time, since the polycrystalline silicon layer 9 is thin, the amount of overetching during etching can be kept small, and in the area where the photoresist 11 is not present, the highly concentrated diffusion layer is is not etched to a large extent.

The thin silicon layer 9 can be patterned arbitrarily on the field and on the gate electrode.

As shown in FIG. 1(e), a thin polycrystalline silicon layer 9 formed by CVD, a polycrystalline silicon layer 10 in an impurity-doped region, and an exposed high concentration impurity diffusion layer 8 are shown.
Approximately 1000 to 1500 refractory metals (eg, tungsten) 12 are selectively grown on top.

At this time, the layer resistance of the high melting point metal layer is 1Ω/mouth or less.

As shown in FIG. 1Tf), the interlayer insulation 11A13 is
A contact hole is formed on the high melting point metal 12, and then tungsten or tungsten silicide 14 is buried, and then a metal is placed on top of it! 115 is formed to electrically connect the high melting point metal 12 and the metal wiring 15.

FIG. 1(f) is a sectional view of the final process when manufactured by the manufacturing method of the present invention.

(Example 2) Example 2 of the present invention will be described below.

In the method for manufacturing a semiconductor device of the present invention, FIG.
In the process, the second oxide film 7 is etched back, leaving the second oxide W:47 only on the regular walls of the gate electrode 4 and exposing the surface of the semiconductor substrate, and then a thin polycrystalline silicon layer (
For example, 200 to 500 people) 9 is grown, and a second impurity of a conductivity type opposite to that of the semiconductor substrate (for example, arsenic in the case of a P type substrate) is ion-implanted through the polycrystalline silicon layer 9.

Next, by performing a heat treatment (for example, about 900 DEG C. Cl2O), the same structure as in FIG. 1+d) can be obtained.

The following manufacturing method is the same as that described in Example 1.

(Example 3) An application example of the manufacturing method of the present invention will be described below with reference to the drawings.

Figure 3 (a), (b) and Figure 4 (a), (b)
) by the production method of the present invention. ! A plan view and a cross-sectional view of the semiconductor device that was left behind are shown.

In Figures 3(a) and 3(b), two MOS transistors are placed close together, the drains and sources of different transistors are close together, and contact holes are opened for each source train. The case where holes are made is shown below.

By the manufacturing method of the present invention, the polycrystalline silicon layer 9 is patterned over a part of the gate electrode, a high melting point metal 12 is grown on top of the polycrystalline silicon layer 9, and a contact hole is formed in the high melting point metal, Electrical connection is obtained with the upper metal wiring. In this case, the contact hole is opened through the oxide film to the high melting point metal existing at the top of the gate "Ijh".

FIGS. 4(a) and 4(b) show a case where two MOS transistors are arranged at a certain distance from each other, and the diffusion layers arranged facing each other are both sources.

According to the manufacturing method of the present invention, the polycrystalline silicon layer 9 is patterned to include the sources of two MOS transistors facing each other, a high melting point metal 12 is grown on top of the polycrystalline silicon layer 9, and a contact hole is opened in the high melting point metal. A hole is made to obtain electrical connection with the metal wiring on the top. The contact hole in this case is opened to the high melting point metal 12 on the field oxide ridge.

Further, the transistor Tr2 in FIG. Most of the area of the contact holes connected to the drains of the transistors Trl and Tr2 in FIG. 4 is a high melting point metal region drawn out onto the field, and the area of the drain diffusion layer is kept small.

〔Effect of the invention〕

As explained above, in the manufacturing method of the present invention, the contact holes for the source and drain of the MOS transistor are opened for the refractory metal drawn from the source train onto the field oxide film. The area of the source/drain diffusion layer can be minimized. Therefore, the junction capacitance between the semiconductor substrate and the drain diffusion layer can be significantly reduced, and the integrated circuit device can operate at high speed.

In addition, the high melting point metal drawn from the source train can be formed up to the top of the gate electrode via the oxide film, and the contact hole is formed on the high melting point metal in that area, so it is necessary to form the contact hole. There is no need to provide a large area on the diffusion layer, and the area of the transistor can be reduced. Therefore, there is an effect that the degree of integration of the integrated circuit device can be improved.

Furthermore, since the thin polycrystalline silicon can be patterned arbitrarily, separate diffusion layers can be connected with a high melting point metal via the thin polycrystalline silicon, making it possible to arrange elements at a higher density.

[Brief explanation of the drawing]

1(a) to 1(f) are cross-sectional views showing embodiments of the present invention in the order of steps, FIG. 2 is a plan view explaining the present invention in detail, and FIG. ) is a plan view for explaining the arrangement of a MOS transistor to which the present invention is applied, and FIG.
) is a sectional view taken along the line B-B' in FIG. 3(a), FIG. 4(b) is a sectional view taken along the line c-c' in FIG. 4(a), and FIGS.
) is a sectional view showing the conventional manufacturing method in the order of steps, and FIG. 6 is a plan view for explaining the conventional manufacturing method. 1.Paper.Semiconductor substrate 2...Field oxide film 3...Gate oxide film 4...Gate electrode 5...
- First oxide film 6...Low concentration impurity diffusion layer 7...Second oxide film 8...High concentration impurity diffusion layer 9...Polycrystalline silicon layer 10...Polycrystalline silicon layer 10... Crystalline silicon layer 11...
・Photoresist 12...High melting point metal 13...
Interlayer insulating film 14...tungsten or tungsten silicide 1
5...Metal wiring 16...Titanium 17...
・Titanium silicide patent applicant NEC Corporation Figure 3 (f) Figure 3 (cl) Figure (, f) Figure (b) (C) Figure 5

Claims (2)

[Claims] (1) Gate oxide film formation process, gate electrode and oxide film formation process, low concentration impurity diffusion layer formation process, substrate surface exposure process, high concentration diffusion layer formation process, impurity diffusion process, patterning process , a method for manufacturing a semiconductor device comprising a growth step and a wiring step, the gate oxide film forming step forming a field region and an active region on a semiconductor substrate having one conductivity type, and forming a gate oxide film on the active region. The gate electrode and oxide film forming process is to form a gate electrode and a first oxide film with the same pattern as the gate electrode in a predetermined pattern on the gate oxide film, and to form a first oxide film with a low concentration impurity. In the diffusion layer forming step, a first impurity of a conductivity type opposite to that of the semiconductor substrate is ion-implanted into the semiconductor substrate in a self-aligned manner using the gate electrode as a mask to form a low concentration impurity diffusion layer, In the substrate surface exposure step, a second oxide film is grown on the semiconductor substrate, and by anisotropic etching, the second oxide film is left only on the side walls of the gate electrode, and at the same time, the second oxide film is left on the side walls of the gate electrode and other areas other than the gate electrode and the field area. The high-concentration impurity diffusion layer forming step involves self-aligning a second impurity having a conductivity type opposite to that of the semiconductor substrate using the gate electrode and the second oxide film on the sidewalls as a mask. In this process, ions are implanted into the semiconductor substrate to form a highly concentrated impurity diffusion layer.The impurity diffusion process involves growing a thin polycrystalline silicon layer and then heat-treating it to connect it to the highly concentrated diffusion layer. A second impurity is diffused into the polycrystalline silicon layer from a high concentration diffusion layer, the patterning step is to pattern the polycrystalline silicon layer into a predetermined shape, and the growth step is to pattern the polycrystalline silicon layer into a predetermined shape. A high melting point metal is selectively grown by CVD on a polycrystalline silicon layer patterned into a shape and on a high concentration diffusion layer exposed after the polycrystalline silicon layer is removed. A method of manufacturing a semiconductor device, comprising growing an insulating film, forming a contact hole in an interlayer insulating film on the high melting point metal, and making an electrical connection to an upper metal wiring. (2) includes a doping step, in which the second oxide film is etched by anisotropic etching to expose the semiconductor substrate surface;
A thin polycrystalline silicon layer is grown, and then a second impurity of a conductivity type opposite to that of the semiconductor substrate is ion-implanted through the polycrystalline silicon to form a highly concentrated diffusion layer, and at the same time the second impurity is implanted into the polycrystalline silicon. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method comprises doping.