JPS60113456A - Ic device - Google Patents

Abstract

PURPOSE:To prevent the leakage current of elements by a method wherein the thickness of the insulation film at the field section is set to an extremely low value, and a field electrode is provided thereon and then supplied with a fixed potential. CONSTITUTION:The thickness of the insulation film 12 of an element insulating region is formed equally to the thickness of a gate insulation film 7 of the active element or more thinly than it. contact apertures are formed above an electrode 11 and above the polycrystalline Si 5 of the element-insulating region. A metallic electrode 13 is adhered on the insulation film 12. In the operation of the elements, the electrode 13 is grounded or biased to a negative voltage, thus inhibiting the inversion of the surface of the element insulation region Si, resulting in element insulation. Then, the malfunction of the elements due to the conduction of a parasitic transistor can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION In recent years, as semiconductor integrated circuits have been incorporated into communication satellites and used in outer space, deterioration of device characteristics due to ultraviolet radiation has become a serious problem. In MO8 type integrated circuits, significant fluctuations in threshold voltage due to gamma rays are sometimes observed. This is because, among the electron-hole pairs generated in the gate oxide film by ionization, the holes move due to the electric field in the gate oxide film and are trapped at the Si Sing interface.

The variation in threshold voltage is more pronounced in the active device region (
・The absorption amount of gamma rays is about 103 to 10' Rad L (
Even in the case of As the thickness increases, the number of electron-hole pairs generated by ionization increases, and the gate capacitance also decreases as the oxide film thickness increases, so the change in threshold voltage increases rapidly as the gate film thickness increases. It's for a reason.

The present invention eliminates the above-mentioned drawbacks and provides a MO8 type collapse circuit structure in which the threshold voltage of the field portion varies extremely little even when irradiated with gamma rays.

The present invention attempts to prevent leakage current between elements by making the insulating film thickness in the field part extremely thin, about xooA or less, and providing a shield/electrode thereon to apply a constant potential. Next, one embodiment of the present invention will be described according to the drawings.

In FIG. 1, a p-type impurity layer 2 is formed on the surface of an icp-type silicon substrate 10 by ion implantation. This p
The type layer is provided for the purpose of preventing bunch-through of the MOS transistor and increasing the threshold 'magnetic pressure for field m. Next, as shown in FIG.
Then, a nitride film 4 is deposited, and polycrystalline silicon 5 is further deposited. Polycrystalline silicon 5 is doped with conductive impurities. Next, as shown in FIG. 3, the polycrystalline silicon 5 in the active element portion is removed by a photoetching process, leaving the polycrystalline silicon 5 in the inter-element insulation region. Next, heat treatment is performed in an oxidizing atmosphere to cover the surface of the polycrystalline silicon 5 with an oxide film.

Since the active element region is covered with the nitride film 4, the silicon substrate is not oxidized. Next, as shown in FIG. 4, after removing the nitride film 4 and oxide film 3 on the active element region, a new gate oxide film 7 is formed, and then polycrystalline silicon is deposited. After the gate electrode 8 is formed by a photoetching process, as shown in FIG. 5, n-type impurities are introduced by ion implantation or thermal diffusion to form the source/drain 9. Next, as shown in FIG. 6, contact openings are formed and source/drain electrodes 11 are formed by a photoetching process.

Next, as shown in FIG. 7, after depositing an interlayer insulating film, for example, an oxide film 12, contact openings are formed on the electrode 11 and on the polycrystalline silicon 5 in the interelement insulating region, and the electrode metal 13 A final lead-out electrode to the outside is formed by depositing and photo-etching. When the device is in operation, the electrode 5 is grounded or biased to a negative voltage, suppressing inversion of the silicon surface in the inter-element region and providing insulation between the devices.

In the present invention, since the inter-element insulating film is extremely thin, generation of fixed charges due to γ-ray irradiation is suppressed, and malfunction of the element due to conduction of parasitic transistors can be completely prevented.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views for explaining one embodiment of the present invention. In the figure, 1...p-type silicon substrate, 2...p-type impurity layer, 3...oxide film, 4...nitride film, 5 ...Polycrystalline silicon, 6 ... Oxide film, 7 ... Oxide film, 8 ... Polycrystalline silicon, 9 ... Nu impurity Layer, 10...
・Interlayer insulating film, 11... Electrode, 12...
-Interlayer insulating film, 13...electrode. 5-lx sa k prisoner ku ku ku ku ku ku ku n s zo

Claims (1)

[Claims] In an integrated circuit device having an insulated gate field effect transistor as a main component, the thickness of the insulating film in the inter-element insulating region is the same as or thinner than the thickness of the gate insulating film of the active element, and the insulating film in the inter-element insulating region is An integrated circuit device in which an electrode is provided on a membrane and a constant potential is applied to the electrode.