JPH0644590B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Object of the Invention) The present invention relates to a semiconductor device, and more particularly to improvement of radiation resistance of an electrically insulating separation film between semiconductor integrated circuit elements.

In recent years, there are increasing opportunities to use semiconductor integrated circuits in outer space, around nuclear reactors, and the like. A semiconductor integrated circuit placed in such a severe environment suffers various radiation damages,
Circuit malfunctions and breakdowns are likely to occur, and system functions are easily degraded. Therefore, development of a semiconductor integrated circuit resistant to radiation is desired. Radiation damage to insulated gate field effect transistors (hereinafter abbreviated as MOS transistors) and bipolar transistors, which are the basic elements of highly integrated circuits, is mainly caused by the accumulation of positive charges in the silicon oxide film and the silicon oxide-silicon interface. This is an increase in interface state density. As a result, the threshold voltage fluctuates and the leak current increases, or the current amplification factor decreases. That is, when ionizing radiation enters the silicon oxide film, a large number of electron-hole pairs are generated. After that, some of them recombine and disappear, but some of them are trapped in the silicon oxide film. Electrons have high mobility and diffuse out of the oxide film in a short time under positive gate voltage, but holes have low mobility and are trapped in the silicon oxide film to form positive fixed charges. . Further, it is said that the holes trapped at the silicon oxide film-silicon interface form an interface level. In particular, since the field oxide film, which is an electrically insulating isolation film, has a thick oxide film thickness as compared with the gate oxide film, a large amount of holes are generated, which causes a large threshold voltage change and interface state generation, which causes parasitic MOS transistor generation. And causes an increase in leakage between elements.

(Prior Art) Conventionally, (1): thinning of a field oxide film and (2): low temperature annealing have been considered in order to suppress change in value voltage and generation of interface state. However, thinning of the field oxide film surely reduces the threshold voltage and the amount of interface states generated, but on the other hand, it causes an increase in the capacitance between the wiring running on the upper surface and the substrate, thus degrading the performance of the semiconductor integrated circuit. Also, the improvement by low temperature annealing is slight.

(Structure of the Present Invention) An object of the present invention is to provide a semiconductor device having a novel field oxide film structure in order to solve the above problems. The new field oxide film has a multi-layer insulating film structure. That is, it is characterized in that a thermally oxidized silicon oxide film is first formed, and then a chemically vapor-deposited silicon oxide film (or phosphorus glass) and a silicon nitride film are alternately deposited.

(Principle of the Present Invention) Next, the principle will be described. The film thickness of the field oxide film is usually 500 mm or more, and it is difficult for most of the generated holes to diffuse outside the oxide film. Further, the closer the hole capturing position is to the silicon oxide film-silicon interface, the greater the influence on the fluctuation of the threshold voltage. Further, if holes generated inside the oxide film easily reach the vicinity of the interface, the interface state increase amount increases. Therefore, if the holes generated by the incidence of the ionizing radiation are immediately captured at that place, the change in the threshold voltage can be small. Furthermore, if the electrons generated at the same time are also captured in the vicinity of the generated position, the charges in the oxide film are offset. Further, the increase in the interface level is small because the number of holes reaching the silicon film-silicon interface decreases.

The chemical vapor deposition silyl oxide film, phosphorus glass, and silicon nitride film contain a high concentration of holes and electron traps therein. In particular, the density of holes and electron traps in the interface region between the silicon oxide film and the silicon nitride film is high. Therefore, the amount of charges in the element insulating film formed from the multilayer insulating film is very small. Further, the interface state increase amount is also greatly reduced because the amount of holes reaching the silicon oxide film-silicon interface is small. However, since the chemical vapor grown silicon oxide film or silicon nitride film has a relatively high interface state density at the initial stage, the thermal oxide film of the recon is formed first to reduce the interface density before irradiation. If this thermal oxide film is made thinner, the amount of holes generated in the thermal oxide film will decrease, so that the interface state increase amount can be significantly reduced. However, a film thickness is necessary to prevent the components of the silicon oxide film and the silicon nitride film chemically vapor-deposited by the heat treatment after the formation of the field oxide film from diffusing to the silicon oxide film-silicon interface. In any case, it is necessary to make the film thickness in consideration of the subsequent heat treatment process. This film thickness is 10
0 to 1000Å is preferable, and 100 to 500Å is more preferable.

(Examples of the Invention) Next, the present invention will be described in detail by examples. Below, P
The present invention is applied to the case where a MOS transistor is formed on a silicon substrate, but the same structure can be used for other semiconductor integrated circuits.

1 to 8 show an example of the formation of the present invention for each step.

As shown in FIG. 1, a thin oxide film 102 and a silicon nitride film 103 patterned on the surface of a P-type silicon semiconductor substrate 101 are formed by using a known photoresist and etching technique. Next, as shown in FIG. 2, using the silicon nitride film 103 as a mask, anisotropic plasma etching and wet etching are combined to selectively etch the surface of the silicon semiconductor substrate 101. At that time, the wet etching process is used for smoothing the etched surface, providing a slope on the wall, and further removing damage due to plasma etching. Although the depth of the etched groove is determined by the degree of integration of the semiconductor integrated circuit to produce a few hundred n _{m ~} several mu _m. Next, using the silicon nitride film 103 as an ion implantation mask, P-type impurities such as boron are ion-implanted 104 into the etching groove to form a channel stopper region 105.

Next, as shown in FIG. 3, the etching groove is aligned with the channel stopper region and is formed into a film having a thickness of 100 to 100 by low temperature thermal oxidation.
A 0Å silicon oxide film 106 is formed.

Further, as shown in FIG. 4, a chemically vapor-deposited silicon oxide film (or phosphorus glass) and a chemically vapor-deposited silicon nitride film are alternately deposited in the etching groove. One example thereof is the following method. That is, a silicon oxide film (or phosphorus glass) and a silicon nitride film are deposited on the entire surface of a silicon substrate by a chemical vapor deposition method at intervals of several hundred Å to several thousand Å, and then a photoresist is applied to the silicon oxide film grown by chemical vapor deposition. This is a method in which the film (or phosphorus glass) and the silicon nitride film are plasma-etched and left only in the etched groove portion. Then, the silicon nitride film 103 and the thin silicon oxide film 102 are removed by a known etching method to obtain the state shown in FIG.

FIG. 6 and subsequent steps are steps for forming an n-channel MOS transistor. That is, FIG. 6 shows that after the gate oxide film of the MOS transistor is newly formed by thermal oxidation, the gate electrode 1 is made of polysilicon containing phosphorus or refractory metal.
9 shows a state in which 09 is formed by a known etching technique. Next, as shown in FIG. 7, after the side surface of the gate electrode 109 is oxidized, the source region 111,
And the drain region 112 is formed.

Finally, as shown in FIG. 8, a protective insulating film 1 such as phosphor glass is used.
After covering the whole with 13, the source electrode 114 and the drain electrode 115 of the MOS transistor are formed, and MO
The S transistor structure is completed. Further completed MOS
The transistor will be protected by a silicon nitride film or the like.

As described above, when the present invention is applied to the MOS transistor, even if the insulating element isolation region is irradiated with the ionizing radiation, the generated electrons and holes are immediately captured without being diffused, and the charges are offset, so that the insulating film is formed. The internal charge is less likely to occur, and holes are less likely to diffuse to the silicon oxide film-silicon interface, so that the interface level does not increase. Therefore, the leak current between the adjacent MOS transistors is suppressed, and the radiation resistance is significantly improved.

[Brief description of drawings]

1 to 8 are cross-sectional views showing manufacturing steps of the embodiment of the present invention in the order of steps. 101 ... Silicon semiconductor substrate, 102 ... Thin silicon oxide film, 103 ... Masking silicon nitride film, 104
... Ions for generating channel stopper region, 1
05 ... Channel stopper region, 106 ... Silicon oxide film generated by thermal oxidation, 107 ... Insulating film in which chemical vapor deposition silicon oxide film (or phosphorus glass) and silicon nitride film are alternately layered, 108 ...... Gate oxide film, 109 ・ ・ ・ Gate electrode, 110 ・ ・ ・ Side oxide film, 111 ・ ・ ・ Source region, 112 ・ ・ ・ Drain region,
113 ... Protective insulating film, 114 ... Source electrode, 115
...... Drain electrode.

Claims (1)

[Claims] 1. A buried region of the same conductivity type as that of the semiconductor substrate, which is selectively formed on the surface of the semiconductor substrate, and an electrically insulating separation film between semiconductor elements, the heat being formed on the surface of the buried region. A silicon oxide film formed by oxidation, and a silicon oxide film formed on the surface of the silicon oxide film alternately by chemical vapor deposition or an electrically insulating separation film containing a phosphorus glass film and a silicon nitride film. Semiconductor device.