JPS60130136A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an IC element having high resistance to radiation by a method in which, before separating an MIS-type IC element, the periphery of the element is surrounded by a thick insulation film, a thin gate oxide film is provided in an element forming region, an annular shield electrode is formed on the gate oxide film, and a region having the same type of conductance with the substrate and a high impurity concentration is provided under the shield electrode through the gate oxide film. CONSTITUTION:A thin SiO2 film 33 is adhered on the surface of a P type Si substrate 31. Ions are implanted into the periphery of the substrate to form a P<+> type region 32. An Si3N4 film 35 is then provided on the film 33 such that the both ends thereof overlap with the regions 32. The substrate is heat treated to change the uppermost layer of the region 32 into a thick field SiO2 film 36, while the inner end of the region 32 is caused to penetrate in the active region. After that, the film 35 required no more is removed and the film 33 connected to the film 36 is renewed to a gate oxide film 33', on which an annular shield electrode 37 is provided and covered with an SiO2 film connected to the films 36 and 33'. A gate electrode 38 is then adhered on the electrode 37. In such a manner, an IC element resistant to ionizing radiation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an element isolation means for an MIS type semiconductor integrated circuit device, and more particularly to a symmetrical support device.

In general, Nch-MIS type transistors are shown in Figure 1(a).
The source 17 and the drain 16 are connected to both the surrounding thick isolation insulating film (field oxide film) 12 and the gate electrode material 14. is formed in a self-aligned manner by ion implantation using as a mask. Therefore, the active region under the gate electrode, ie, the channel region 15, borders on the edge of the field oxide film 12. When an NCh transistor with such a structure is irradiated with ionizing radiation (gamma rays, As a result, when a voltage is applied between the drain and the source, a leakage current flows as shown by the arrow in FIG. 1(a), deteriorating the transistor characteristics. In addition, leakage current to other transistors also occurs due to a decrease in isolation voltage between elements, so if the circuit is configured, characteristics may deteriorate, or if the circuit has a complementary MIS configuration, leakage current may This had the disadvantage of causing a latch-up phenomenon.

The above-mentioned decrease in isolation voltage due to ionizing radiation irradiation is due to the fact that holes among the electron-hole pairs generated in the oxide film during irradiation are captured and accumulated in the trap level at the oxide film-substrate interface. However, the thicker the oxide film, the greater the amount of charge accumulated. Generally MOS (metal-
The amount of variation after radiation irradiation in the threshold voltage of a transistor with an oxide film-semiconductor structure is ΔvTil-1, and the oxide film thickness is tox
It is known that the relationship is approximately expressed by the following equation.

△vT ■t0X'4 (1) Therefore, although the threshold voltage varies with both gate oxide film and field oxide film, it is
The threshold voltage fluctuation of the field oxide film, which is twice as thick, has become a more important issue from the standpoint of maintaining circuit functionality.

The present invention covers the above! This was done in view of the above situation, and by extending the element isolation region below the gate oxide film, the above-mentioned drawbacks are solved and a semiconductor integrated circuit device with improved radiation resistance is provided. It is something.

Hereinafter, embodiments of the present invention will be explained using drawings.

FIG. 2 shows an embodiment of the present invention, and Ca1 diagram is M
IS) Planar arrangement of transistors, (b) is a sectional view taken along line AA' in (a).

In the figure, 21 is a semiconductor substrate, 22 is a field oxide film, and 23
2 is a gate oxide film, 24 is a gate electrode material, 25 is a high concentration impurity region for element isolation, and source and drain regions 2
7.28 is formed in a self-aligned manner using the shield electrode 26 for preventing a drop in element isolation breakdown voltage and the gate electrode 24 thereon as a mask. A shield electrode 26 is formed on the gate oxide film.
and the high-concentration impurity region 25 thereunder serve to separate the region under the field oxide film, where a channel is formed due to a huge threshold voltage fluctuation during radiation irradiation, from the source and drain regions 27 and 28 of the transistor. It turns out.

This is because the thickness of the oxide film under the shield electrode is thinner than the thickness of the field oxide film, so that the fluctuation in the threshold value due to continuous radiation irradiation as shown in equation (1) above is small. Of course, the threshold voltage of the current part after radiation irradiation needs to be high enough to prevent channel leakage from occurring under the shield electrode, but if the wiring is connected so that the shield electrode has the same potential as the substrate. As long as the amount of threshold variation due to radiation irradiation is smaller than the initial setting value, channel formation is not performed and the function of isolation between elements is achieved, so it is safe.

Therefore, the impurity concentration of the high concentration impurity region 25 for element isolation is extremely high, for example, about 1010 to 1020 arL-s, for example, 1010 to 1020 CrIL.
Since it does not need to be made to a certain degree, there is a large degree of freedom in the process and it is easy to manufacture. Also, a high concentration impurity region 25 for element isolation.
By having a structure that partially overlaps with the source and drain regions, leakage between the source and drain under the gate electrode near the shield electrode during radiation irradiation is prevented. In addition, the second
In the figure, the shield electrode 26 is formed on the gate oxide film 23, but the same effect can be obtained even if it straddles the gate oxide film and the field oxide film 22.

FIG. 3 shows an example of a method for manufacturing the Nch MOS l transistor of this embodiment. First, a thin oxide film 23 of about several hundred amps is grown on the P-type semiconductor substrate 31, a photosensitive resist is applied, the resist is patterned using photolithography, and ions are implanted using the deceptive resist 34 as a mask. By performing this step, a high impurity concentration region 32 having the same conductivity type as the substrate is formed in the substrate. This region is used to increase the threshold voltage of the parasitic field transistor and at the same time to increase the isolation breakdown voltage of the shield electrode portion to be formed in a later step.

(FIG. 3(a)) Next, after peeling off the resist, a nitride film with a thickness of about 1000 to zoooX is grown on the thin oxide film 33, and the nitride film is buttered using photolithography technology. The structure shown in FIG. 3(b) is obtained. The point to note here is that the nitride film 35 is formed so as to overlap the high impurity concentration region 32 for element isolation, and a field oxide film of about 0.5 to 1 μm is formed by the subsequent long oxidation process. Then, as shown in FIG. 3C, the high impurity concentration region remains in the active region under the nitride film 35, that is, the so-called diffusion layer region. Next, the nitride film is removed and a shielding electrode 37 is formed on the diffusion layer region with a high impurity concentration, but this electrode 37 is formed so as to surround the diffusion layer region as shown in FIG. 2(a). Make it into a shape. At this time, as described above, the periphery of the shield electrode may or may not overlap with the thick field oxide film. In order to suppress the step difference as much as possible, it is desirable that the shield electrode be made of a thin material with low resistance, but it may be made of polycrystalline silicon having a thickness of about 2000 to 5000 Å, for example. (Fig. 3(d)) After this, the thin oxide film 33 is removed and a gate oxide film 33' with a thickness of several hundred amps is grown again to form a gate electrode, resulting in the structure shown in Fig. 3(e). can get. Furthermore, by performing ion implantation to form an L source and a drain using the shield electrode material and gate electrode material as masks, the NCh transistor structure shown in FIG. 2 is obtained.

In the above embodiment, an oxide film is used as the gate insulating film, but it is obvious that other insulating films may be used. It is desirable that the shield electrode and the shield electrode are always at the same potential as the substrate, but even if they are floating, a certain degree of effect can be obtained from equation (1). Furthermore, in the above explanation, a method of forming an NCII l transistor on a semi-dedicated (■) type substrate was shown, but a P type impurity layer (P-well) was
It is also applicable to the case where an NCII) run disk is formed within the NCII.

As explained above, in the present invention, the shielding electrode 7i is formed on a hard oxide film, and the substrate region under the shielding electrode is made into a high impurity concentration region.
This makes it possible to suppress a decrease in the element isolation breakdown voltage of transistors, and realizes an MIS type semiconductor integrated circuit device with excellent radiation resistance. In particular, NCh
When this embodiment is applied to a complementary MI8 semiconductor integrated circuit device in which both transistors are formed on the same substrate to form a circuit, a mechanism occurs that is triggered by leakage current caused by a drop in isolation voltage between elements. This invention is very effective in preventing latch-up.

[Brief explanation of the drawing]

Figures 1 (a) and (b) show the conventional Nch MI
Planar layout and cross-sectional view of S transistor, Figure 2 (
a) and (b) respectively show a plan layout diagram and a cross-sectional view of a transistor according to an embodiment of the present invention, and FIGS. It is something that 11, 21... Semiconductor substrate, 12.22...
...Field insulating film, 13.23...Gate insulating film, 14, 24...Gate lightning, pole, 15
．． 25...High concentration impurity region for element isolation, 16
, 17...source, drain region, 26...
... Shielding amount, pole, 27.28 ... Source, drain region, 31 ... Semiconductor substrate, 32 ...
...High concentration impurity region for element isolation, 33...
Gate oxide film, 34...Photosensitive resist, 35
. . . Nitride film, 36 . . . Field oxide film, 37 . . . Shield electrode, 38 . . . Gate electrode. (o,)'' (b) 1st zo 2nd figure ([L) 3rd figure

Claims (2)

[Claims] (1) MIS (metallic) surrounded by a thick insulating film
It has a plurality of insulating film-semiconductor type transistor elements, and has a shielding electrode formed on a thin oxide film around the source and drain regions as an element isolation means, and a shielding electrode of the same conductivity type as the substrate under the electrode. A semiconductor integrated circuit device comprising a high concentration impurity region. (2) The semiconductor integrated circuit device according to claim (1), wherein the shield electrode is connected to the substrate so that it has the same potential.