JPH0582068B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to the manufacture of a protection circuit element formed in a semiconductor integrated circuit device, particularly a protection circuit element that is more suitable for a new high-voltage MOS FET.

(b) Background of technology In semiconductor integrated circuit devices (hereinafter abbreviated as IC), in order to achieve objectives such as higher integration density and larger scale, there is a need for margins in the junction breakdown voltage of, for example, MIS type elements used for this purpose. protection circuit elements that protect these elements from abnormally high voltages are becoming increasingly important.

Most IC circuits use a power supply voltage of about 5 [V]. However, for example, in ICs that drive fluorescent display tubes, MIS type elements, etc.
It is necessary to operate at a relatively high voltage, and protection circuit elements with an appropriate operating voltage are required.However, unlike normal low operating voltage protection circuit elements, high operating voltage protection circuit elements have a A means to increase the value is needed.

(c) Prior Art and Problems A protection circuit element with a lateral structure is conventionally known as having a structure suitable for high voltage operation.

A P-channel oven drain high voltage output circuit to which a lateral structure protection circuit element is applied is shown in the circuit diagram shown in Fig. 1, in which the drain of the protection circuit element _T1 is connected to the output terminal _V0 , and the source, gate, and substrate are connected to each other. is connected to a reference potential (for example, the power supply voltage V _D ), and when an abnormally high voltage is applied to the output terminal V ₀ , the protection circuit element T ₁ exhibits lateral transistor characteristics, and the output terminal is shorted to the reference potential side. This protects the drain side of the output transistor _T2 from being applied with a high voltage.

FIG. 2 illustrates the cross-sectional structure of such a protection circuit element _T1 , in which a thick field oxide film 3 is formed on an N-type semiconductor substrate 1 via an N ⁺ type channel cut region 2, and A P ⁺ type drain region 4 and a P ⁺ type source region 5 are provided in the active region, respectively. When an abnormally high negative voltage is applied from the output terminal to the protection circuit element having such a structure, the PN junction between the drain region 4 and the channel cut region 2 breaks down, and the substrate 1 is damaged. The potential decreases. Therefore, the substrate 1 and the source region 5 at the reference potential level are in the forward direction, and at the same time a current flows from the source region 5 to the substrate 1, the lateral transistor is activated, and a current flows from the source region 5 to the drain region 4, and the protective element It will serve as a role.

In this way, the protection circuit element with the lateral type (horizontal) structure utilizes the lateral transistor characteristics, and the break occurs at the portion 7 where the drain region 4 on the output terminal V ₀ side contacts the channel cut region 2. The down voltage determines the withstand voltage that can be guaranteed. On the other hand, since the main purpose of the channel cut region is to suppress parasitic transistor operation throughout the IC, the concentration cannot be made very low.

Therefore, with this structure as it is, the voltage is 20 to 30 [V]
This is insufficient as a protection element for high-voltage elements. In the figure, 6 is the gate electrode, 8
indicates a surface protective film such as phosphosilicate glass (PSG), 9 indicates a drain electrode, and 10 indicates a source electrode.

The present inventor previously proposed a structure in which the operating voltage of a protection circuit element with a lateral structure can be made higher than the above-mentioned value in Japanese Patent Application No. 56-136663 (Japanese Unexamined Patent Publication No. 58-1989).
37969).

According to the invention, a protection circuit element having a cross-sectional structure as shown in FIG. 3, for example, is provided. That is, the protection circuit element is provided with a field oxide film 12 on the surface of an N-type semiconductor (silicon) substrate 11 that defines and exposes the active region surface, and is separated by the field oxide film 12. A P + -type high concentration drain region 14 surrounded by a P ^{- -type} low concentration offset 13 is formed in one active region, and a P ⁺ -type high concentration source region 15 is formed in the other active region. Further, an N ⁺ -type high concentration channel cut region 16 is provided in the substrate surface layer below the field oxide film 12 and is in contact with both the offset region 13 and the source region 15. Furthermore, an insulating film 17 such as PSG, a drain electrode 18, a source electrode 19
A gate electrode 20 is formed on the field oxide film 12 between the drain region and the source region, and the drain electrode 18 is connected to the input terminal 21.
A source electrode 19 and a gate electrode 20 are connected to a reference potential terminal 22. In the protection circuit element having the above structure, even if an abnormal voltage is applied to the drain region through the input terminal, the depletion layer in the PN junction 23 has a low impurity concentration.
In order to spread widely within the P ^- type offset region 13,
The breakdown voltage of the protection circuit element can be increased to a value determined by the resistivity of the offset region and the channel cut region.

The protection circuit element having the structure described above is suitable for being formed simultaneously on the same substrate as a MOS FET with an offset gate structure, which is conventionally widely used for high voltage applications, and good results have been obtained. .

(d) Purpose of the invention However, in the structure shown in FIG. 3, in addition to the process of forming the N ⁺ type high concentration channel ^cut region,
A post-formation process for the low concentration offset region 13 is required, and a mask is required to cover the offset region 13 for the subsequent formation of the high concentration P ⁺ type drain electrode. An offset region 13 is provided on the surface of the substrate to surround the drain region, and is covered with PSG. In this structure, when a negative potential is applied to the drain electrode, P ^- type Sodium ions (Na ⁺ ) are collected in the low concentration offset region 13, and the ability of this offset region to improve the withstand voltage is reduced. Therefore, the present invention can reduce the number of steps in the protection circuit element, set the breakdown voltage to a high value, prevent the breakdown voltage from decreasing in the offset region, and still be usable in the same way as before. The purpose is to

(e) Structure of the Invention According to the present invention, the present invention provides a source region and a drain region consisting of high concentration regions of a second conductivity type separated from each other by a field oxide film on the surface of a semiconductor substrate of a first conductivity type; Below the surfaces of the source and drain regions, between the lower part of the field oxide film and the interface with the semiconductor substrate, there is a first layer along the boundary between the field oxide film and one side of the source region, one end of which is in contact with the source region. A punch-through prevention region consisting of a conductive type region, and an offset consisting of a region of a second conductive film having a lower concentration than the drain region whose one end is in contact with the drain region along the boundary between the field oxide film and one side of the drain region. This is achieved by a protection circuit element characterized in that a source region is connected to a reference potential and a drain region is connected to a protected element.

(f) Embodiments of the invention The protection circuit elements according to the present invention will be described below using the same IC.
MOS FETs formed at the same time will be explained in detail by way of embodiments with reference to the drawings.

FIGS. 4a to 4f are schematic sectional views showing the embodiment of the present invention during its manufacturing process.
A subscript a or b is added to indicate the FET and each part.

Refer to Figure 4a. A film with a thickness of several tens of mm is applied to an N-type silicon (Si) substrate 31 with an impurity concentration of, for example, about 4×10 ¹⁵ [cm ^-3 ].
Through a silicon dioxide (SiO ₂ ) film 32 of approximately
A silicon nitride (Si ₃ N ₄ ) film 33 with a thickness of about 100 mm is formed, and the Si ₃ N ₄ film 33 is formed in a region where an insulating film (hereinafter referred to as a field oxide film) that separates and defines each active region is formed. selectively remove.

Next, for the protection circuit element, the entire surface except a selected area near the drain formation region is covered, and for the MOS FET, the window in the inter-element region of the Si ₃ N ₄ film 33 is entirely covered, or the drain is A resist film 34 is applied except for the vicinity of the formation area. Although the protection circuit element of the present invention operates as a lateral transistor, it can also be used as a MOS transistor.
Due to the process of manufacturing at the same time as the FET manufacturing process,
The emitter or collector will be called the source or drain.

After that, for example, boron (B) energy 25
P-type impurity introduced region 35 is formed by implanting ions at a dose of about [KeV] and a dose of about 5×10 ¹² [cm ^-2 ].

Refer to FIG. 4b. The resist film 34 is peeled off, the area other than the channel cut forming area is covered with the resist film 36, and then phosphorus (P) is applied, for example, at an energy of 80 [KeV] and a dose of 5×10 ¹² [cm ^{-2 ]} . ] by implanting ions to the extent of
A type impurity introduction region 37 is formed.

Refer to FIG. 4c. The resist film 36 is peeled off, and selective thermal oxidation is performed using the Si ₃ N ₄ film 33 as an oxidation-resistant mask.
A field oxide film 38 is selectively formed, and the
The Si ₃ N ₄ film 33 and the SiO ₂ film 32 are removed.

The field oxide film 38 formed here forms the drain formation region 40a and source formation region 41a of the protection circuit element, as well as the gate formation region 39b and drain formation region 40b of the MOS FET.
The source forming region 41b is separated and defined, and its position and dimensions are determined.

Note that the P-type impurity doped region 35 and the N-type impurity doped region 37 are located under the field oxide film 38.

Refer to FIG. 4d. A SiO ₂ film 42 is formed on the surface of the Si substrate 31 to a thickness of, for example, about 70 mm, usually by thermal oxidation.
This SiO ₂ film 42 becomes a gate oxide film.

Next, a gate electrode 43b of the MOS FET made of polycrystalline silicon is formed by chemical vapor deposition or the like. This gate electrode 43b can have a shape extending over the field oxide film 38 surrounding the gate formation region 39. Gate electrode 43b
After forming, the excess gate oxide film is removed by etching. After that, each drain forming region 40a and 40
A SiO ₂ film 44 with a thickness of about 50 mm is formed on the exposed surfaces of the source formation regions 41a and 41b.

Next, for example, boron (B) is given an energy of 25
[KeV], dose amount approximately 5×10 ¹⁵ [cm ^-2 ], protection circuit element and drain formation region 40 of MOS FET
a and 40b, source formation regions 41a and 41b
ion implantation. During this implantation, the field oxide film 38 and the gate electrode 4 of the MOS FET are
3b functions as a mask to limit ion implantation to each region defined as above.

Refer to FIG. 4e. A surface protective film 45 made of phosphosilicate glass (PSG) or the like is provided on the entire surface of the base 31.

A window for electrode formation is provided in the surface protection film 45,
SiO ₂ film 4 replacing the SiO ₂ film 44 from which the window portion has been removed
4' is formed at low temperature.

Next, the activation of the ions implanted so far and
Heat treatment is performed for the purpose of smoothing the surface of the PSG surface protection film 45. This heat treatment determines the depth of the P ⁺ type impurity in each drain region 40a and 40b and source formation region 41a and 41b, but this heat treatment is performed in a nitrogen atmosphere, and the conditions are, for example, a temperature of 1050 [℃], time 10
It takes about a minute.

Also, by this heat treatment, the P type impurity introduced region 35 becomes a P ^- type offset region 35 or a P - type low concentration region 35', and the N type impurity introduced region 37 becomes a P ^- type offset region 35 or a P - type low concentration region 35'.
This becomes an N ⁺ type channel cut region 37. (This region 37 is provided to prevent punch-through in the protection circuit element, but it is
This is tentatively called a channel cut region 37 due to the FET process. ) Refer to FIG. 4f. By removing the SiO ₂ film 44' and using aluminum (Al), for example, as for the protection circuit element,
A gate electrode or shield electrode 43a is placed on the field oxide film 48 between the drain region 40a and the source region 41b, and a drain electrode 46a and a source electrode 47a in contact with each region are connected to a MOS FET.
Similarly, a drain electrode 46b, a source electrode 47b, and a gate pipe 48 are provided. Electrode 43
a does not act as a gate for a normal FET, but acts as a potential-fixing shield electrode.
For convenience, it is called the gate electrode because it is manufactured in the same process as the MOS FET. Note that necessary wiring and the like can also be formed at the same time.

As is known from the manufacturing method of the embodiments described above, by applying the structure of the present invention to the protection circuit element of the lateral structure, which is originally a bipolar type element, the high withstand voltage type of the new structure explained at the same time in the embodiments can be realized. At the same time as an offset gate type MOS FET, it can be formed with fewer steps than conventional methods.

In the above embodiment, the guaranteed breakdown voltage is improved by separating the N ⁺ type channel cut region 37 from the P type offset region 35 of the protection circuit element, but depending on the target operating voltage, both regions may be separated. There is no need for isolation, and
The P ^- type low concentration region 35' may be omitted.

The protection circuit element of the present invention has a drain electrode 46a.
By connecting the source electrode 47a and the gate electrode 43a to the reference potential terminal to the input terminal of a circuit made of a MOS FET, the same function as the protection circuit element of the conventional example can be obtained. In the protection circuit element of the present invention, since the P ^- type offset region 35 is provided under the thick field oxide film 38, even when a negative potential is applied to the drain region, sodium ions (Na ⁺ ) does not enter the offset region through the PSG and thick field oxide film, and the withstand voltage in this area is improved compared to the conventional example. By the way, although the function as a protection element can be achieved even without the gate electrode 43a, it is better to provide it in order to guarantee reliability.

Note that the protection circuit element of the present invention can also be adapted to the conductivity type of a MOS FET by being of a conductivity type opposite to that of the above-mentioned embodiments.

(g) Effects of the Invention As explained above, the present invention provides a new offset gate structure MOS with improved characteristics.
It is now possible to easily integrate FETs and their protection circuit elements into ICs with fewer steps than before.
It becomes possible to better meet the demands for semiconductor devices from various application fields.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a circuit of a protection circuit element, Figs. 2 and 3 are sectional views showing an example of a conventional protection circuit element, and Figs. FIG. 3 is a schematic cross-sectional view showing a state during a manufacturing process together with a MOS FET. In the figure, 31 is an N-type silicon substrate, 33 is a silicon nitride film, 35 is a P-type impurity doped region and
P ^- type offset region, 35' is P ^- type low concentration region,
37 is an N type impurity introduction region and an N ⁺ type channel cut region, 38 is a field oxide film, 40a and 40b are drain regions, 41a and 41b are source regions, 42 is a gate oxide film, 43a and 43b
is a gate electrode, 45 is a protective film, 46a and 46b
indicates the drain electrode, 47a and 47b indicate the source electrode, the subscript a indicates the protection circuit element, and the subscript b indicates the MOS
Indicates that it applies to FET.

Claims (1)

[Claims] 1. A source region and a drain region consisting of high concentration regions of a second conductivity type separated from each other by a field oxide film are provided on the surface of a semiconductor substrate of a first conductivity type, and a field oxide film is provided below the surface of the source region and the drain region. a punch-through prevention region consisting of a first conductivity type region whose one end is in contact with the source region along the boundary between the field oxide film and one side of the source region, between the lower part of the field oxide film and the interface with the semiconductor substrate; An offset region is provided along the boundary between the field oxide film and the first side of the drain region, the offset region consisting of a region of a second conductivity type having a lower concentration than the drain region, one end of which is in contact with the drain region, and the source region is connected to a reference potential. A protection circuit element characterized in that the drain region is connected to a protected element.