JPS6359258B2 - - Google Patents
Info
- Publication number
- JPS6359258B2 JPS6359258B2 JP54126574A JP12657479A JPS6359258B2 JP S6359258 B2 JPS6359258 B2 JP S6359258B2 JP 54126574 A JP54126574 A JP 54126574A JP 12657479 A JP12657479 A JP 12657479A JP S6359258 B2 JPS6359258 B2 JP S6359258B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- semiconductor
- type region
- opposite conductivity
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 description 32
- 230000015556 catabolic process Effects 0.000 description 13
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 10
- 230000005669 field effect Effects 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- -1 boron ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は、高耐圧保護素子を備えて高耐圧素子
の保護をさせている半導体集積回路装置の改良に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a semiconductor integrated circuit device that is equipped with a high voltage protection element to protect the high voltage element.
一般に、半導体集積回路装置では、チツプ周辺
部分に入出力用高耐圧素子群が形成され、それ等
の内側に標準耐圧素子群が形成されている。入出
力用の素子として高耐圧のものを用いるのは外部
接続される装置からの影響や静電気に依る影響に
対処させることが理由の一つになつているが、そ
れでも破壊される場合があるので、入出力ライン
と接地間に保護素子（回路）を挿入し、ラインに
異常高電圧が印加されたときに該保護素子がブレ
イク・ダウンしてラインを接地することが行なわ
れている。 Generally, in a semiconductor integrated circuit device, a group of input/output high-voltage elements is formed around a chip, and a standard-voltage element group is formed inside these elements. One of the reasons why high-voltage elements are used as input/output elements is to counteract the effects of externally connected devices and static electricity, but they can still be destroyed. A protection element (circuit) is inserted between an input/output line and ground, and when an abnormally high voltage is applied to the line, the protection element breaks down and grounds the line.
ところで、前記のような入出力用高耐圧素子を
保護する為の素子はそれ自体の耐圧も或る程度高
くなければならない。その保護素子の耐圧を向上
するには、例えば集積回路装置がｎチヤネルMIS
（Metal Insulator Semiconductor）素子を主体
とするものであれば、保護素子に於けるn+型不
純物拡散領域の周囲にn-型不純物領域を形成す
ることが行なわれている。しかしながら、そのよ
うにすると保護素子の耐圧が保護されるべき高耐
圧素子のそれに比較して高くなる傾向に在り、従
つて、保護素子がブレイク・ダウンする前に保護
されるべき高耐圧素子が先に破壊されてしまう事
故がしばしば発生している。このような事故を生
じないようにする為にはn-型不純物領域の不純
物濃度を適当に選択すれば良いと考えられるであ
ろうが、その制御は甚だ困難である。 By the way, the element for protecting the high voltage input/output element as described above must also have a certain level of voltage resistance. In order to improve the withstand voltage of the protection element, for example, if the integrated circuit device is an n-channel MIS
(Metal Insulator Semiconductor) element, an n - type impurity region is formed around the n + type impurity diffusion region in the protection element. However, in this case, the withstand voltage of the protection element tends to be higher than that of the high voltage element to be protected, and therefore, the high voltage element to be protected comes first before the protection element breaks down. Accidents resulting in destruction often occur. In order to prevent such accidents from occurring, it may be considered that the impurity concentration of the n - type impurity region should be appropriately selected, but it is extremely difficult to control this.
本発明は、保護素子の耐圧を前記のようなn-
型不純物領域を持たないものよりも高く、また、
保護すべき高耐圧素子に比較すると僅かに低く設
定することを容易になし得るように、そして、保
護素子は他の素子を製造する工程を利用して同時
に形成できるようにするものであり、以下これを
詳細に説明する。 In the present invention, the withstand voltage of the protection element is set to n -
higher than that without type impurity region, and
In order to easily set the voltage to be slightly lower than the high-voltage element to be protected, and to enable the protection element to be formed at the same time using the process of manufacturing other elements, the following This will be explained in detail.
第１図乃至第７図は本発明一実施例を製造する
場合を説明する為の工程要所に於ける半導体集積
回路装置の要部側断面図であり、次にこれ等の図
を参照しつつ記述する。 1 to 7 are side sectional views of main parts of a semiconductor integrated circuit device at key points in the process for explaining the case of manufacturing an embodiment of the present invention, and these figures will be referred to next. Describe it in detail.
第１図参照
(1) Ｐ型シリコン半導体基板１に例えば窒化シリ
コン膜をマスクとするアクセプタ例えば硼素イ
オンの注入及びこれに続く通常の選択酸化法に
て、その直下にP+型チヤンネルカツト領域CC
を有する二酸化シリコン・フイールド用絶縁膜
２を厚さを例えば8000〔Å〕に形成する。尚、
QE0はエンハンスメント型オフセツト・ゲート
高耐圧電界効果トランジスタ形成領域、QEは
エンハンスメント型電界効果トランジスタ形成
領域、QDはデイプレツシヨン型電界効果トラ
ンジスタ形成領域、QLは保護素子（回路）で
あるラテラル型npnトランジスタ形成領域をそ
れぞれ指示している（これ等領域は以下第７図
に至るまで変りない）。Refer to Fig. 1 (1) A P + type channel cut region CC is formed directly under the P type silicon semiconductor substrate 1 by implanting an acceptor such as boron ions using a silicon nitride film as a mask, followed by a conventional selective oxidation method.
A silicon dioxide field insulating film 2 having a thickness of, for example, 8000 Å is formed. still,
Q E0 is an enhancement type offset gate high voltage field effect transistor formation region, Q E is an enhancement type field effect transistor formation region, Q D is a depletion type field effect transistor formation region, and Q L is a lateral type protection element (circuit). The npn transistor forming regions are indicated respectively (these regions do not change until the subsequent steps shown in FIG. 7).
第２図参照
(2) 例えば熱酸化法を適用し、二酸化シリコン・
ゲート絶縁膜２Ｇを厚さ例えば700〔Å〕程度に
形成する。See Figure 2 (2) For example, by applying a thermal oxidation method, silicon dioxide
The gate insulating film 2G is formed to have a thickness of, for example, about 700 [Å].
(3) 閾値電圧Vth、ドレイン・ソース間電流IDSS
を調整する為、エンハンスメント型の領域
QE0，QEには硼素イオン（B+）を、また、デイ
プレツシヨン型の領域QDにはB+及び燐イオン
（P+）の注入を行なう。(3) Threshold voltage Vth, drain-source current I DSS
In order to adjust the enhancement type area
Boron ions (B + ) are implanted into Q E0 and Q E , and B + and phosphorus ions (P + ) are implanted into the depletion type region Q D.
第３図参照
(4) ノン・バツテイング・コンタクトを採る必要
があればそれについての窓開けを例えば通常の
フオト・リソグラフイ技術を適用して行なう。See Figure 3 (4) If it is necessary to make a non-butting contact, a window is opened for it, for example, by applying ordinary photolithography technology.
(5) 例えば化学気相成長法を適用して多結晶シリ
コン層を厚さ例えば4000〔Å〕適度に成長させ
る。この多結晶シリコン層は不純物含有であつ
ても良い。(5) For example, by applying chemical vapor deposition, a polycrystalline silicon layer is grown to a suitable thickness, for example, 4000 [Å]. This polycrystalline silicon layer may contain impurities.
(6) 通常のフオト・リソグラフイ技術にて、前記
多結晶シリコン層のパターニングを行ない、シ
リコン・ゲート電極３Ｇを形成する。(6) The polycrystalline silicon layer is patterned using normal photolithography technology to form a silicon gate electrode 3G.
(7) イオン注入法を適用し、P+の注入を行ない
オフセツト・ゲート用のn-型不純物領域４を
形成する。この際、他の部分にもP+が注入さ
れるが、それは後の工程で更に不純物が導入さ
れてn+型不純物領域になされる。尚、n-型不
純物領域４のイオン注入量は１×1012〔cm-2〕
程度である。(7) Applying the ion implantation method, P + is implanted to form the n - type impurity region 4 for the offset gate. At this time, P + is implanted into other parts, but impurities are further introduced in a later step to form n + type impurity regions. The ion implantation amount for the n - type impurity region 4 is 1×10 12 [cm -2 ]
That's about it.
第４図参照
(8) 通常のフオト・リソグラフイ技術にてゲート
絶縁膜２Ｇのパターニングを行なう。尚、領域
QE0のゲート絶縁膜２Ｇは他の領域QE，QDのそ
れと比較すると若干長くなつている。また、領
域QLに於いては該ゲート絶縁膜を全部除去す
る。See FIG. 4 (8) Patterning of the gate insulating film 2G is performed using normal photolithography technology. Furthermore, the area
The gate insulating film 2G of Q E0 is slightly longer than that of the other regions Q E and Q D. Further, in the region Q L , the gate insulating film is completely removed.
第５図参照
(9) 適当な不純物導入技術、例えばイオン注入
法、固相−固相拡散法などを適用してソース領
域、ドレイン領域形成の為の不純物導入を行な
い、n+型ソース領域５SEO，５SE，５SD、n+型ド
レイン領域５DEO，５DE，５DDを形成するととも
に領域QLに於けるラテラル型npnトランジスタ
のn+型不純物領域６D（第一の反対導電型不純
物領域）及びn+型不純物領域６S（第二の反対
導電型不純物領域）を形成する。尚、これ等
n+型の各領域をイオン注入法で形成した場合
のドーズ量は５×1015〔cm-2〕程度である。Refer to Figure 5 (9) Applying an appropriate impurity introduction technique such as ion implantation, solid phase-solid phase diffusion, etc., impurities are introduced to form the source region and drain region, and the n + type source region 5 is formed. SEO , 5 SE , 5 SD , n + type drain regions 5 DEO , 5 DE , 5 DD are formed, and n + type impurity region 6 D (first opposite conductivity type (impurity region) and an n + type impurity region 6 S (second opposite conductivity type impurity region). Furthermore, these etc.
When each n + type region is formed by ion implantation, the dose is about 5×10 15 [cm −2 ].
第６図参照
(10) 例えば化学気相成長法を適用し、燐硅酸ガラ
ス（PSG）層間絶縁膜７を厚さ例えば〜１
〔μm〕程度に成長させる。See Figure 6 (10) For example, by applying chemical vapor deposition, a phosphosilicate glass (PSG) interlayer insulating film 7 is formed to a thickness of, for example, ~1.
Grow to about [μm].
(11) 通常のフオト・リソグラフイ技術を適用して
層間絶縁膜７のパターニングを行ない電極コン
タクト窓を形成する。この際、領域QLに於け
る不純物領域６D上の電極コンタクト窓ではフ
イールド用絶縁膜２が露出するように層間絶縁
膜７のパターニングを若干大きくする。(11) The interlayer insulating film 7 is patterned using ordinary photolithography technology to form electrode contact windows. At this time, the patterning of the interlayer insulating film 7 is slightly enlarged so that the field insulating film 2 is exposed in the electrode contact window on the impurity region 6D in the region QL .
(12) 必要に応じて前記露出されたフイールド用絶
縁膜２の選択エツチングを行なつて、その部分
の厚さを最初の厚さよりも例えば500〔Å〕程度
薄くする。かかる工程(12)は、必ずしも必要では
なく、工程(11)における層間絶縁膜７に対する電
極コンタクト窓の形成の際発生するオーバーエ
ツチング現象によつても同様の状態が得られ
る。(12) If necessary, the exposed field insulating film 2 is selectively etched to make the thickness of that portion thinner, for example, by about 500 [Å] than the initial thickness. This step (12) is not necessarily necessary, and a similar state can be obtained by the overetching phenomenon that occurs when forming the electrode contact window on the interlayer insulating film 7 in step (11).
第７図参照
(13) 例えば蒸着法を適用し、例えばアルミニウ
ム層を形成し、そのアルミニウム層を通常のフ
オト・リソグラフイ技術にてパターニングして
エンハンスメント型オフセツト・ゲート高耐圧
電界効果トランジスタのソース電極８SEO、ゲ
ート電極８GEO、ドレイン電極８DEO、エンハン
スメント型電界効果トランジスタのソース電極
９SE、ゲート電極９GE、ドレイン電極９DE、デ
イプレツシヨン型電界効果トランジスタのソー
ス電極１０SD、ゲート電極１０GD、ドレイン電
極１０DD、ラテラル型npnトランジスタの電極
１１D，１１Sを形成する。See Figure 7 (13) For example, by applying a vapor deposition method, for example, an aluminum layer is formed, and the aluminum layer is patterned using ordinary photolithography technology to form a source electrode of an enhancement type offset gate high voltage field effect transistor. 8 SEO , gate electrode 8 GEO , drain electrode 8 DEO , source electrode 9 SE of enhancement type field effect transistor, gate electrode 9 GE , drain electrode 9 DE , source electrode 10 SD of depletion type field effect transistor, gate electrode 10 GD , A drain electrode 10 DD and electrodes 11 D and 11 S of a lateral type npn transistor are formed.
このようにして製造されるが、本装置に於ける
保護素子であるラテラル型npnトランジスタがn-
型不純物領域を要することなく耐圧が向上し、し
かも、その耐圧上昇を容易に制御できることを第
８図を参照して説明する。 Although manufactured in this way, the lateral type npn transistor, which is the protection element in this device, is n -
The fact that the breakdown voltage is improved without requiring a type impurity region and that the increase in breakdown voltage can be easily controlled will be explained with reference to FIG.
第８図は第７図の要部拡大図であつて同部分は
同記号で指示してある。 FIG. 8 is an enlarged view of the main parts of FIG. 7, and the same parts are indicated by the same symbols.
図は勿論保護素子の部分であり、この素子に関
して重要なことは、入力端子（回路）に接続され
る電極１１Dが絶縁膜２の露出部分及び絶縁膜７
の一部をも覆うように形成されていることであ
り、この構成は紙面と直交する方向に関しても同
様である。そして、これに依り電極１１D、絶縁
膜２、基板１からなる第１のMIS構造と、電極１
１D、絶縁膜７及び２、基板１からなる第２の
MIS構造が得られている。従つて、第１のMIS構
造に於ける絶縁膜厚は薄く、第２のMIS構造に於
けるそれは遥かに厚い。なお電極１１Sは接地又
は基板電位に接続される。 The figure shows, of course, a portion of the protective element, and the important thing about this element is that the electrode 11D connected to the input terminal (circuit) is connected to the exposed part of the insulating film 2 and the insulating film 7.
This structure is also the same in the direction perpendicular to the plane of the paper. As a result, the first MIS structure consisting of the electrode 11D , the insulating film 2, and the substrate 1, and the electrode 1
1 D , a second layer consisting of insulating films 7 and 2, and substrate 1
MIS structure has been obtained. Therefore, the insulation film thickness in the first MIS structure is thin, and that in the second MIS structure is much thicker. Note that the electrode 11S is connected to ground or substrate potential.
さて、ここで電極１１Dと基板１との間に、基
板１と領域６Dとで形成されるｐ・ｎ接合に逆バ
イアスが加わるような電圧を印加すると、前記第
２のMIS構造の基板表面にはその上の絶縁膜が厚
いこと、絶縁膜７中に燐が存在していることなど
の理由に依り前記電圧の影響は現われない。しか
しながら、前記第１のMIS構造の基板表面に於け
る領域６Dの曲率半径の小なる部分に燐接するｐ
型周辺部分にはクーロン力に基づいて基板１中の
少数キヤリヤである電子１２が引き寄せられ、逆
に正孔は追い払われるので、そこにｎ型反転層が
自然に形成され、そのｎ型反転層は従来技術とし
てさきに記述したn-型不純物領域と同じ働きを
することになり、そしてそれに依る耐圧上昇は保
護すべき高耐圧素子、即ち、図示例ではエンハン
スメント型オフセツト・ゲート高耐圧電界効果ト
ランジスタの耐圧を上廻らないように制御するこ
とは容易である。その理由は、該保護素子の耐圧
は前記フイールド用絶縁膜２下に配設されるチヤ
ンネルカツト領域CCの不純物濃度に依存するこ
とによる。前記ｎ型反転層と近接するチヤンネル
カツト領域CCの不純物濃度（注入イオンのドー
ズ量）を選択することによつて、当該保護素子の
ブレインダウン電圧を保護されるべき素子の耐圧
以下とすることができる。チヤンネルカツト領域
の不純物濃度を高めれば耐圧は低下し、チヤンネ
ルカツト領域の不純物濃度を低くすれば耐圧は上
昇する。したがつて、前記実施例にあつても、必
要に応じて素子形成領域QEO，QE及びQDの周囲に
形成されるチヤンネルカツト領域の不純物濃度と
保護素子の周囲に形成されるチヤンネルカツト領
域の不純物濃度を変えるとよい。 Now, when a voltage is applied between the electrode 11D and the substrate 1 so as to apply a reverse bias to the p/n junction formed by the substrate 1 and the region 6D , the substrate of the second MIS structure The influence of the voltage does not appear on the surface due to reasons such as the thickness of the insulating film thereon and the presence of phosphorus in the insulating film 7. However, in the region 6D on the substrate surface of the first MIS structure, which is in contact with the small radius of curvature,
Electrons 12, which are minority carriers in the substrate 1, are attracted to the area around the mold based on the Coulomb force, and holes are driven away, so an n-type inversion layer is naturally formed there. has the same function as the n - type impurity region described earlier as a conventional technique, and the increase in breakdown voltage due to this increases the breakdown voltage of the high breakdown voltage element to be protected, that is, in the illustrated example, an enhancement type offset gate high breakdown voltage field effect transistor. It is easy to control the voltage so that it does not exceed the withstand voltage. The reason for this is that the breakdown voltage of the protection element depends on the impurity concentration of the channel cut region CC provided under the field insulating film 2. By selecting the impurity concentration (dose of implanted ions) of the channel cut region CC adjacent to the n-type inversion layer, the brain-down voltage of the protection element can be set to be lower than the breakdown voltage of the element to be protected. can. If the impurity concentration in the channel cut region is increased, the breakdown voltage will be lowered, and if the impurity concentration in the channel cut region is lowered, the breakdown voltage will be increased. Therefore, even in the above embodiment, the impurity concentration of the channel cut region formed around the element formation regions Q EO , Q E and Q D and the channel cut formed around the protection element may be changed as necessary. It is better to change the impurity concentration in the region.
前記実施例では、領域６Dには金属の電極１１D
が接触しているが、これは多結晶シリコンを用い
る構成にしても良く、その例が第９図に示されて
いる。 In the above embodiment, a metal electrode 11D is provided in the region 6D .
are in contact with each other, but this may also be constructed using polycrystalline silicon, an example of which is shown in FIG.
第９図に於ける記号１３は多結晶シリコン電極
を指示しており、また、前記実施例にて説明した
部分と同部分は同記号で指示してある。尚、必要
あれば領域６Sに接する電極１１Sも多結晶シリコ
ンを用いたノン・バツテイング方式で形成しても
良い。 The symbol 13 in FIG. 9 indicates a polycrystalline silicon electrode, and the same parts as those explained in the previous embodiment are indicated by the same symbols. Incidentally, if necessary, the electrode 11S in contact with the region 6S may also be formed by a non-batting method using polycrystalline silicon.
以上の説明で判るように、本発明に依れば、高
耐圧半導体素子を保護する高耐圧半導体保護素子
として、ラテラル型半導体素子を用い、それを構
成する不純物領域の中、電圧が印加される側の不
純物領域に於いては、それと基板との間で形成さ
れるpn接合からフイールド部分に向つてその上
に在る絶縁膜を薄く形成し、且つ、前記不純物領
域とコンタクトを採つた電極のエツジを少なくと
も前記薄く形成した絶縁膜の部分まで延在させて
あるので、その電極に電圧を印加することに依つ
て前記不純物領域周辺の薄い絶縁膜直下には同導
電型の反転層が形成されるようにして、該反転層
の作用で前記不純物領域の耐圧を高め、しかも、
その耐圧は保護すべき高耐圧半導体素子のそれよ
りも大にならないように容易に制御することがで
きるのでその保護作用は確実である。また、本発
明装置を製造するにあたつてはn-型（或いはP-
型）不純物領域を形成する必要が無いから、その
工程は簡単である。 As can be seen from the above explanation, according to the present invention, a lateral type semiconductor element is used as a high voltage semiconductor protection element that protects a high voltage semiconductor element, and a voltage is applied to the impurity region constituting the lateral type semiconductor element. In the impurity region on the side, an insulating film is formed thinly from the pn junction formed between the impurity region and the substrate toward the field portion, and an electrode is made in contact with the impurity region. Since the edge extends to at least the thinly formed insulating film, by applying a voltage to the electrode, an inversion layer of the same conductivity type is formed directly under the thin insulating film around the impurity region. The breakdown voltage of the impurity region is increased by the action of the inversion layer, and
Since its breakdown voltage can be easily controlled so as not to become higher than that of the high breakdown voltage semiconductor element to be protected, its protective effect is reliable. Furthermore, when manufacturing the device of the present invention, n - type (or P - type)
Since there is no need to form an impurity region (type), the process is simple.
第１図乃至第７図は本発明一実施例を製造する
場合を説明する為の工程要所に於ける装置の要部
側断面図、第８図は装置の要部拡大側断面図、第
９図は他の実施例の要部拡大側断面図である。
図に於いて、１は基板、２はフイールド用絶縁
膜、６D，６Sはラテラル型npnトランジスタのn+
型不純物領域、７は絶縁膜、１１D，１１Sは電
極、１２は電子である。
1 to 7 are side sectional views of the main parts of the apparatus at key points in the process for explaining the case of manufacturing an embodiment of the present invention, FIG. 8 is an enlarged side sectional view of the main parts of the apparatus, and FIG. FIG. 9 is an enlarged side sectional view of a main part of another embodiment. In the figure, 1 is the substrate, 2 is the field insulating film, and 6 D and 6 S are the n + lateral type npn transistors.
7 is an insulating film, 11 D and 11 S are electrodes, and 12 is an electron.
Claims (1)
素子を有する半導体集積回路装置に於いて、 前記半導体保護素子は、 装置の他の素子部分と共通である一導電型の半
導体基板中に形成され該半導体基板との間にpn
接合を形成すると共に保護されるべき半導体素子
の入力端或いは出力端に接続される第一の反対導
電型領域と、 該第一の反対導電型領域の近傍に在つて接地或
いは前記一導電型の半導体基板と同電位にする為
の電極とコンタクトしている第二の反対導電型領
域と、 前記第一の反対導電型領域と該第二の反対導電
型領域との間に形成されて該第一の反対導電型領
域に於ける前記pn接合の端部分を覆い且つ電圧
が印加された際にその影響を該pn接合の端部分
近傍に及ぼし得る程度に薄く成されたフイールド
部分を有する絶縁膜と、 前記第一の反対導電型領域にコンタクトし且つ
エツジが該絶縁膜の薄く形成されたフイールド部
分直上にまで延在し接触している電極と から構成されて耐圧が前記保護されるべき半導体
素子のそれよりも小さいラテラル型トランジスタ
を成していること を特徴とする半導体集積回路装置。[Claims] 1. In a semiconductor integrated circuit device having a semiconductor element and a semiconductor protection element for protecting the element, the semiconductor protection element is a semiconductor substrate of one conductivity type that is common to other element parts of the device. A pn is formed in the semiconductor substrate and between it and the semiconductor substrate.
a first opposite conductivity type region that forms a junction and is connected to an input end or an output end of a semiconductor element to be protected; a second opposite conductivity type region in contact with an electrode for making the potential the same as the semiconductor substrate; and a second opposite conductivity type region formed between the first opposite conductivity type region and the second opposite conductivity type region. an insulating film having a field portion that covers the end portion of the pn junction in one opposite conductivity type region and is made thin enough to exert its influence on the vicinity of the end portion of the pn junction when voltage is applied; and an electrode that is in contact with the first opposite conductivity type region and whose edge extends directly above and in contact with the thinly formed field portion of the insulating film, so that the withstand voltage is the same as that of the semiconductor to be protected. A semiconductor integrated circuit device comprising a lateral transistor smaller than that of an element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12657479A JPS5650527A (en) | 1979-09-29 | 1979-09-29 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12657479A JPS5650527A (en) | 1979-09-29 | 1979-09-29 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5650527A JPS5650527A (en) | 1981-05-07 |
| JPS6359258B2 true JPS6359258B2 (en) | 1988-11-18 |
Family
ID=14938527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12657479A Granted JPS5650527A (en) | 1979-09-29 | 1979-09-29 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5650527A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276346A (en) * | 1983-12-26 | 1994-01-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having protective/output elements and internal circuits |
| US5610089A (en) * | 1983-12-26 | 1997-03-11 | Hitachi, Ltd. | Method of fabrication of semiconductor integrated circuit device |
| JPS61195721A (en) * | 1985-02-26 | 1986-08-30 | Nisshinbo Ind Inc | Nc sheet material working machine |
| US5371395A (en) * | 1992-05-06 | 1994-12-06 | Xerox Corporation | High voltage input pad protection circuitry |
| US5545910A (en) * | 1994-04-13 | 1996-08-13 | Winbond Electronics Corp. | ESD proctection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511394A (en) * | 1974-03-19 | 1976-01-08 | Norsk Hydro As | |
| JPS5324157A (en) * | 1976-08-18 | 1978-03-06 | Sanyo Electric Co Ltd | Control circuit of air conditioner |
| JPS5365081A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Field effect semiconductor device |
-
1979
- 1979-09-29 JP JP12657479A patent/JPS5650527A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS511394A (en) * | 1974-03-19 | 1976-01-08 | Norsk Hydro As | |
| JPS5324157A (en) * | 1976-08-18 | 1978-03-06 | Sanyo Electric Co Ltd | Control circuit of air conditioner |
| JPS5365081A (en) * | 1976-11-22 | 1978-06-10 | Nec Corp | Field effect semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5650527A (en) | 1981-05-07 |
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