JP2890532B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor integrated circuit devices such as bipolar transistors, field effect transistors (MOS, CMOS).
Etc.) and a method of manufacturing a semiconductor device having a composite structure in which a bipolar transistor and a MOS element coexist on the same chip.

2. Description of the Related Art In recent years, in the field of integrated circuit devices, a composite device has been realized between a bipolar element and a MOS element, which were conventionally used alone, and thereby, a higher speed and a higher performance have been achieved. It is becoming important to develop and optimize manufacturing technologies to realize composite devices.

As an example of a method for manufacturing a silicon semiconductor composite device,
A method of manufacturing a semiconductor device as shown in FIG. 4 in which a bipolar element and a MOS element are made to coexist using a conventional technique can be considered. The background of the prior art will be described while briefly describing the method of manufacturing the composite device with reference to FIG.

As shown in FIG. 4A, an N-type buried semiconductor region 102 is formed on a single-crystal P-type substrate 100 by ion implantation, and an N-type single-crystal semiconductor layer 104 is formed by epitaxial growth. After the ion implantation of boron, the P-type element isolation layer 108 is formed by heat treatment, and the surface of the epitaxial layer 104 is thermally oxidized to form a buffer oxide film 110 and a nitride film 112 thereon.
An element isolation film 114 is formed by selectively growing a thermal oxide film by a selective oxidation method (LOCOS method).

As shown in FIG. 4B, after removing the nitride film 112 and the oxide film 110, they are oxidized again to form a gate oxide film 115, and a collector wall is formed by a phosphorus ion implantation method using the resist pattern 156 as a mask. N-type semiconductor region 118 is formed.

After the resist 156 is removed as shown in FIG. 4 (c), polysilicon is deposited by a CVD method, a polysilicon pattern 133 to be a gate portion of the MOS transistor is formed, and the oxide film 115 is further etched. It is not always necessary to remove the gate oxide film at this time). Further, the base layer 122 and the source region 1 which is a P-type semiconductor region
28A and a drain region 128B are respectively formed by ion implantation, an oxide film 126 is further deposited by CVD, openings for collector windows and emitter windows are selectively formed by etching, and a polycrystalline semiconductor film is formed by CVD. Deposit polysilicon 134.

As shown in FIG. 4D, a collector polysilicon electrode pattern 124A and an emitter polysilicon electrode pattern 134B of the bipolar transistor are formed by an etching method using a resist pattern, and further, a collector metal electrode 140A and an emitter Metal electrode 140B, base metal electrode 140C, source metal electrode 140D, drain metal electrode
Form 140E.

Thus, the P-channel MOS element and the vertical bipolar transistor coexist.

Problems to be Solved by the Invention There are the following problems in a method of manufacturing a bipolar device by a conventional process as shown in FIG. 4 or a semiconductor device in which a bipolar device and a MOS device coexist.

(1) As shown in FIG. 4 (b), a resist pattern 156 is used to form an N-type semiconductor region 118 for a collector wall. Therefore, contamination of the gate oxide film by the resist is likely to occur. This contamination causes MO
Occurs variation in the threshold voltage of the transistor S (V _T), also instability on the reliability V _T is likely to occur, is a problem. In order to prevent the gate oxide film 115 from being contaminated, a method of forming an N-type semiconductor region 118 before forming the gate oxide film 115 may be considered. MOS from the surface of the semiconductor region 118
And the like, or out-diffusion of N-type impurities into the active transistor region of a coexisting bipolar transistor (evaporation of high-concentration impurities during high-temperature heat treatment), for example, N There is a drawback that contamination by mold impurities easily occurs.

(2) As shown in FIG. 4 (c), when the polysilicon 134 is deposited by the CVD method and then annealed, high concentration impurities from the N-type region 118 serving as a collector region are removed. By spreading through
N-type impurities such as phosphorus penetrate from the base surface through the opening of the emitter and cause contamination of the P-type base surface.
There is a problem that the junction depth of the N-type semiconductor region which will later be formed in the base and which serves as the emitter is out of order, leading to an increase in the variation of the current amplification factor of the transistor.

(3) LOCOS the base end near the collector
Since the positioning is performed by the process, the dimension of the electrical isolation between the collector and the base becomes unnecessarily large due to the so-called bird's beak pattern conversion in the LOCOS process. For this reason, it is necessary to design in consideration of the reduction of the base region, which leads to an increase in the size of the bipolar transistor, which is a problem for high integration.

The present invention solves these problems, a bipolar element,
Another object of the present invention is to provide a new semiconductor device manufacturing method in which a bipolar element and a MOS element coexist.

Means for Solving the Problems In order to solve the problems, a first manufacturing method of the present invention includes a step of forming an insulating film on a first conductivity type single crystal semiconductor layer region serving as a collector; Forming a collector opening in the insulating film; depositing a non-single-crystal semiconductor film on the insulating film in which the opening is formed and the opening; Forming a non-single-crystal semiconductor film pattern for extracting a collector by patterning into a shape for extracting, and introducing an impurity of a first conductivity type into the semiconductor layer region through the opening for the collector, thereby extracting a collector electrode. Forming a first semiconductor region of the first conductivity type for use in the semiconductor layer region using the non-single-crystal semiconductor film pattern drawn to the base formation scheduled portion side as a mask Selectively forming a second semiconductor region of a second conductivity type serving as a base, and a first semiconductor region for leading a collector electrode.
And a second semiconductor region serving as a base.

Further, according to a second manufacturing method of the present invention, a step of forming a first insulating film on a first-conductivity-type single-crystal semiconductor layer region serving as a collector; Forming a second insulating film for a gate on the portion where the field-effect transistor is to be formed after removing the first insulating film; and forming a first insulating film on the first insulating film and the second insulating film. Depositing an opening for a collector in the first non-single-crystal semiconductor film;
Removing the first insulating film in the collector opening; and forming the collector on the first non-single-crystal semiconductor film in which the collector opening is formed and removing the first insulating film from the first insulating film. Depositing a second non-single-crystal semiconductor film on the opening, and patterning the first and second non-single-crystal semiconductor films to form a non-single-crystal semiconductor film pattern for extracting a collector and a gate electrode. Forming a non-single-crystal semiconductor film pattern and introducing a first conductivity type impurity into the semiconductor layer region through the collector opening to form a first conductivity type first semiconductor region for leading a collector electrode. Forming a second semiconductor region of the second conductivity type serving as a base in the first semiconductor layer region, wherein the bipolar element and the field effect element coexist. A method of manufacturing a semiconductor device according to claim.

Operation The following effects are obtained as effects of the first manufacturing method of the present invention.

(1) An opening for the collector is formed in the insulating film formed on the entire surface of the region where the element is to be formed, and the insulating film is left on the base surface, so that the non-single-crystal semiconductor film serving as an extraction electrode of the collector can be formed. The insulating film can prevent intrusion of impurities from the base surface caused by out-diffusion of high-concentration impurities, and can prevent contamination of the base surface. In addition, since impurity contamination on the base surface can be prevented, it is possible to prevent a phenomenon that the junction depth with the emitter formed later in the base becomes out of order, which leads to an increase in the variation of the current amplification factor of the transistor.

(2) Since the base can be formed by a method such as ion implantation using the non-single-crystal semiconductor film itself of the collector as a mask, the influence of dimensional conversion can be prevented, and the base can be formed small, so that the degree of integration of the transistor is increased. be able to.

The effects of the second manufacturing method of the present invention include the following.

(1) By depositing a first non-single-crystal semiconductor film on a first insulating film in a portion where a bipolar element is to be formed and a second insulating film for a gate in a portion where a field effect element is to be formed In addition, it is possible to form a window for a collector for exposing the surface of the single-conductivity semiconductor region of the first conductivity type without contaminating the gate insulating film. Since the second non-single-crystal semiconductor film could be deposited on the crystalline semiconductor film to have a desired thickness, the electric field was obtained by patterning the two-layer non-single-crystal semiconductor film. The gate of the effect transistor and the electrode for extracting the collector can be formed at the same time, and the manufacturing process can be simplified.

(2) Since the electrode formed by the non-single-crystal semiconductor film for the collector and the electrode formed by the non-single-crystal semiconductor film for the gate such as a MOS are used in common, they are used in a normal manufacturing process to reduce the resistance of the gate electrode. The diffusion of phosphorus generated by the reaction of phosphorus oxychloride (POCl ₃ ) into the electrode by the non-single-crystal semiconductor film forms a low-resistance semiconductor region for extracting a deep collector electrode into the semiconductor layer region immediately below the collector electrode. It can be easily formed.

Example (Example 1) FIGS. 1A to 1F are cross-sectional views showing a series of steps for explaining a method of manufacturing an NPN transistor according to a first example of the present invention. As shown in FIG. 1 (a), an N-type buried semiconductor region 102 is formed in a P-type substrate 100 of silicon single crystal having a specific resistance of 1-10 ohm.cm by arsenic ions having a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2. An N-type semiconductor layer 104 having a thickness of about 1.5 μm is formed by epitaxial growth.
The element isolation semiconductor region 108 is formed by boron ion implantation, and the surface of the epitaxial layer 104 is selectively oxidized to about 600 nanometers by the LOCOS method by thermal oxidation to form an element isolation film 114 to form a collector wall. Thin silicon oxide film about 30 nanometers thick
On 111, a resist pattern 150 was opened.

As shown in FIG. 1B, an N-type semiconductor region 120 serving as a collector wall is formed by a phosphorus ion implantation method at a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2 using a resist pattern 150, and a collector window is formed. The oxide film 111 at the position was removed by a normal etching method, and then the resist 150 was removed. Next, polysilicon 136 to be a non-single-crystal semiconductor thin film was deposited to a thickness of about 300 nanometers by a CVD method. In this case, an amorphous silicon thin film may be deposited instead of the polysilicon film 136.

As shown in FIG. 1 (c), after a polysilicon serving as a collector electrode is formed by a normal etching method using a resist pattern so as to be drawn out to the end of a base formation scheduled portion, a resist pattern 152 is further formed. Using the pattern 152 and the polysilicon 136A as a mask, the dose is 1
A P-type semiconductor region 122 serving as a base was formed by a boron ion implantation method of 0 ¹³ -10 ¹⁴ cm ^-2 .

As shown in FIG. 1D, an oxide film 126 was deposited by a CVD method, and a resist pattern 154 for an opening for an emitter was formed.

After forming a contact window for the emitter by a normal etching method using a resist pattern 154 as shown in FIG. 1E, an ion implantation method of arsenic or the like with a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2 is performed. An N-type semiconductor region 124A serving as an N-type emitter was formed.

As shown in FIG. 1 (f), an aluminum electrode 140A for a collector, an aluminum electrode 140B for an emitter, and an aluminum electrode 140C for a base were formed by a usual method.

The oxide film 111 thus formed in the element formation planned region
An opening for the collector is formed by the resist 150, and the oxide film 111 is left on the base surface, so that the impurity from the base surface caused by the out-diffusion of the high concentration impurity from the polysilicon 136 serving as the collector extraction electrode is formed. Can be prevented by the oxide film 111 and contamination of the base surface can be prevented. In addition, since impurity contamination on the base surface can be prevented, it is possible to prevent a phenomenon that the junction depth of the emitter region 124A formed later in the base 122 is out of order, which leads to an increase in the variation of the current amplification factor of the transistor.

Furthermore, according to the above-described method, the base 122 can be formed by a method such as ion implantation using the polysilicon 136A of the collector as a mask, so that an increase in dimension due to pattern conversion in the LOCOS step can be prevented. The transistor can be formed small, and the degree of integration of the transistor can be increased.

Example 2 FIGS. 2 (a) to 2 (f) are cross-sectional views showing a series of steps for explaining a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS element coexist according to a second example of the present invention. .

As shown in FIG. 2 (a), the specific resistance of the silicon single crystal is approximately
An N-type buried semiconductor region 102 is formed on a 10-ohm.cm P-type semiconductor substrate 100 by an ion implantation method of arsenic or the like with a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2 , and an N-type semiconductor having a thickness of about 2 μm is formed by epitaxial growth. A semiconductor layer 104 is formed, a P-type element isolation semiconductor region 108 is formed by ion implantation of boron or the like, and an oxide film 111 serving as a first insulating film and approximately 100 An element isolation film 114 of about 600 nanometers was formed by selective oxidation by the LOCOS method using the nanometer nitride film 112 as a mask.

As shown in FIG. 2 (b), after removing the nitride film 112 and the oxide film 111 in the portion where the MOS element is to be formed, only the portion where the MOS transistor is to be formed is a gate insulating film having a thickness of about 15 nanometers which becomes the second insulating film. Forming a film 115 and forming a first non-single-crystal film by a CVD method;
Was deposited, and a resist pattern 150 was further formed.

As shown in FIG. 2C, the polysilicon film 130 and the oxide film 115 at the collector window forming position are removed by an etching method using the resist pattern 150, and the resist pattern is further removed.
N-type semiconductor region 12 serving as a collector wall by ion implantation of phosphorus or the like at a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2 using 150
After forming 0, the resist 150 is removed. Then CV
A polysilicon 132 having a thickness of about 100 to 300 nanometers to be a second non-single-crystal film was deposited by the method D. This second
It is also possible to employ amorphous silicon as the non-single-crystal film. Phosphorus oxychloride (POC), which is used in normal manufacturing processes to reduce the resistance of the gate electrode
l ₃₎ forming a low resistance semiconductor region 124B for deep collector contact to the semiconductor layer region 120 serving as the collector just below the collector electrode by diffusion into the polysilicon electrode of the generated phosphorus by reaction.

As shown in FIG. 2 (d), the polysilicon film 130, 132 having a two-layer structure is etched by a normal etching method using a resist pattern, so that polysilicon serving as a polysilicon extraction electrode for a collector of the bipolar transistor is formed. The patterns 130A and 132A and the polysilicon patterns 130B and 132B serving as the gates of the MOS transistors are formed, and the P-type semiconductor region 122P serving as the base of the bipolar transistor and the P-type semiconductor regions 128A serving as the source and drain of the P-channel MOS transistor are formed. 128B was formed by ion implantation of boron or the like using a resist pattern (not shown) as a mask, and an oxide film 126 was deposited on the entire surface by CVD.

As shown in FIG. 2 (e), after forming a window of an opening for an emitter by a normal etching method using a resist pattern, a polysilicon 138 is deposited by a CVD method to form a polysilicon electrode at the emitter. Then, a resist pattern 158 was formed. It is also possible to employ an amorphous silicon film as the semiconductor thin film for the emitter.

As shown in FIG. 2 (f), using the resist pattern 158 as a mask, a polysilicon electrode pattern 138A for an emitter is formed by a normal etching method, and this is implanted into the polysilicon electrode 138A by an ion implantation method at a dose of 10 ¹⁵ -10. ¹⁶ cm
^-2 arsenic is implanted, and an N-type semiconductor region 124A serving as an emitter is further formed by thermal diffusion, and further, an aluminum electrode 140A for a collector, an electrode 140B for an emitter, an electrode 140C for a base, and an electrode 140D for a source are formed by a usual method. Then, a drain electrode 140E was formed.

By forming an opening for the collector in the oxide film 111 formed on the entire surface of the region where the element is to be formed as described above and leaving the oxide film 111 on the base surface, the height from the polysilicon 120 serving as a collector lead-out electrode is increased. The infiltration of impurities from the base surface caused by the out-diffusion of the concentration impurities can be prevented by the oxide film 111, and contamination of the base surface can be prevented. In addition, since impurity contamination on the base surface can be prevented, it is possible to prevent a phenomenon that the junction depth of the emitter region 124A formed later in the base 122 is out of order, which leads to an increase in the variation of the current amplification factor of the transistor.

Further, since the polysilicon electrode 132A of the collector and the polysilicon electrode 132B for the gate such as a MOS are shared, phosphorus oxychloride (POCl ₃ ) used in a normal manufacturing process for lowering the resistance of the gate electrode is used. The low-resistance semiconductor region 124B for deep extraction of the collector electrode could be easily formed in the semiconductor layer region directly below the collector electrode by diffusion of the phosphorus generated by the reaction of (2) into the polysilicon electrode.

(Embodiment 3) FIGS. 3 (a) to 3 (f) are a series of process cross-sectional views for explaining a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS element coexist according to a third embodiment of the present invention. . As shown in FIG. 3A, an N-type buried semiconductor region 102 is formed on a P-type semiconductor substrate 100 of silicon single crystal having a specific resistance of about 10 ohm.cm by arsenic having a dose of 10 ¹⁵ -10 ¹⁶ cm ^-2 . An N-type semiconductor layer 104 having a thickness of about 2 μm is formed by epitaxial growth, and a P-type semiconductor region 106 serving as a well region is formed at a dose of 10 ¹¹ -10 ¹³
formed by ion implantation, such as boron cm ^-2, the P-type isolation region 108 formed by ion implantation such as boron, about the epitaxial layer 104 surface as a buffer 5
By selectively oxidizing by a LOCOS method using the 0 nm-thick oxide film pattern 111 and the 100 nm-thick nitride film pattern 112 as a mask, a film 114 for device isolation of about 600 nm was formed.

As shown in FIG. 3 (b), after removing the nitride film 112 and the oxide film 111 in the portion where the MOS element is to be formed, a gate oxide film 115 of about 10 nanometers serving as the second insulating film only in the portion where the MOS transistor is to be formed. After depositing a polysilicon 130 having a thickness of about 30 nanometers to be a first non-single-crystal film by a CVD method, a resist pattern 150 was formed.

As shown in FIG. 3C, after removing the polysilicon film 130 and the oxide film 111 at the position where the window for the collector opening is to be formed by the etching method using the resist pattern 150, the resist pattern 150 is removed, and the CVD is performed. A polysilicon film 132 having a thickness of about 250 nanometers serving as a second non-single-crystal semiconductor film is deposited by a method, and POCl ₃ is deposited on the silicon film 132.
The N-type semiconductor region (collector wall) 120 having a depth of about 1 micron for extracting a collector was formed by diffusing phosphorus from the substrate. This diffusion of phosphorus simultaneously reduced the sheet resistance of the polysilicon film 132 to about 30 ohm / b.

As shown in FIG. 3 (d), at the same time as the gate polysilicon patterns 130B and 132B of the MOS transistor, the polysilicon patterns 130A and 132A serving as collector electrodes are drawn out to the end of the base formation planned portion using a resist pattern. Formed by the etching method of
A P-type semiconductor region 122 serving as a base was formed in the oxide film 111 by boron ion implantation using the second and polysilicon 132A and 130A as masks.

As shown in FIG. 3E, an N-type semiconductor region 124A serving as an emitter of a bipolar transistor is formed by ion implantation of arsenic at a dose of 10 ¹⁵ -10 ¹⁶ cm ^{-2 using} the resist pattern 154 and the oxide film 114 as a mask. And 124C and 124D serving as the source and drain of the N-channel MOS transistor were simultaneously formed.

As shown in FIG. 3 (f), after removing the resist pattern 154, an oxide film 126 is deposited by a CVD method, and then a window for an emitter opening and a base opening are formed by a normal etching method using a resist pattern. After forming a window, a window for a source opening, and a window for a drain opening, by a normal method, an aluminum metal electrode 140A for a collector, a metal electrode 140B for an emitter, a metal electrode 140C for a base, and a metal electrode for a source are formed. 140D and a drain metal electrode 140E were formed.

As described above, the first polysilicon film 130 is deposited on the first oxide film 111 in the portion where the collector of the bipolar transistor is to be formed and the second oxide film 115 for the gate where the field effect transistor is to be formed. In addition, it is possible to form a window of an opening for a collector without contaminating the gate oxide film 115, and further, a second thickness is formed on the opened first polysilicon film 130 so as to have a desired thickness. Since the polysilicon film 132 could be deposited, by patterning the polysilicon film having the two-layer structure,
The gates 130B and 132B of the field effect transistor and the electrodes 130A and 132A for extracting the collector can be formed at the same time.

In addition, since the polysilicon electrode 132A of the collector and the polysilicon electrode 132B for the gate of the MOS are used in common, phosphorus oxychloride (POCl ₃ ) used in a normal manufacturing process for lowering the resistance of the gate electrode is used. By diffusion of phosphorus generated by the reaction into the polysilicon electrode, a low-resistance N-type semiconductor region 120 for extracting a deep collector polysilicon electrode could be easily formed in the N-type region serving as a collector immediately below the collector electrode.

Furthermore, according to the above-described method, the base 122 can be formed by a method such as ion implantation using the polysilicon 132A of the collector as a mask, so that an increase in dimensions due to pattern conversion in the LOCOS step can be prevented. The transistor can be formed small, and the degree of integration of the transistor can be increased.

According to the present invention, it is possible to realize a method of manufacturing a bipolar transistor suitable for combining elements, and furthermore, a problem in a manufacturing technology of a semiconductor device in which a bipolar element and a field-effect element such as CMOS coexist. It is possible to provide an excellent manufacturing method that solves the above points.

[Brief description of the drawings]

FIG. 1 shows a bipolar NP according to a first embodiment of the present invention.
FIG. 2 is a sectional view showing a series of manufacturing methods of an N-transistor; FIG. 2 is a cross-sectional view showing a series of manufacturing methods of a semiconductor device in which a bipolar transistor and a MOS element coexist according to a second embodiment of the present invention; FIG. 4 is a series of sectional views showing a series of steps of a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS element coexist according to a third embodiment of the present invention. FIG.
It is a process sectional view showing a series of manufacturing methods of a semiconductor device with which an element coexists. 100: P-type semiconductor single crystal substrate, 102: N-type buried semiconductor region, 104: N-type semiconductor layer, 108, 128 ... P ⁺ -type semiconductor region, 110, 111, 114, 115, 126, 151 ... silicon oxide film, 112 ... silicon nitride film , 120, 124 ... N ⁺ type semiconductor region, 122 ... P type semiconductor region, 130, 132, 134, 136, 138 ...
Polycrystalline silicon film, 140 ... Metal electrode, 150, 152, 154, 15
6,158 Resist.

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁶ , DB name) H01L 21/822 H01L 21/822-21/8228 H01L 21/8232 H01L 27/06 H01L 27/08 H01L 27 / 082

Claims (3)

(57) [Claims] A step of forming an insulating film on a first-conductivity-type single-crystal semiconductor layer region to be a collector; a step of forming an opening for the collector in the insulating film; and a step of forming the opening. Depositing a non-single-crystal semiconductor film over the insulating film and the opening, and forming a non-single-crystal semiconductor film pattern for extracting a collector by patterning the non-single-crystal semiconductor film toward a base formation scheduled portion side Forming a first conductive type first semiconductor region for extracting a collector electrode by introducing a first conductive type impurity into the semiconductor layer region through the collector opening; A step of selectively forming a second semiconductor region of the second conductivity type serving as a base in the semiconductor layer region using the non-single-crystal semiconductor film pattern drawn to the base formation scheduled portion side as a mask; With the door, a method of manufacturing a semiconductor device characterized by separating the first semiconductor region and the underlying second semiconductor region for the collector electrode lead-out. 2. A step of forming a first insulating film on a first conductivity type single crystal semiconductor layer region, and after removing the first insulating film on a field effect transistor forming portion, Forming a second insulating film for a gate on a portion where a field effect transistor is to be formed, and depositing a first non-single-crystal semiconductor film on the first insulating film and the second insulating film; Forming an opening for a collector in the first non-single-crystal semiconductor film, removing the first insulating film in the opening for the collector, and forming a first opening in the opening for the collector. Depositing a second non-single-crystal semiconductor film over the non-single-crystal semiconductor film and over the collector opening from which the first insulating film has been removed; and removing the first and second non-single-crystal semiconductor films. By patterning, the non-single-crystal semiconductor film Forming a non-single-crystal semiconductor film pattern for the ground electrode and the gate electrode, and introducing a first conductive type impurity into the semiconductor layer region through the collector opening, thereby forming a first conductive type for extracting the collector electrode. Forming a first semiconductor region, and then forming a second semiconductor region of a second conductivity type serving as a base in the first semiconductor layer region, wherein a bipolar element and a field effect element are provided. A method for manufacturing a semiconductor device, wherein 3. A non-single-crystal semiconductor film pattern for extracting a collector is formed by patterning the first and second non-single-crystal semiconductor films into a shape to be drawn toward a base formation scheduled portion side. Using the pattern as a mask, a third of the second conductivity type serving as a base in the first semiconductor layer region
3. The method for manufacturing a semiconductor device according to claim 2, wherein said semiconductor region is selectively formed.