JPH03127860A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the surface of the base of a semiconductor device from being contaminated by forming an opening for collector through an insulating film formed on the entire surface of an area proposed for an element and leav ing the insulating film on the surface of the base. CONSTITUTION:An opening for collector is formed through an oxide film 111 formed on an area proposed for an element by using a resist 150 and the film 111 is left on the surface of a base. Accordingly, invasion of impurities produced on the surface of the base by the out-diffusion of high-concentration impurities from the polysilicon 136A which forms a collector lead-out electrode can be blocked by this oxide film 111. Therefore, the base surface can be prevented from being contaminated and, in addition, occurrence of such a phenomenon that the fluctuation of the current amplification factor of a transistor increases due to the wrong junction depth of an emitter area 124A formed later in the base 122 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is in the field of semiconductor integrated circuit devices.
The present invention relates to an improvement in a method for manufacturing a semiconductor device (MO3, etc.), and further relates to a method for manufacturing a semiconductor device with a composite structure in which a bipolar transistor and an MO3 element coexist on the same chip.

Conventional technology In recent years, in the field of integrated circuit devices, composite devices have been realized that combine bipolar elements, MO3 elements, etc., which were previously used singly, and this has led to higher interconnection and higher performance. As an example of a method for manufacturing a silicon semiconductor composite element, the development of manufacturing technology and its optimization to realize a silicon semiconductor device have become important. A method of manufacturing a semiconductor device as shown in the figure can be considered. The background of the prior art will be described while briefly explaining the method for manufacturing a composite device using FIG. 4.

As shown in FIG. 4(a), an N-type buried semiconductor region 102 is formed on a single-crystal P-type substrate 100 by ion implantation and by epitaxial growth.
After forming the type single crystal semiconductor layer 104, a P type element isolation layer 108 is formed by implanting boron ions and then heat treatment, and by thermally oxidizing the surface of the epitaxial layer 104, an oxide film 110 for buffering is formed. After forming a nitride film 112, a thermal oxide film is selectively grown using a selective oxidation method (LOCO3 method) to form an element isolation film 114.

As shown in FIG. 4(b), a nitride film 112 and an oxide film 110
After removing the gate oxide film 115, it is oxidized again to form a gate oxide film 115, and an N-type semiconductor region 1 for the collector all is formed by ion implantation of phosphorus using the resist pattern 156 as a mask.
form 18.

As shown in FIG. 4(c), after removing the resist 156, polysilicon is deposited by the CVD method to form a polysilicon pattern 13 that will become the gate part of the MOS transistor.
3 and further etch the oxide film +15 (this gate oxide film does not necessarily need to be removed at this point), and then ionize the base layer 122 and the source region 128A and drain region 128B, which are P-type semiconductor regions, respectively. An oxide film 126 is deposited by an implantation method, an oxide film 126 is deposited by a CVD method, openings for a collector window and an emitter window are selectively formed by an etching method, and polysilicon 134 as a polycrystalline semiconductor film is deposited by a CVD method.

As shown in FIG. 4(d), a polysilicon electrode pattern 134A for the collector and a polysilicon electrode pattern 134B for the emitter of the bipolar transistor are formed by an etching method using a resist pattern, and then a metal electrode 140A for the collector and a metal electrode 140A for the emitter are formed. Metal electrode 1
40B, a base metal electrode 140C, a source metal electrode 140D, and a drain metal electrode 140E are formed.

In this way, a P-channel MO3 element and a vertical bipolar transistor are formed together.

Problems to be Solved by the Invention In the method of manufacturing a bipolar element or a semiconductor device in which a bipolar element and an MO3 element coexist by the conventional process shown in FIG. 4, the following problems can be raised.

(1) As shown in Figure 4(b), the resist pattern 156 is used to form the N-type semiconductor region 118 for the collector all. Therefore, contamination of the gate oxide film by the resist is likely to occur. This contamination causes the threshold voltage of the MOS transistor (
In addition, VT instability tends to occur in terms of reliability, which is a problem. In addition, the gate oxide film 115
Before forming the gate oxide film 115 to prevent contamination of
Another possible method is to form the N-type semiconductor region 118.During the oxidation heat treatment to form the gate oxide film 115, the surface of the N-type semiconductor region 118 is removed from the active transistor region such as a MOS or the activation of a coexisting bipolar transistor. Out-diffusion of N-type impurities into the transistor region (evaporation of high-concentration impurities during high-temperature heat treatment)
Therefore, there is a drawback that, for example, +z Mos channel deterioration or contamination of the base surface by N-type impurities is likely to occur.

(2) Also, as shown in FIG. 4(C), after the polysilicon 134 is deposited by the CVD method, high concentration impurities from the N-type region +18, which will become the collector region, are diffused through the polysilicon film 134. By doing this, N such as phosphorus is removed from the base surface through the emitter aperture.
Intrusion of type impurities L) The number of contaminations on the surface of the type base. The depth of the junction of the N-type semiconductor region that will become the emitter, which is later formed in the base, is out of order. There is a problem that it may lead to increase.

(3) Furthermore, the base end on the side closer to the collector is t,
Positioned by o cos process △10
Number of COS Processes Due to so-called bird's beak pattern conversion, the dimension of electrical element isolation between the collector and base becomes larger than necessary. However, it is necessary to design the device in consideration of the reduction in the base area, which leads to an increase in the size of the bipolar transistor, which is a problem in achieving high integration.The present invention solves these problems. Alternatively, the present invention provides a new method for manufacturing a semiconductor device in which bipolar elements and MOS elements coexist.

Means for Solving the Problem In order to solve this problem, a first manufacturing method of the present invention (a step of forming an insulating film on a single-crystalline semiconductor layer region of a first conductivity type, which becomes a collector); a step of forming an opening for a collector in an insulating film; a step of depositing a non-single crystal semiconductor film on the insulating film in which the opening is formed and the opening; and a step of depositing the non-single crystal semiconductor film on the side where a base is to be formed. A step of forming a non-single-crystal semiconductor film pattern for drawing out the collector by converting the pattern into a drawing shape, and a step of forming a collector electrode by introducing an impurity of a first conductivity type into the semiconductor layer region through the opening for the collector. A step of forming a first semiconductor region of a first conductivity type for extraction, and forming a base in the semiconductor layer region using the non-single crystal semiconductor film pattern drawn out to the side where the base is to be formed as a mask. selectively forming a second semiconductor region of a second conductivity type, the first semiconductor region for leading out the collector electrode and the second semiconductor region serving as a base are separated from each other. This is a method for manufacturing a semiconductor device.

A second manufacturing method of the present invention includes a step of forming a first insulating film on a first conductivity type single crystal semiconductor layer region which becomes a collector, and a step of forming a first insulating film on a portion where a field effect transistor is to be formed. After removing the first insulating film, forming a second insulating film for a gate on the area where the field effect transistor is to be formed, and forming a first insulating film on the first insulating film and the second insulating film. a step of depositing a non-single crystal semiconductor film, and forming a collector opening in the first non-single crystal semiconductor film;
a step of removing the first insulating film within the collector opening; and a step of removing the first non-single crystal semiconductor film from which the collector opening is formed and the collector from which the first insulating film is removed. A step of depositing a second non-single-crystalline semiconductor film on the opening, and patterning the non-single-crystalline semiconductor film of No. 110- and Gai 2 to form a non-single-crystalline semiconductor film pattern for collector extraction and a gate electrode. a step of forming a non-single-crystal semiconductor film pattern for a collector electrode, and introducing a first conductivity type impurity into the semiconductor layer region through the collector opening, thereby forming a first conductivity type first impurity for extracting the collector electrode. A bipolar element and a field effect element coexist. A method of manufacturing a semiconductor device is characterized in that:

Effects The following effects can be mentioned as effects of the first manufacturing method of the present invention.

(1) By forming an opening for the collector in the insulating film formed on the entire surface of the area where the element is to be formed and leaving this insulating film on the base surface, a This insulating film can prevent impurities from entering from the base surface caused by out-diffusion of highly concentrated impurities, thereby preventing contamination of the base surface. In addition, since impurity contamination on the base surface can be prevented, it is possible to prevent the phenomenon that the depth of the junction with the emitter later formed in the base is out of order, leading to an increase in the variation in the current amplification factor of the transistor.

(2) Since the base can be formed by methods such as ion implantation using the non-single-crystal semiconductor film of the collector itself as a mask, the effects of dimensional conversion can be prevented and the base can be made smaller, increasing the degree of integration of the transistor. be able to.

The following effects can be mentioned as effects of the second manufacturing method of the present invention.

(1) By depositing the first non-single crystal semiconductor film on the first insulating film in the part where the collector of the bipolar element is planned to be formed and the second insulating film for the gate in the part where the field effect element is planned to be formed. , it becomes possible to form a window for the collector opening that exposes the surface of the single-crystalline semiconductor region of the first conductivity type without contaminating the gate insulating film. Since we were able to deposit the second non-single-crystalline semiconductor film to the desired thickness on the non-single-crystalline semiconductor film,
By patterning this two-layer non-single-crystalline semiconductor film, it is possible to simultaneously form the gate and collector lead-out electrode of a field effect transistor.
The manufacturing process can be simplified.

(2> Electrode and MOS made of non-single crystal semiconductor film of collector
Since the electrodes are made of non-single-crystal semiconductor films for gates, they are formed by the reaction of phosphorous oxychloride (]]OCI*), which is used in the normal manufacturing process to reduce the resistance of gate electrodes. By diffusing the phosphorus into the electrode through the non-single-crystal semiconductor film, a deep low-resistance semiconductor region for leading out the collector electrode can be easily formed in the semiconductor layer region which will become the collector directly under the collector electrode.

Embodiment (Example 1) FIGS. 1(a) to 1(f) are a series of process cross-sectional views illustrating a method for manufacturing an NPN transistor according to a first embodiment of the present invention. As shown in FIG. 1(a), the specific resistance of silicon single crystal is 1-10 ohm.

An N-type buried semiconductor region 1 in a P-type substrate 100 of cm
02 is formed by an arsenic ion implantation method at a dose of 10''-10''cm-'', and an N-type semiconductor layer +04 with a thickness of about 1.5 microns is formed by epitaxial growth.The LP-type element isolation semiconductor region 108 is formed by boron ions. The device isolation film 114 is formed by selectively oxidizing the surface of the epitaxial layer 104 to a thickness of approximately 600 nanometers using the LOCO3 method using thermal oxidation. As shown in FIG. 1(b) in which a resist pattern 150 is opened on the oxide film 111, N, which becomes the collector all, is implanted by ion implantation of phosphorus at a dose of 10"-10"cm-" using the resist pattern 150. oxide film 11 at the collector window forming position.
1 was removed by a normal etching method, and then the resist 150 was removed.Next, polysilicon +36, which would become a non-single crystal semiconductor thin film, was deposited to a thickness of about 300 nanometers by the CVD method.
In this case, an amorphous silicon thin film may be deposited instead of the polysilicon film 136.

As shown in FIG. 1(c), after forming the polysilicon which will become the collector electrode by a normal etching method using a resist pattern so as to bring it out to the end of the part where the base is to be formed, a resist pattern 152 is further formed in the shape of this resist pattern. 152 and the P-type semiconductor region 122 that will become the base by boron ion implantation at a dose IQ10 of 1914 cm-2 using acceleration energy that passes through the oxide film Ill using the polysilicon 136A as a mask.
As shown in FIG. 1(d), an oxide film 12 is formed by the CVD method.
6 was deposited, and a resist pattern 154 for an opening for the emitter was further formed.As shown in FIG. 1
0165- An N-type semiconductor region 124A, which will become an N-type emitter, is formed by ion implantation of 10 cm of arsenic or the like. As shown in FIG. 1(f), an aluminum electrode for the collector is formed by a normal method. 140A, an aluminum electrode 140B for an emitter, and an aluminum electrode 140C for a base are formed in this way.
An opening for the collector is formed using resist 150,
By leaving this oxide film 111 on the base surface, the oxide film 111 can prevent impurities from penetrating from the base surface caused by out-diffusion of high concentration impurities from the polysilicon 136, which is the extractor electrode of the collector. It was possible to prevent surface contamination.It also prevented impurity contamination on the base surface.
6-Furthermore, according to the two methods, the collector poly Since the base 122 can be formed by a method such as ion implantation using silicon 136A as a mask, t, a co
Since the increase in dimensions due to pattern conversion in the s process can be prevented, the base dimensions can be made smaller and the degree of integration of the transistor can be increased by 1° (Example 2). FIG. 3 is a series of process cross-sectional views illustrating a method of manufacturing a semiconductor device in which a bipolar transistor and an MO3 element coexist according to a second embodiment of the present invention.

As shown in Figure 2(a), the resistivity of silicon single crystal is 1.
An N-type buried semiconductor region 102 is formed on a P-type semiconductor substrate 100 of 0 ohmocm at a dose of 10110l510.
An N-type semiconductor layer 104 with a thickness of about 2 microns is formed by epitaxial growth. An LP-type element isolation semiconductor region 108 is formed by ion implantation of boron or the like, and the surface of the epitaxial layer 104 is selected. The oxide film Ill, which becomes the first insulating film and the nitride film 1 with a thickness of approximately 100 nanometers, is
By selectively oxidizing by the LOCO3 method using 12 as a mask, an element isolation film 11 of about 600 nanometers is formed.
As shown in FIG. 2(b), after removing the nitride film 112 and the oxide film 111 in the area where the MOS transistor is to be formed, a second insulating film is formed only in the area where the MOS transistor is to be formed. A gate oxide film 115 with a thickness of 15 nanometers is formed. Polysilicon 130 with a thickness of about 10-50 nanometers is deposited as the first non-single crystal film by CVD, and a resist pattern 150 is further formed. As shown in (c), the polysilicon film 130 and oxide film 115 at the collector window formation position are removed using a resist pattern 15.
0"-10"cm-
After forming an N-type semiconductor region 120 which becomes a collector all by ion implantation of phosphorus or the like, resist 1 is formed.
Remove 50. Thereafter, polysilicon 132 with a thickness of about 10 (1-300 nanometers), which will become the second non-single crystal film, is deposited by CVD. It is also possible to use amorphous silicon as this second non-single crystal film. In addition, the direct F of the collector electrode is reduced by the diffusion of phosphorus produced by the reaction of phosphorus oxychloride (POCI-), which is used in the normal manufacturing process to reduce the resistance of the gate electrode, into the polysilicon electrode. Semiconductor layer region 1 that becomes the collector
Low resistance semiconductor region 1 for leading out the deep collector electrode at 20
24I3 is formed.

As shown in FIG. 2(d), the CS two-layer polysilicon films 130 and 132 are etched by a normal etching method using a resist pattern to form polysilicon lead electrodes for the collector of the bipolar transistor. Polysilicon patterns 130A and 132A and polysilicon pattern 130B that becomes the gate of the MOS transistor
・P-type semiconductor region 122P and P-channel MO3 which form 132B and become the base of the bipolar transistor)
P-type 9- semiconductor regions 128A and 128B, which will become the source and drain of the transistor, are implanted into 5I2. Further, an oxide film 126 is deposited on the entire surface by the CVD method, and an opening 11 window for the emitter is formed by a normal etching method using a resist pattern as shown in FIG. 2(e). Deposit polysilicon 138 by
A resist pattern 158 was formed to form the emitter polysilicon electrode. It is also possible to use an amorphous silicon film as the semiconductor thin film for the emitter.

As shown in FIG. 2(f), an emitter polysilicon electrode pattern 138A is formed using the resist pattern 158 as a mask by a normal etching method.
016-10 "cm-2" of arsenic is implanted, and then an N-type semiconductor region 124A that will become an emitter is formed by thermal diffusion, and then an aluminum electrode for collector - 40A, emitter electrode 140 is formed by a normal method. B. An opening for the collector is formed in the oxide film II+ formed on the entire surface of the region where the element is to be formed, in which the base electrode 140C, the source electrode 140D, and the drain electrode 140E are formed. By leaving the film 111, the intrusion of impurities from the base surface caused by out-diffusion of high-concentration impurities from the polysilicon 120, which becomes the extractor electrode of the collector, can be prevented by this oxide film.
Contamination of the base surface can be prevented. Also, since impurity contamination of the base surface can be prevented, the depth of the junction of the emitter region 124A, which will be formed later in the base 122, will be incorrect, leading to an increase in the variation in the current amplification factor of the transistor. In addition, since the polysilicon electrode 132A of the collector and the polysilicon electrode 132B for the gate of MOS etc. are shared, this phenomenon is used in the normal manufacturing process to reduce the resistance of the gate electrode. By diffusing phosphorus generated by the reaction of phosphorus oxychloride (POCI3) into the polysilicon electrode, a low-resistance semiconductor region 124B for leading out the collector electrode deep can be easily formed in the semiconductor layer region that will become the collector directly under the collector electrode. (Embodiment 3) 31i(a) to 31i(f) are a series of process cross-sectional views illustrating a method for manufacturing a semiconductor device in which a bipolar transistor and a MOS element coexist according to a third embodiment of the present invention. . As shown in FIG. 3(a), the resistivity of silicon single crystal is 10 ohm.

An N-type buried semiconductor region 102 is formed on a P-type semiconductor substrate 100 of Cm at a dose of 10'! An N-type semiconductor layer 104 with a thickness of approximately 2 microns is formed by epitaxial growth, and a P-type semiconductor region 106 that will become a well region is formed at a dose of 10''-10''c. The LP type element isolation region 108 is formed by ion implantation of boron or the like, and an oxide film pattern 111 of approximately 50 nanometers is formed on the surface of the epitaxial layer 104 to serve as a buffer. Approximately 100 nanometer nitride film pattern 11
As shown in FIG. 3(b), an oxide film 114 for device isolation of about 600 nanometers was formed by selectively oxidizing the nitride film 1 by the LOCO3 method using nitride film 1 as a mask.
After removing the oxide film 111 in the MO8 element formation area, a gate oxide film 115 of about 10 nanometers, which will become the second insulating film, is formed only in the area where the MOS transistor is to be formed. After depositing polysilicon 130 with a thickness of about 30 nanometers, which will be a non-single-crystalline film, a resist pattern 150 is formed, and as shown in FIG. and the oxide film 111 removed by an etching method using a resist pattern 150.
This resist pattern 150 is removed, and a polysilicon film 132 with a thickness of approximately 250 nanometers, which will become a second non-single crystal semiconductor film, is deposited by CVD, and phosphorus is diffused into this polysilicon film +32 using POCl3. Approximately 1 micron deep N for collector drawer by Numaichi
A type semiconductor region (collector all) 120 is formed.
, Due to the diffusion of phosphorus, the polysilicon film 132
At the same time as the gate polysilicon patterns 130B and 13213 of the MOS transistor, the sheet resistance of the MOS transistor can be reduced to about 30 ohm/o as shown in Fig. 3(d).
Polysilicon batan +30A, 132 as collector electrode
A is formed into a shape that extends to the end of the part where the base is to be formed by a normal etching method using a resist pattern, and then resist 152 and polysilicon 132A-130A are formed.
Using the resist pattern 154 and the oxide film 1]4 as a mask, a P-type semiconductor region 122 as a base was formed by boron ion implantation through the oxide film 111 as shown in FIG. 3(e). Amount lO-10”c
m-2 arsenic ion implantation method to form an N-type semiconductor region 124A that will become the emitter of the bipolar transistor;
124 C serves as the input and drain of the N-channel MOS transistor.

As shown in Figure 3(f), after removing the resist pattern 154, depositing M126 oxide by CVD method, and then etching the base of the opening for the emitter by the usual etching method using the resist pattern. After forming the window for the source opening and the drain opening, the collector aluminum metal electrode 140 A is formed using the usual method.
, the metal electrode 140B for the emitter, the metal electrode 140C for the base, the metal electrode 140D for the source, and the metal electrode 140E for the drain. A first oxide film 115 is formed on the second oxide film 115 for the gate in the area where the field effect transistor is to be formed.
By depositing the first polysilicon film 130, it becomes possible to form a window for the collector opening without contaminating the gate oxide film 115, and furthermore, a desired amount of polysilicon film 130 can be deposited on the opened first polysilicon film 130. Since the second polysilicon film 132 has been deposited to a thickness of , the gate 130B of the field effect transistor is
132B and collector extraction electrodes 130A, 132
It is now possible to form the collector polysilicon electrode 132A and the MO at the same time.
Since the polysilicon electrode 132B for the gate of S is shared, the polysilicon electrode is made of phosphorus produced by the reaction of phosphorus oxychloride (POCl3), which is used in the normal manufacturing process to reduce the resistance of the gate electrode. By diffusion into the collector electrode, a low-resistance N-type semiconductor region 12D for drawing out the deep collector polysilicon electrode could be easily formed in the N-type region that will become the collector directly under the collector electrode. Since the base 122 can be formed by a method such as ion implantation using a mask as a mask, it is possible to prevent the size from increasing due to pattern conversion in the LOCO3 process. Can you give it to me? .

Effects of the Invention By the means of the present invention, a method for manufacturing bipolar transistors suitable for compounding elements has been realized, and furthermore, problems in the manufacturing technology of semiconductor devices in which bipolar elements and field effect elements such as CMO8 coexist can be realized. We can provide an excellent manufacturing method that solves the problem.

[Brief explanation of the drawing]

FIG. 1 shows a bipolar N according to a first embodiment of the present invention.
Figure 2 is a cross section showing a series of manufacturing methods for a transistor (PN). Figure 2 is a cross section showing a series of manufacturing methods for a semiconductor device in which a bipolar transistor and an MO8 element coexist, which is a second embodiment of the present invention. 4 is a series of process cross-sectional hand-drawn drawings showing a series of steps for manufacturing a semiconductor device in which a bipolar transistor and an MO8 element coexist, which is a third embodiment of the present invention. FIG. 3 is a process cross-sectional view showing a series of manufacturing methods for a semiconductor device. - Should 100...P-type semiconductor single crystal substrate, 102...N-type embedded semiconductor tilted plate 104...N-type semiconductor screen 108
, 128...P+ type semiconductor region 110.111.1
14.115.126.151...Silicon oxide II
I 112...Silicon nitride! 120,124
...N゛-type semiconductor region 122...P-type semiconductor region 1
30,132,134.136.138...Polycrystalline silicon WL140...Metal type &, 150.152.1
54.156.158...Resist.

Claims (3)

[Claims] (1) A step of forming an insulating film on a first conductivity type single-crystalline semiconductor layer region that will become a collector, a step of forming an opening for the collector in the insulating film, and an insulating film in which the opening is formed. and forming a non-single-crystalline semiconductor film pattern for collector extraction by depositing a non-single-crystalline semiconductor film on the opening, and patterning the non-single-crystalline semiconductor film in a shape that draws it out toward a portion where a base is to be formed. process and
forming a first semiconductor region of a first conductivity type for extracting a collector electrode by introducing an impurity of a first conductivity type into the semiconductor layer region through the collector opening; and a step of forming a first semiconductor region of a first conductivity type for leading out a collector electrode; selectively forming a second semiconductor region of a second conductivity type as a base in the semiconductor layer region using the non-single crystal semiconductor film pattern drawn out to the side as a mask, for drawing out the collector electrode. A method for manufacturing a semiconductor device, comprising separating a first semiconductor region and a second semiconductor region serving as a base. (2) forming a first insulating film on a first conductivity type single-crystalline semiconductor layer region that will become a collector; and removing the first insulating film on a portion where a field effect transistor is to be formed; a step of forming a second insulating film for a gate on the area where the field effect transistor is to be formed; and a step of depositing a first non-single crystal semiconductor film on the first insulating film and the second insulating film. forming a collector opening in the first non-single crystal semiconductor film and removing the first insulating film in the collector opening; depositing a second non-single-crystalline semiconductor film on the non-single-crystalline semiconductor film and on the collector opening from which the first insulating film has been removed; forming a non-single-crystal semiconductor film pattern for collector extraction and a non-single-crystal semiconductor film pattern for a gate electrode by patterning, and injecting impurities of a first conductivity type into the semiconductor layer region through the collector opening. a step of forming a first semiconductor region of a first conductivity type for extracting a collector electrode by introducing a second semiconductor region of a second conductivity type to serve as a base in the first semiconductor layer region; 1. A method for manufacturing a semiconductor device, comprising a step of forming a semiconductor device, wherein a bipolar element and a field effect element coexist. (3) A non-single-crystal semiconductor film pattern for collector extraction is formed by patterning the first and second non-single-crystal semiconductor films in a shape that draws them out toward the portion where the base is to be formed, and this non-single-crystal semiconductor film pattern The first mask is
3. The method of manufacturing a semiconductor device according to claim 2, wherein a third semiconductor region of the second conductivity type serving as a base is selectively formed in the semiconductor layer region.