JPS58158967A - Silicon thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high performance silicon thin film transistors with low idle voltage and high transconductance.

Conventionally, silicon thin film transistors on an amorphous insulating substrate have been produced by using an amorphous or polycrystalline silicon thin film deposited directly on an amorphous insulating substrate as a semiconductor thin film, and by thermal oxidation, sputtering, or OVN method. A silicon oxide thin film was used as the gate insulating film. Energy band diagram for a structure in which a silicon thin film is directly deposited on an amorphous insulating substrate! Shown in Figure 12. Here, 1 is a gate electrode region, 2 is a silicon oxide thin film,
3 is a silicon fII expansion region, and 4 is an amorphous insulating substrate. In this structure, there are many interface states at the interface between the silicon thin film 3 and the substrate 4, and the silicon thin Ml! I area 3 and substrate 4
At the interface, the band of the silicon thin layer region is influenced by the interface state and the phenomenon in which mobile electrons are created, the so-called back channel effect, increases the threshold voltage of the thin film silicon transistor, and the source This has the disadvantage that leakage current between the drains increases. Furthermore, the breakdown voltage of the thin film transistor decreases due to deterioration of the interface characteristics between the silicon thin film and the substrate. Furthermore, in amorphous silicon or polycrystalline silicon on an amorphous insulating substrate, a decrease in carrier mobility is observed due to poor crystallization, and there is a drawback that the mutual conductance of a thin film transistor cannot be increased.

Furthermore, when the silicon oxide thin film 2 is used as the gate film, an inversion region is formed at the interface between the silicon thin film region 3 and the silicon oxide thin JII 2 due to the influence of mobile cations in the silicon oxide thin film 2, and the thin film transistor The disadvantage is that the threshold voltage of

In order to eliminate these drawbacks, the present invention interposes Zn8@jl between the silicon thin film and the amorphous insulating substrate and uses Ta, O@ thin film for the gate insulating film, thereby producing high-performance silicon. 111JIi) The purpose is to realize a transistor.

In order to achieve the above object, the present invention has a structure in which a Zn8 thin film is interposed between a silicon thin film and an amorphous insulating substrate, in which a silicon thin film is used as a semiconductor thin film and a Ta, O, thin film is used as a gate insulating film. The gist of the invention is a silicon thin film transistor characterized in that it is used.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 2 shows an embodiment of the present invention, in which 5 is an amorphous insulating substrate, 1lFi! ;n#1lJIi, 7 is the source area, 8
is Te 1.0. In the thin film, 9 is a drain region, 10 is a source electrode, 11 is a gate electrode, 12 is a drain electrode, and 13 is a silicon thin M region.

An energy band diagram with this configuration is shown in FIG. By providing the Znb thin film 6 between the silicon 11 film 13 and the amorphous insulating substrate 6, the band shift 9 in the silicon thin film region 13 on the amorphous insulating substrate s side can be made as shown in FIG. Induction of electrons tilted toward higher energy is suppressed. This means that silicon and 2nd electron affinity are 4.
01@V, 3.9eV, silicon and Z
The bandgap of n8 is 1.1@V and 3.54, respectively.
- Required from the relationship of being V. Furthermore, the deviation in lattice constant between the silicon crystal and the Zn8 thin film is about 0.2%@degree, and the interface unit due to the lattice mismatch between the silicon 111[ and the XnB thin film becomes very small. In addition, instability due to mobile cations, which is a problem with amorphous insulating substrates◆
It's also hot due to removal.

On the other hand, there is an interface state at the interface between the Zn8 thin film and the amorphous insulating substrate.
Even if charges are induced in the thin ZnBn film, the mobility of the charges in the thin ZnBn film is very small and does not work as a mobile charge. That is, the presence of zng@J[ makes it possible to eliminate the pack channel effect that is a problem between silicon thinning and an amorphous insulating substrate, and to reduce the threshold voltage and source-drain leakage current. Here, since the band gap of ZnBqMI& is as large as 3.54 eV and the carrier mobility is extremely low, it can be considered as a weak insulating layer for silicon thin film transistors.

Furthermore, the Zn & thin film is...
> direction and has a lattice constant that matches that of silicon crystal, it is possible to grow single-crystal silicon thin films on Zn8 thin films by ordinary molecular beam epitaxial method or OVD method. This results in high transconductance as a thin film transistor. Also, silicon thin film and Zn
With the improvement of the interface characteristics between the eight thin films, the device breakdown voltage of the thin film transistor can be increased.

9. For example, sputtering or OVD is applied to the gate insulating film.
By using a Ta1O1 thin sheet formed by the method,
In the silicon thin film region 13 on the gate insulating layer side, the band shift shifts toward the higher energy side, as shown in FIG. 83, and the formation of an inversion region is suppressed. This is because there are very few mobile cations present in the T-0 thin film. Furthermore, the Ta, O, and gluing coefficients are 25, which is 81 degrees higher than that of silicon oxide.

That is, the gate insulating film is a 10g Ta thin film (for example, 500g
~4000^) can eliminate the formation of a problematic inversion region between the silicon 1 film and the silicon oxide 111 film, making it possible to reduce the wJ value voltage. Since the dielectric constant is large, mutual conductance can be increased. Note that the film thickness of Ta10°113111 is determined depending on the application of the transistor.

As mentioned above, according to the present invention, a silicon N film transistor can be manufactured by interposing a Zn8 thin film between a silicon thin film region and an amorphous insulating substrate and using a Ta, O, thin film as a gate insulating film. The threshold voltage and source-drain leakage current can be reduced. Further, by using a T-0 thin film, a silicon thin film transistor with high mutual conductance can be realized due to an increase in the dielectric constant of the gate insulating layer.

[Brief explanation of the drawing]

Fig. 1 is an energy band diagram of a conventional structure in which a silicon thin film and an amorphous insulating substrate are in direct contact, Fig. 2 is a cross-sectional view of an embodiment of the present invention, and Fig. 3 is a structure according to the present invention. An energy band diagram is shown. DESCRIPTION OF SYMBOLS 1... Gate electrode region, 2... Silicon oxide thin film development, 3... Silicon thin film region, 4... Amorphous insulating substrate, 5... Amorphous insulating substrate, 6... Zn8 thin exhibition, 7
...Source region, 8...Ta, O, thin film, 9...
Drain region, 10... Source electrode, 11... Gate electrode, 12... Drain electrode, 13... Silicon r
#11171 Area Patent Applicant Figure 1 Figure 2

Claims (1)

[Claims] A silicon thin film transistor characterized in that a silicon thin film is used as a semiconductor thin film and a Tag OH thin film is used as a gate insulating film in a structure in which a ZnB thin film is interposed between a silicon thin film and an amorphous insulating substrate.