JPS58158967A - Silicon thin film transistor - Google Patents

Silicon thin film transistor

Info

Publication number
JPS58158967A
JPS58158967A JP57040111A JP4011182A JPS58158967A JP S58158967 A JPS58158967 A JP S58158967A JP 57040111 A JP57040111 A JP 57040111A JP 4011182 A JP4011182 A JP 4011182A JP S58158967 A JPS58158967 A JP S58158967A
Authority
JP
Japan
Prior art keywords
thin film
silicon
silicon thin
film
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57040111A
Other languages
Japanese (ja)
Inventor
Shunji Seki
関 俊司
Takashi Umigami
海上 隆
Bunjiro Tsujiyama
辻山 文治郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57040111A priority Critical patent/JPS58158967A/en
Publication of JPS58158967A publication Critical patent/JPS58158967A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]

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  • Electrodes Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は低閑値電圧および高相互コンダクタンスを有す
る高性能のシリコン薄膜トランジスタに関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high performance silicon thin film transistors with low idle voltage and high transconductance.

従来、非晶質絶縁基板上のシリコン薄膜トランジスタは
非晶質絶縁基板上に直接堆積したアモルファス状あるい
は多結晶状のシリコン薄膜を半導体薄膜として用い、ま
た熱酸化法あるいはスパッタリング法、ovn法によっ
て得られた酸化シリコン薄膜をゲート絶縁膜として用い
ていた。シリコン薄膜を非晶質絶縁基板上に直接堆積し
た構造におけるエネルギーバンド図を#!1図に示2す
。ここで1はゲート電極領域、2は酸化シリコン薄膜、
3はシリコンfII展領域、4は非晶質絶縁基板である
。この構造ではシリコン薄膜3と基板4の界面での界面
準位が数多く存在し、シリコン薄Ml!I域3と基板4
の界面においてシリコン薄層領域のバンドが界面準位の
影曽を受けてまがシ、可動電子が鋳起される現象、いわ
ゆるバックチャンネル効果によって薄膜シリコントラン
ジスタの閾値電圧が大きくなるとともに、ソース・ドレ
イン間のリーク電流が増加するという欠点がある。また
シリコン薄膜−基板間の界面特性の劣化に起因して薄膜
トランジスタの素子耐圧が低下する。さらに非晶質絶縁
基板上のアモルファスシリコンあるいは多結晶シリコン
においては結晶が悪いことによるキャリア移動度の低下
が見られ、薄膜トランジスタの相互コンダクタンスが高
くならないという欠点がある。
Conventionally, silicon thin film transistors on an amorphous insulating substrate have been produced by using an amorphous or polycrystalline silicon thin film deposited directly on an amorphous insulating substrate as a semiconductor thin film, and by thermal oxidation, sputtering, or OVN method. A silicon oxide thin film was used as the gate insulating film. Energy band diagram for a structure in which a silicon thin film is directly deposited on an amorphous insulating substrate! Shown in Figure 12. Here, 1 is a gate electrode region, 2 is a silicon oxide thin film,
3 is a silicon fII expansion region, and 4 is an amorphous insulating substrate. In this structure, there are many interface states at the interface between the silicon thin film 3 and the substrate 4, and the silicon thin Ml! I area 3 and substrate 4
At the interface, the band of the silicon thin layer region is influenced by the interface state and the phenomenon in which mobile electrons are created, the so-called back channel effect, increases the threshold voltage of the thin film silicon transistor, and the source This has the disadvantage that leakage current between the drains increases. Furthermore, the breakdown voltage of the thin film transistor decreases due to deterioration of the interface characteristics between the silicon thin film and the substrate. Furthermore, in amorphous silicon or polycrystalline silicon on an amorphous insulating substrate, a decrease in carrier mobility is observed due to poor crystallization, and there is a drawback that the mutual conductance of a thin film transistor cannot be increased.

またゲート絶に膜に酸化シリコン薄膜2を用いた場合は
、酸化シリコン薄膜2中の可動陽イオンの影伽を受けて
、シリコン薄膜領域3と酸化シリコン薄JII2の界面
において反転領域が形成され薄膜トランジスタの閾値電
圧が大きくなるという欠点がある。
Furthermore, when the silicon oxide thin film 2 is used as the gate film, an inversion region is formed at the interface between the silicon thin film region 3 and the silicon oxide thin JII 2 due to the influence of mobile cations in the silicon oxide thin film 2, and the thin film transistor The disadvantage is that the threshold voltage of

本発明は、これらの欠点を除去するため、シリコン薄膜
と非晶質絶縁基板との間にZn8@jlを介在させゲー
ト絶縁膜にTa、 O@薄膜を用いることによル、高性
能のシーリコン111JIi)ランジスタを実現できる
ことを目的とするものである。
In order to eliminate these drawbacks, the present invention interposes Zn8@jl between the silicon thin film and the amorphous insulating substrate and uses Ta, O@ thin film for the gate insulating film, thereby producing high-performance silicon. 111JIi) The purpose is to realize a transistor.

前記の目的を達成するため、本発明はシリコン薄膜と非
晶質絶縁基板との間にZn8薄論を介在させた構造にお
いて、半導体薄膜としてシリコン薄膜を、ゲート絶縁膜
としてTa、 O,薄膜を用いることを特徴とするシリ
コン薄膜トランジスタを発明の要旨とするものである。
In order to achieve the above object, the present invention has a structure in which a Zn8 thin film is interposed between a silicon thin film and an amorphous insulating substrate, in which a silicon thin film is used as a semiconductor thin film and a Ta, O, thin film is used as a gate insulating film. The gist of the invention is a silicon thin film transistor characterized in that it is used.

次に本発明の実施例を添附図面について説明する。なお
実施例は一つの例示であって、本発明の:″′ 精神を逸脱しない範囲内で、種々の変更あるい祉改良を
行いうろことは云うまでもない。
Next, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

第2図は本発明の実施例であって、5は非晶質絶縁基板
、1lFi!;n#1lJIi、 7はソース領域、8
はテ1.0.薄膜、9はドレイン領域、10はソース電
極、11はゲート電極、12はドレイン電極、13はシ
リコン薄M領域である。
FIG. 2 shows an embodiment of the present invention, in which 5 is an amorphous insulating substrate, 1lFi! ;n#1lJIi, 7 is the source area, 8
is Te 1.0. In the thin film, 9 is a drain region, 10 is a source electrode, 11 is a gate electrode, 12 is a drain electrode, and 13 is a silicon thin M region.

この構成によるエネルギーバンド図を第3図に示す。シ
リコン11膜13と非晶質絶縁基板6との間にZnb薄
膜6を設けることによシ、非晶質絶縁基板s側のシリコ
ン薄膜領域13において、バンドのまが9は第3図のよ
うにエネルギーの高い方へ傾き電子の誘起が抑制される
。これはシリコンと2ndの電子親和力がそれぞれ4.
01@V 、 3.9eVであることと、シリコンとZ
n8のバンドギャップがそれぞれ1.1@V、3.54
・Vであることの関係から求められる。さらにシリコン
結晶とZn8薄膜の格子定数のずれは約0.2%@度で
あシ、シリコン111[と’XnB薄膜との格子不整合
による界面単位が非常に小さくなる。また非晶質絶縁基
板で問題となる可動陽イオンによる不安定性などの影◆
も除  ′去で暑る。
An energy band diagram with this configuration is shown in FIG. By providing the Znb thin film 6 between the silicon 11 film 13 and the amorphous insulating substrate 6, the band shift 9 in the silicon thin film region 13 on the amorphous insulating substrate s side can be made as shown in FIG. Induction of electrons tilted toward higher energy is suppressed. This means that silicon and 2nd electron affinity are 4.
01@V, 3.9eV, silicon and Z
The bandgap of n8 is 1.1@V and 3.54, respectively.
- Required from the relationship of being V. Furthermore, the deviation in lattice constant between the silicon crystal and the Zn8 thin film is about 0.2%@degree, and the interface unit due to the lattice mismatch between the silicon 111[ and the XnB thin film becomes very small. In addition, instability due to mobile cations, which is a problem with amorphous insulating substrates◆
It's also hot due to removal.

一方、Zn8薄膜と非晶質絶縁基板との界面においては
界面準位が存在するが、この界面準位によ、6 zna
薄展薄膜電荷が誘起されても、ZnBn膜薄での電荷の
移動度は非常に小さく可動電荷と祉ならない。すなわち
zng@J[の存在によルシリコン薄換と非晶質絶縁基
板間で問題となるパックチャンネル効果を除去でき、閾
値電圧およびソース・ドレイン間のリーク電流を小さく
することが可能である。ここで、ZnBqMI&のバン
ドギャップは、3.54 eVと大きいことと、キャリ
ア移動度が極めて小さいことから、シリコン薄膜トラン
ジスタに対して祉絶縁層と見なせる。
On the other hand, there is an interface state at the interface between the Zn8 thin film and the amorphous insulating substrate.
Even if charges are induced in the thin ZnBn film, the mobility of the charges in the thin ZnBn film is very small and does not work as a mobile charge. That is, the presence of zng@J[ makes it possible to eliminate the pack channel effect that is a problem between silicon thinning and an amorphous insulating substrate, and to reduce the threshold voltage and source-drain leakage current. Here, since the band gap of ZnBqMI& is as large as 3.54 eV and the carrier mobility is extremely low, it can be considered as a weak insulating layer for silicon thin film transistors.

さらに、Zn&薄膜は非晶質絶縁基板上において奄〈…
〉方向に配向し、かつシリコン結晶と格子定数が一致す
ることから、Zn8薄撫上に通常の分子線エピタキシャ
ル法やOVD法によル単結晶シリコン薄膜の成長が可能
であシ、キャリア移動度が高く薄膜トランジスタとして
高相互コンダクタンスとなる。またシリコン薄膜とZn
8薄膜間の界面特性の向上にともなって薄膜トランジス
タの素子耐圧を増大させることができる。
Furthermore, the Zn & thin film is...
> direction and has a lattice constant that matches that of silicon crystal, it is possible to grow single-crystal silicon thin films on Zn8 thin films by ordinary molecular beam epitaxial method or OVD method. This results in high transconductance as a thin film transistor. Also, silicon thin film and Zn
With the improvement of the interface characteristics between the eight thin films, the device breakdown voltage of the thin film transistor can be increased.

を九、ゲート絶縁膜に例えばスパッタリング法やOVD
法によシ形成したTa1O1薄展を用いることによシ、
ゲート絶縁層側のシリコン薄膜領域13においてバンド
のまがシは83図のように、エネルギーの高い方へ#き
、反転領域の形成が抑制される。仁れはT−0,薄膜中
に存在する可動陽イオンが非常に少ないためである。ま
たTa、O,のり電率は25で酸化シリコンにくらベア
倍81度大きい。
9. For example, sputtering or OVD is applied to the gate insulating film.
By using a Ta1O1 thin sheet formed by the method,
In the silicon thin film region 13 on the gate insulating layer side, the band shift shifts toward the higher energy side, as shown in FIG. 83, and the formation of an inversion region is suppressed. This is because there are very few mobile cations present in the T-0 thin film. Furthermore, the Ta, O, and gluing coefficients are 25, which is 81 degrees higher than that of silicon oxide.

すなわちゲート絶縁膜にTa10g薄膜(例えば500
〜4000^)を用いることによシリコン1膜と酸化シ
リコン111膜の間で問題となる反転領域の形成を除去
でき、wJ値電圧を小さくすることが可能となる。ま九
誘電率が大きいため、相互コンダクタンスを高くするこ
とが可能となる。なおTa10゜113111の膜厚は
トランジスタの用途によシ定められるものである。
That is, the gate insulating film is a 10g Ta thin film (for example, 500g
~4000^) can eliminate the formation of a problematic inversion region between the silicon 1 film and the silicon oxide 111 film, making it possible to reduce the wJ value voltage. Since the dielectric constant is large, mutual conductance can be increased. Note that the film thickness of Ta10°113111 is determined depending on the application of the transistor.

以上、rii、明したように本発明によればシリコン薄
膜領域と非晶質絶縁基板の間にZn8薄膜を介在させゲ
ート絶縁膜にTa、 O,薄膜を用いることによシ、シ
リコンN膜トランジスタの閾値電圧、ソース・ドレイン
間のリーク電流を小さくできる。また、T−0,薄膜を
用いることでゲート絶縁層の誘電率の増大による高相互
コンダクタンスのシリコン薄膜トランジスタを実現する
ことができる効果を有するものである。
As mentioned above, according to the present invention, a silicon N film transistor can be manufactured by interposing a Zn8 thin film between a silicon thin film region and an amorphous insulating substrate and using a Ta, O, thin film as a gate insulating film. The threshold voltage and source-drain leakage current can be reduced. Further, by using a T-0 thin film, a silicon thin film transistor with high mutual conductance can be realized due to an increase in the dielectric constant of the gate insulating layer.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のシリコン薄膜と非晶質絶縁基板とが直接
接触している構造におけるエネルギーバンド図、第2図
は本発明の一実施例の断面図、第3図は本発明の構成に
よるエネルギーバンド図を示す。 1・・・ゲート電極領域、2・・・酸化シリコン薄膜展
、3・・・シリコン・薄膜領域、4・・・非晶質絶縁基
板、5・・・非晶質絶縁基板、6・・・Zn8薄展、7
・・・ソース領域、8・・・Ta、O,薄膜、9・・・
ドレイン領域、10・・ソース電極、11・・・ゲート
電極、12・・・ドレイン電極、13・・・シリコンr
#11171領域特許出願人 第1図 第2図
Fig. 1 is an energy band diagram of a conventional structure in which a silicon thin film and an amorphous insulating substrate are in direct contact, Fig. 2 is a cross-sectional view of an embodiment of the present invention, and Fig. 3 is a structure according to the present invention. An energy band diagram is shown. DESCRIPTION OF SYMBOLS 1... Gate electrode region, 2... Silicon oxide thin film development, 3... Silicon thin film region, 4... Amorphous insulating substrate, 5... Amorphous insulating substrate, 6... Zn8 thin exhibition, 7
...Source region, 8...Ta, O, thin film, 9...
Drain region, 10... Source electrode, 11... Gate electrode, 12... Drain electrode, 13... Silicon r
#11171 Area Patent Applicant Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] シリコン薄膜と非晶質絶縁基板との間にZnB薄展を介
在させた構造において、半導体薄膜としてシリコン薄膜
を、ゲート絶縁膜としてTag OH薄膜を用いること
を特徴とするシリコン薄膜トランジスタ。
A silicon thin film transistor characterized in that a silicon thin film is used as a semiconductor thin film and a Tag OH thin film is used as a gate insulating film in a structure in which a ZnB thin film is interposed between a silicon thin film and an amorphous insulating substrate.
JP57040111A 1982-03-16 1982-03-16 Silicon thin film transistor Pending JPS58158967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57040111A JPS58158967A (en) 1982-03-16 1982-03-16 Silicon thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57040111A JPS58158967A (en) 1982-03-16 1982-03-16 Silicon thin film transistor

Publications (1)

Publication Number Publication Date
JPS58158967A true JPS58158967A (en) 1983-09-21

Family

ID=12571737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57040111A Pending JPS58158967A (en) 1982-03-16 1982-03-16 Silicon thin film transistor

Country Status (1)

Country Link
JP (1) JPS58158967A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5289030A (en) * 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
US5568288A (en) * 1991-03-26 1996-10-22 Semiconductor Energy Laboratory Co., Ltd. Method for forming thin film transistors with anodic oxide on sides of gate line
US5572047A (en) * 1990-12-10 1996-11-05 Semiconductor Energy Laboratory Co., Ltd. Electro-Optic device having pairs of complementary transistors
US5913112A (en) * 1991-03-06 1999-06-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region
US5917225A (en) * 1992-03-05 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor having specific dielectric structures
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
USRE36314E (en) * 1991-03-06 1999-09-28 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode
US6028333A (en) * 1991-02-16 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
KR20030047571A (en) * 2001-12-11 2003-06-18 삼성에스디아이 주식회사 Method of Forming Silicon Thin Film
US6624450B1 (en) 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5572047A (en) * 1990-12-10 1996-11-05 Semiconductor Energy Laboratory Co., Ltd. Electro-Optic device having pairs of complementary transistors
US6028333A (en) * 1991-02-16 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors
USRE36314E (en) * 1991-03-06 1999-09-28 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode
US5474945A (en) * 1991-03-06 1995-12-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming semiconductor device comprising metal oxide
US5289030A (en) * 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
US5913112A (en) * 1991-03-06 1999-06-15 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an insulated gate field effect semiconductor device having an offset region and/or lightly doped region
US5933205A (en) * 1991-03-26 1999-08-03 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5963278A (en) * 1991-03-26 1999-10-05 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method for driving the same
US5568288A (en) * 1991-03-26 1996-10-22 Semiconductor Energy Laboratory Co., Ltd. Method for forming thin film transistors with anodic oxide on sides of gate line
US5956105A (en) * 1991-06-14 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6778231B1 (en) 1991-06-14 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical display device
US7928946B2 (en) 1991-06-14 2011-04-19 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6975296B1 (en) 1991-06-14 2005-12-13 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6803600B2 (en) 1991-08-26 2004-10-12 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US6331723B1 (en) 1991-08-26 2001-12-18 Semiconductor Energy Laboratory Co., Ltd. Active matrix display device having at least two transistors having LDD region in one pixel
US7456427B2 (en) 1991-08-26 2008-11-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US7821011B2 (en) 1991-08-26 2010-10-26 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect semiconductor devices and method of manufacturing the same
US5917225A (en) * 1992-03-05 1999-06-29 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor having specific dielectric structures
US6624450B1 (en) 1992-03-27 2003-09-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
KR20030047571A (en) * 2001-12-11 2003-06-18 삼성에스디아이 주식회사 Method of Forming Silicon Thin Film

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