JPS6127681A - Field effect transistor having channel part of superlattice construction - Google Patents

Field effect transistor having channel part of superlattice construction

Info

Publication number
JPS6127681A
JPS6127681A JP14795784A JP14795784A JPS6127681A JP S6127681 A JPS6127681 A JP S6127681A JP 14795784 A JP14795784 A JP 14795784A JP 14795784 A JP14795784 A JP 14795784A JP S6127681 A JPS6127681 A JP S6127681A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
layer
construction
superlattice
si
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14795784A
Other versions
JPH0224025B2 (en )
Inventor
Zenko Hirose
Seiichi Miyazaki
Original Assignee
Res Dev Corp Of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H01L29/78687Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure

Abstract

PURPOSE:To obtain a stable and high-speed operable field effect transistor by employing a superlattice construction formed by laminating semiconductor thin films of two kinds of semiconductors having different forbidden bands alternately in channel parts. CONSTITUTION:A hetero junction superlattice construction formed by laminating very thin films of two kinds of semiconductors having different forbidden bands alternately is employed in channel parts. The said hetero junction superlattice construction is formed by alternately laminating super thin layers of crystals Si and Si1-xGex, non-crystalline Si and Si1-xNx, non-crystalline Si and Si1-xCx or the like. For example, a non-crystalline a-Si1-xNx:H layer 7 containing hydrogen and a non-crystalline a-Si:H layer 8 are alternately laminated on a semiconductor bulk layer 1. With the thickness of each layer W selected in the range of 30-200Angstrom , an active layer 2 of a heterojunction superlattice construction of which channels are formed during operation is rovided and a source electrode 3, a drain elecerode 4, a gate electrode 5 and a gate insulating film 6 of SiO2, Si3N4 or the like are provided too, thereby to produce a thin film field effect transistor.
JP14795784A 1984-07-17 1984-07-17 Expired - Lifetime JPH0224025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14795784A JPH0224025B2 (en) 1984-07-17 1984-07-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14795784A JPH0224025B2 (en) 1984-07-17 1984-07-17

Publications (2)

Publication Number Publication Date
JPS6127681A true true JPS6127681A (en) 1986-02-07
JPH0224025B2 JPH0224025B2 (en) 1990-05-28

Family

ID=15441903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14795784A Expired - Lifetime JPH0224025B2 (en) 1984-07-17 1984-07-17

Country Status (1)

Country Link
JP (1) JPH0224025B2 (en)

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61230374A (en) * 1985-04-05 1986-10-14 Seiko Epson Corp Field-effect type transistor and manufacture thereof
JPS62279672A (en) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd Semiconductor device
JPS6394681A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Manufacture of insulated-gate field-effect semiconductor device
JPS6394680A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Insulated-gate field-effect semiconductor device
JPS6394682A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Manufacture of insulated-gate field-effect semiconductor device
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
US4908678A (en) * 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US5051786A (en) * 1989-10-24 1991-09-24 Mcnc Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof
EP0484987A2 (en) * 1987-01-23 1992-05-13 Hosiden Corporation Thin film transistor
EP0694756A2 (en) 1994-07-27 1996-01-31 Shimadzu Corporation Elongation measurement using a laser non-contact extensometer
WO2002001641A1 (en) * 2000-06-27 2002-01-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device
WO2002043157A1 (en) * 2000-11-21 2002-05-30 Matsushita Electric Industrial Co.,Ltd. Semiconductor device and its manufacturing method
US6460418B1 (en) 2000-01-19 2002-10-08 Kishimoto Sangyo Co., Ltd. Method of and apparatus for measuring elongation of a test specimen
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
WO2005018004A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
WO2005034245A1 (en) * 2003-06-26 2005-04-14 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131779A (en) * 1977-04-20 1978-11-16 Ibm Semiconductor superlattice structure
JPS55117281A (en) * 1979-03-05 1980-09-09 Nippon Telegr & Teleph Corp <Ntt> 3[5 group compound semiconductor hetero structure mosfet
JPS5984475A (en) * 1982-11-05 1984-05-16 Hitachi Ltd Field effect device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131779A (en) * 1977-04-20 1978-11-16 Ibm Semiconductor superlattice structure
JPS55117281A (en) * 1979-03-05 1980-09-09 Nippon Telegr & Teleph Corp <Ntt> 3[5 group compound semiconductor hetero structure mosfet
JPS5984475A (en) * 1982-11-05 1984-05-16 Hitachi Ltd Field effect device

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61230374A (en) * 1985-04-05 1986-10-14 Seiko Epson Corp Field-effect type transistor and manufacture thereof
JPS62279672A (en) * 1986-05-28 1987-12-04 Kanegafuchi Chem Ind Co Ltd Semiconductor device
US4806998A (en) * 1986-06-30 1989-02-21 Thomson-Csf Heterojunction and dual channel semiconductor field effect transistor or negative transconductive device
US5008211A (en) * 1986-10-08 1991-04-16 Semiconductor Energy Laboratory Co., Ltd. Method for forming FET with a super lattice channel
JPS6394680A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Insulated-gate field-effect semiconductor device
JPS6394682A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Manufacture of insulated-gate field-effect semiconductor device
US4908678A (en) * 1986-10-08 1990-03-13 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
US4988634A (en) * 1986-10-08 1991-01-29 Semiconductor Energy Laboratory Co., Ltd. Method for forming FET with a super lattice channel
JPS6394681A (en) * 1986-10-08 1988-04-25 Semiconductor Energy Lab Co Ltd Manufacture of insulated-gate field-effect semiconductor device
US5021839A (en) * 1986-10-08 1991-06-04 Semiconductor Energy Laboratory Co., Ltd. FET with a super lattice channel
EP0484987A2 (en) * 1987-01-23 1992-05-13 Hosiden Corporation Thin film transistor
US5051786A (en) * 1989-10-24 1991-09-24 Mcnc Passivated polycrystalline semiconductors quantum well/superlattice structures fabricated thereof
EP0694756A2 (en) 1994-07-27 1996-01-31 Shimadzu Corporation Elongation measurement using a laser non-contact extensometer
US6993222B2 (en) 1999-03-05 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
US7123792B1 (en) 1999-03-05 2006-10-17 Rj Mears, Llc Configurable aperiodic grating device
US6460418B1 (en) 2000-01-19 2002-10-08 Kishimoto Sangyo Co., Ltd. Method of and apparatus for measuring elongation of a test specimen
US6674131B2 (en) 2000-06-27 2004-01-06 Matsushita Electric Industrial Co., Ltd. Semiconductor power device for high-temperature applications
WO2002001641A1 (en) * 2000-06-27 2002-01-03 Matsushita Electric Industrial Co., Ltd. Semiconductor device
WO2002043157A1 (en) * 2000-11-21 2002-05-30 Matsushita Electric Industrial Co.,Ltd. Semiconductor device and its manufacturing method
US6580125B2 (en) 2000-11-21 2003-06-17 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US7033437B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
WO2005013371A3 (en) * 2003-06-26 2005-04-14 Ilija Dukovski Semiconductor device including band-engineered superlattice
US6952018B2 (en) 2003-06-26 2005-10-04 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
WO2005034245A1 (en) * 2003-06-26 2005-04-14 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US7018900B2 (en) 2003-06-26 2006-03-28 Rj Mears, Llc Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7034329B2 (en) 2003-06-26 2006-04-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
WO2005018004A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7071119B2 (en) 2003-06-26 2006-07-04 Rj Mears, Llc Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
US7109052B2 (en) 2003-06-26 2006-09-19 Rj Mears, Llc Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7279699B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Integrated circuit comprising a waveguide having an energy band engineered superlattice
US7279701B2 (en) 2003-06-26 2007-10-09 Rj Mears, Llc Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7288457B2 (en) 2003-06-26 2007-10-30 Rj Mears, Llc Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
US7303948B2 (en) 2003-06-26 2007-12-04 Mears Technologies, Inc. Semiconductor device including MOSFET having band-engineered superlattice
US7432524B2 (en) 2003-06-26 2008-10-07 Mears Technologies, Inc. Integrated circuit comprising an active optical device having an energy band engineered superlattice
US7436026B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
US7435988B2 (en) 2003-06-26 2008-10-14 Mears Technologies, Inc. Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7446334B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Electronic device comprising active optical devices with an energy band engineered superlattice
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
US7265002B2 (en) 2003-06-26 2007-09-04 Rj Mears, Llc Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7718996B2 (en) 2006-02-21 2010-05-18 Mears Technologies, Inc. Semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US8389974B2 (en) 2007-02-16 2013-03-05 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
US9972685B2 (en) 2013-11-22 2018-05-15 Atomera Incorporated Vertical semiconductor devices including superlattice punch through stop layer and related methods
US9716147B2 (en) 2014-06-09 2017-07-25 Atomera Incorporated Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
US9899479B2 (en) 2015-05-15 2018-02-20 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
US9941359B2 (en) 2015-05-15 2018-04-10 Atomera Incorporated Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
US9721790B2 (en) 2015-06-02 2017-08-01 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control

Also Published As

Publication number Publication date Type
JPH0224025B2 (en) 1990-05-28 grant
JP1596992C (en) grant

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