JPH02246277A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable the leakage current under reverse voltage to be restrained from occurring by a method wherein polysilicon film to be a drain in a single gate shape is formed as a thin part near a gate while as thick film parts outside the gate and then the impurity concentration in the thin film part is lowered compared with that in the thick film parts. CONSTITUTION:A thin film type single gate MOS transistor formed on the surface of a quartz substrate 9 is composed of a gate 12 through the intermediary of a gate oxide film 11 provided on a thin film part 10a of a polysilicon film 10 in the central part, a source 13 and a drain 14 comprising thick film parts 10b implanted with an impurity and formed of two layered polysilicon films 10 distant from the thin film part 10a and both sides of the central gate 12. Accordingly, the field intensity between the gate 12 and the drain 14 can be decreased. Through these procedures, the numbers of electrons and holes excited by field emission can be decreased to restrain the leakage current from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS transistor and a method for manufacturing the same.

(Prior Art) In recent years, in order to develop high-speed LSIs and display elements, research has been actively conducted on amorphous films, polysilicon films, or recrystallized silicon films formed on transparent substrates. In particular, various approaches have been taken to improve the performance of switching transistors for operating liquid crystals and their driver ICs for liquid crystal display devices such as pocket TVs that are in the practical stage.

Regarding this type of conventional MoS transistor, an enlarged cross-section of the main part shown in FIG. This will be explained using figures.

In the figure, the conventional switching transistor is a dual-gate type MOS transistor formed on a polysilicon film 2 formed on the surface of a quartz substrate 1, with sources 3.
It is composed of a first drain 4 and a second drain 5, and a first gate 7 and a second gate 8 separated by a gate oxide film 6.

In a switching transistor configured in this way,
The source 3 is grounded, the first drain 4 is left floating, a voltage is applied to the second drain 5, and the same voltage is applied to the first and second gates 7 and 8.

(Problems to be Solved by the Invention) However, the above configuration has a problem in that it takes up a large area due to the dual gate type and is difficult to miniaturize. Further, when a negative voltage is applied to the first and second gates 7 and 8 and a positive voltage is applied to the second drain 5 (hereinafter referred to as a reverse voltage), the second drain 5 and the second gate 8 There was a problem in that a high electric field was generated at the contacts. When the electric field strength is large, electrons and holes are generated by field emission from the grain boundary level of the polysilicon film 2. When the generated electrons flow into the second drain 5, it becomes a leak current because it is under a reverse voltage. Furthermore, when the voltage of the second drain 5 increases, there is a problem in that the leakage current further increases due to avalanche amplification.

The present invention solves the above problems and provides a MoS transistor that suppresses leakage current under reverse voltage and a method for manufacturing the same.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention adopts a single gate type, forms a thin film portion of the polysilicon film serving as a drain near the gate, a thick film portion outside of the thin film portion, and The impurity concentration in the thick film portion is lower than that in the thick film portion. The manufacturing method is such that during ion implantation to form source and drain regions in a polysilicon film, the distance from the surface (hereinafter referred to as R) where the concentration of the implanted impurity is maximum is the thickness of the thick film part. The implantation energy is approximately the same as the thickness.

(Function) With the above manufacturing method, the polysilicon film near the gate is formed in a thin film part, which is thinner than the thick film part of the drain equal to R2, so most of the implanted impurities are implanted into the quartz substrate. The impurity concentration in the thick film portion is lower than that in the thick film portion.

That is, the drain has a structure in which the impurity concentration near the gate is reduced. With the above configuration, the electric field strength between the gate and drain can be reduced, and therefore,
The number of electrons and holes excited by field emission decreases. In other words, leakage current is suppressed.

(Example) An example of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is an enlarged sectional view of the main part of a single-gate MOS transistor according to the present invention, FIGS. 2(a) to 8) are enlarged sectional views of the main part showing each manufacturing process, and FIG. FIG. 4, which is a concentration distribution diagram from the surface when implanted, is a characteristic diagram showing the relationship between the gate voltage (v6) and drain current (L) of the MOS transistor according to the present invention.

In FIG. 1, a thin film type single gate MoS transistor is formed on the surface of a quartz substrate 9.

In the center, there is a gate 12 via a gate oxide film 11 provided on the thin film portion 10a of the polysilicon film 10, and the thin film portion 10 described above.
a, and a source 13 and a drain 14 provided on both sides thereof by implanting impurities into a thick film portion 10b formed of two layers of polysilicon film at a distance from the central gate 12.

FIG. 3 is a concentration distribution diagram of impurities implanted into the thick film portion 10b of the polysilicon film 10 shown in FIG. 1, where the horizontal axis represents the depth from the surface and the vertical axis represents the number of atoms per volume lea. The implanted impurity concentration, respectively, increases almost linearly from the surface to form a mountain shape, and begins to decrease after passing the maximum point.

In the MoS transistor shown in FIG.
The film thickness of ilO is such that the thick film part 10b is formed at t in FIG. 3, and the thin film part 10a is formed at t2, which is approximately 1/3 of the thickness. Therefore, the drain 14 consists of a low impurity concentration region near the gate 12 and a high impurity concentration region far away.

Next, a method for manufacturing a MOS transistor according to the present invention will be explained with reference to FIGS. 2(a) to 6).

First, a film thickness of 0.2 μm to 0.3 μm is applied to the entire surface of the quartz substrate 9.
After forming a polysilicon film of μm, buttering is performed to form a single layer portion 10c of the island-shaped thick film portion 10b (see FIG. 2(, )). Next, a film is deposited to form a thick film portion 10b and a thin film portion 10a sandwiched between the thick film portions 10b [FIG. 2(b)].

A gate oxide film 1 with a film thickness of 0.12 μm to 0.13 μm is formed in the center of the thin film portion 10a using dry oxygen gas.
1, a polysilicon film with a thickness of approximately 4000 nm is grown to form a gate 12 [FIG. 2(c)].

Phosphorus ions 15 are added as an n-type impurity at an energy of about 160 k eV to 1×101' to 5×10° pieces/ali.
The MoS film shown in FIG. According to the 6-piece manufacturing method that yields a transistor, 160ke
When phosphorus ions are implanted at V, R is about 0.2μ, and the range where 90% or more of impurities are implanted is 0.2±.
Since it is 0.06 μm, as can be seen from the distribution diagram in FIG. 3, the thick film portion 10b of the source 13 and drain 14 has a high concentration, while the film thickness of the source 13 and drain 14 is approximately 0.05 μm. The concentration is about two orders of magnitude lower.

Returning to FIG. 1, the drain 14 near the gate 13 becomes a thin film part 10a, and its impurity concentration is lower than that of the distant thick film part tab.
Since the impurity concentration is two orders of magnitude lower than the impurity concentration, the electric field strength between the gate 12 and the drain 14 is about 1/100th that of the conventional one, and the number of electrons and holes generated by field emission can be significantly reduced. That is, as shown by curve A in FIG. 4, an increase in leakage current under reverse voltage can be suppressed compared to curve B of the conventional example.

Furthermore, the MOS transistor according to the present invention can reduce the thickness of the channel region under the gate 12 without lowering the impurity concentration of the thick film portion 10b of the source 13 and drain 14 connected to metal such as aluminum silicide. be able to. In general, the subthreshold coefficient S, which indicates the gate voltage required for the current to change by one order of magnitude, is s = dvaz n , to −−(1+ −!;
1--) T dlogID q Cow where,
CI): capacitance under the channel C(1z: given by oxide film capacitance. In other words, as the channel thickness becomes thinner, CD becomes smaller, S also becomes smaller, and the switching characteristics of the MoS transistor become better. Therefore, , the MoS transistor of the present invention is.

Switching characteristics can be improved without reducing contact resistance.

(Effects of the Invention) As explained above, according to the present invention, a MOS transistor with low leakage current and good switching characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is an enlarged sectional view of the main part of the MoS transistor according to the present invention, FIG. 2 (a) or a) is a sectional view of the main part showing each manufacturing process, and FIG. Fourth
The figure shows a MoS transistor according to an embodiment of the present invention and a conventional example. -v6 characteristic diagram, FIG. 5 is an enlarged sectional view of the main part of a conventional MoS transistor. 1.9...Quartz substrate, 2.10...Polysilicon film, 3.13...Source, 4...First drain,
5... Second drain, 6, 11... Gate oxide film, 7... First gate, 8... Second gate, 1
0a...Thin film part, 10b...Thick film part% 10c・
...1st layer part, 12...gate, 14...drain, 15...phosphorus ion. Patent Applicant: Matsushita Electronics Industry Co., Ltd. No. 1゜9...Shidan Shuban too...Book Kenshu 11...G'-to*Ihi Kahi 13°・°So人0...Horisilicon Temperature 10b...78 Job 12...Kate 14... Drain 1st Immortal S Friend Table @ Furnace (pm)

Claims (2)

[Claims] (1) In a MOS transistor in which a source region, a channel region, and a drain region are formed in a semiconductor film,
A channel region is formed in the center of the thin film part of the above semiconductor film, and the impurity concentration in the drain region, which is composed of a thin film part and a thick film part, is set so that the thin film part has a lower concentration than the thick film part. A MOS transistor characterized by having the following structure. (2) In a MOS transistor in which a source region, a channel region, and a drain region are formed in a semiconductor film,
A thick film part and a thin film part are formed in the above semiconductor film, a channel region is formed in the center of the thin film part, and the depth at which the impurity concentration is maximized when implanted into the semiconductor film is determined, and the thick film part of the above drain region is The impurity is implanted with energy that is approximately the same as that of the thick film, so that the impurity concentration in the drain region, which is composed of a thin film part and a thick film part, is lower than that in the thick film part. A method for manufacturing a MOS transistor characterized by the following.