JPS62281473A - Manufacture of field-effect type transistor - Google Patents

Abstract

PURPOSE:To form LDD structure by a simple process by shaping stepped sections so that sections in the vicinity of a gate electrode of source-drain regions are made lower than the other surfaces of the source-drain regions and implanting impurity ions, using a gate electrode region as a mask. CONSTITUTION:Stepped sections are shaped so that a source region 14a and a drain region 15a in the vicinity of a gate electrode 19 are made lower than the surfaces of other source region 14b and drain region 15b, and ions are implanted to the source regions 14a, 14b and the drain regions 15a, 15b, employing a gate electrode 19 region as a mask. A polycrystalline Si layer 12 is shaped onto an insulating substrate 11, a mask layer 13 consisting of SiO2 is formed, and the polycrystalline Si layer 12 in the vicinity of the gate electrode 19 is thinned through etching. The surface of the layer 12 is thermally oxidized to shape a gate oxide film 16, a polycrystalline layer 17 is formed, and a photo-resist 18 is shaped to a section to which the gate electrode 19 must be formed. The gate electrode 19 is shaped through etching, and As ions are implanted, employing the gate electrode 19 region as a mask.

Description

[Detailed Description of the Invention] Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a field-effect transistor, particularly! The present invention relates to a method for manufacturing a field effect transistor (FET) having a film structure.

[Summary of the invention]

The present invention is a method for manufacturing a field effect transistor, in which a step is formed so that the vicinity of the gate electrode in the source and drain regions is lower than the surface of other source and drain regions, and then impurity ions are implanted using the gate electrode region as a mask. By doing so, it is possible to form an LDD (lightly redoped drain) structure.

[Conventional technology]

Traditionally, insulated gate field effect transistors (MOS
In order to solve the problem of characteristic deterioration due to the injection of hot carriers generated near the drain region into the gate oxide film with the miniaturization of FETs, the so-called LD shown in FIG.
A transistor (11) according to the D structure has been proposed.A field effect transistor (11) according to such an LDD structure has been proposed.
), first, source and drain regions T4) and (5
) to make the concentration low, then 5i02 sidewalls (71, (81) are formed on the sidewalls of the gate electrode (3) on the insulating film (6), and using this as a mask, ions are implanted again. High concentration implantation is performed to form high concentration source and drain regions (91, (10). In this way,
The source and drain regions near the gate electrode (3) (
Since the impurity concentration of 41, (5) can be lowered, electric field concentration near the drain region is reduced, and a high-performance and highly reliable transistor (1) can be obtained.

[Problem that the invention seeks to solve]

No report has yet been made regarding a field-effect transistor (FET) having the above-described conventional LDD structure that can be used as a thin mono-transistor (TPT). When attempting to manufacture a thin film transistor following the manufacturing method of a conventional FET with an LDD structure, ions are first implanted using photoresist to form a low concentration impurity region, and then high concentration source and drain regions are formed. A possible manufacturing method is to use photoresist to implant ions at a high concentration. However, when the LDD II structure is manufactured in this manner, two steps, a photoresist formation step and an ion implantation step, are required to form impurity regions with different concentrations, making the manufacturing process cumbersome.

In view of the above points, the present invention provides a simpler method for manufacturing a field effect transistor having an LDD structure.

[Means for solving problems]

In the present invention, in order to manufacture a field effect transistor having an LDD structure, a source region (14a) and a drain region (15a) near the gate electrode (19) are connected to another source region (14b) and a drain region (15b). After forming a step to be lower than the surface, the gate electrode (19
) a source region (14a) using the region as a mask.

(14b) and drain region (15a), (1
5b) Perform ion implantation.

[Effect]

As shown in FIG. 2, when impurity ions are implanted into, for example, a polycrystalline Si layer (12), the impurity concentration draws a Gaussian distribution curve with respect to the distance in the depth direction.

Therefore, the source region (14a) near the gate electrode (19)
) and drain region (15a) are formed shallow < (depth of I), and the other parts of the source region (14b) and drain region (15b) are formed deep < (depth of II). In the source region (14a) and drain region (15a), the dose peaks in the substrate (11).
) side, whereas the other source region (14b)
In the drain region (15b), the peak of the dose is located in the polycrystalline Si layer (12). This results in
An LDD structure can be obtained in which the impurity concentration in the source region (14a) and drain region (15a) near the gate electrode (19) is lower than that in the other source region (14b) and drain region (15b).

〔Example〕

One embodiment of the present invention will be described with reference to FIGS. 1A-D.

First, as shown in FIG. 1A, an insulating substrate, for example, S
A polycrystalline St layer (
12) to a thickness of 600 mm, a mask layer (13) made of Si02 is formed.

Next, as shown in FIG. 1B, the gate electrode (19) is etched by immersing it in ammonia water at 75 to 80°C.
Nearby source region (14a) and drain region (15)
a) The polycrystalline Si layer (12) is thinned to a thickness of 200 mm.

Next, as shown in FIG. 1C, this polycrystalline Si layer (12)
Gate oxidation by thermally oxidizing the surface! l! After forming (16), a polycrystalline Si layer (17) is formed. Then, a photoresist (18) is formed in a portion of this polycrystalline Si layer (17) where a gate electrode (19) is to be formed.

Next, as shown in the first diagram, after etching is performed to form a gate electrode (19), using this gate electrode (19) region as a mask, impurity of the first conductivity type, for example, N type, such as arsenic As, is etched at 50 keV. Implant ions. When ions are implanted under these conditions, as shown in Figure 2,
Peak depth (impurity concentration is 5 x 10.”C)
11-"), the impurity concentration draws a Gaussian curve. Therefore, the source region (14a) near the gate electrode (19)
) and the drain region (15a) are as thin as 200 mm (■ on the X axis), so the peak dose is at the substrate (11) I
Located at ll. On the other hand, the source region (14b) and drain region (15b) other than the vicinity of the gate electrode (19)
Since the thickness is as thick as 600 mm (■ on the X axis), the peak of the dose is located in the polycrystalline Si layer (12). As a result, in one ion implantation process, the impurity concentration in the source region (14a) and drain region (15a) near the gate electrode (19) is lower than that in the other source region (14b) and drain region (15b'). It's becoming LDD
A field effect transistor according to the structure can be obtained.

As shown in FIG. 2, in the case of the ion implantation according to this example, the impurity concentration peaks at a depth of about 400 mm from the surface, but by changing the implantation conditions, ), (14b) and the drain regions (15a), (15b) at arbitrary concentrations. Note that by making the source and drain regions have the structure according to the present invention,
It is possible to reduce the resistance of the source and drain regions.

〔Effect of the invention〕

According to the present invention, the photoresist formation process and the ion implantation process for making a field effect transistor into an LDD structure only need to be performed once each, making the process simpler than conventional manufacturing methods. Note that the present invention is applicable not only to thin film type transistors but also to other field effect type transistors.

[Brief explanation of the drawing]

1A to 1D are process diagrams of the embodiment, FIG. 2 is a graph showing the state of ion implantation, and FIG. 3 is a sectional view of the conventional example. (11) is a 5i02 board, (14a), (14
b) is the source region, (15a), (15b
) is a drain region, and (19) is a gate electrode.

Claims (1)

[Claims] A step is formed so that the vicinity of the gate electrode in the source and drain regions is lower than the surface of the other source and drain regions, and impurity ions are implanted into the source and drain regions using the gate electrode region as a mask. A method for manufacturing a field effect transistor characterized by: