JPH02240934A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To enable oxidation of an etching residue of a polysilicon film without changing a gate length of an MOS-type semiconductor device, by forming a high-concentration diffused layer on a silicon substrate in a self-alignment manner by using as a mask the polysilicon film of which the side-wall part is covered with an oxidation-resistant film. CONSTITUTION:An impurity of low concentration is injected into a silicon substrate 1 in a self-alignment manner by using a polysilicon film 4 to be a gate electrode as a mask. Subsequently, the sidewall part of this polysilicon film 4 to be the gate electrode is covered with an oxidation-resistant film 6, and then an etching residue of the polysilicon film 4 left on a gate oxide film 3 is subjected to oxidation treatment. Using as a mask the polysilicon film 4 of which the sidewall part is covered with this oxidation-resistant film 6, moreover, an impurity of high concentration is injected into the silicon substrate 1 in the self-alignment manner. By this method, the etching residue of the polysilicon film 4 left on the gate oxide film can be oxidized without oxidizing the sidewall part of the polysilicon film 4 to be the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS type semiconductor device.

[Conventional technology]

In recent years, MOS type semiconductor devices have come into widespread use due to the demand for low power consumption. On the other hand, as the degree of integration of integrated circuits increases, it is required to reduce the dimensions of semiconductor devices, but as the gate length of MO8 type semiconductor devices is shortened, the punch-through breakdown voltage of P-channel transistors deteriorates. It is also known that in N-channel transistors, the electric field strength near the drain region increases and true carriers are generated, resulting in a so-called short channel effect in which the threshold voltage is significantly lowered.

In order to suppress these short channel effects, there is a method of providing a lightly doped diffusion layer in the source/drain region at the end of the gate side, such as a source/drain double diffusion structure known as an LDD structure.

A conventional method for manufacturing a MOS type semiconductor device will be described below, taking the structure of an N-channel transistor as an example.

2A to 1E are step-by-step cross-sectional views of a part of a conventional method for manufacturing a MOS type semiconductor device, in which 11 is a p-type silicon substrate, 12 is an element isolation region, 13 is a gate oxide film,
14 is a polysilicon film, 15 is an n-type low concentration diffusion layer, 17
18 is an oxide layer of a polysilicon film, 18 is an n-type high concentration diffusion layer,
19 is a silicon oxide film.

First, an element bone Mwi region 12 made of a thick oxide film is formed on a p-type silicon substrate 11 using a known technique.

Next, a gate oxide film 13 is grown on the p-type silicon substrate 11, and a polysilicon W11 that will become the gate electrode is grown on it.
Grow 4. Next, high-concentration phosphorus is diffused into the polysilicon film 14 in a vapor phase to form a low-resistance film. Furthermore, the resist film is spin-coated, and light exposure technology, electron beam exposure technology,
A resist film is formed into a desired resist pattern using X-ray exposure technology or ion beam exposure technology, and using this resist pattern as a mask, the polysilicon film 14 is selectively removed by dry etching to form a gate electrode. remove. The state at this time is shown in Figure 2 1a.
It is shown in l.

Next, as shown in FIG. 2(b), using the polysilicon film 14 as a gate electrode as a mask, the p-type silicon substrate 1 is
A low concentration impurity is implanted into the n-type low concentration diffusion layer 15.

Next, as shown in FIG. 2(C), the element bone # region 12
In order to prevent the etching residue of the polysilicon film 14 that could not be removed due to the stepped portions of the edges of the polysilicon film 14 from causing an electrical short circuit between the eyebrows of the polysilicon film, a thermal oxidation method is used to remove the etching residue of the polysilicon film 14. Oxidize to make an insulator. At this time, polysilicon 1Iil which also becomes the gate electrode
The sidewalls and top surface of 14 are also oxidized. Furthermore, at this time, the oxidation may invade the gate oxide film 13 in the gate electrode portion, lifting the polysilicon film 14, and creating a shape called a gate bird's beak at both ends of the gate electrode. Note that 17 is an oxide layer of the polysilicon film.

Next, as shown in FIG. 2 1dl, a silicon oxide film 19 is formed on the p-type silicon substrate 11 by a well-known CVD method.
The silicon oxide film 19 is grown to a thickness of μm and anisotropically etched so that the silicon oxide film 19 remains only on the side edges of the gate electrode.
Form a spacer.

Then, as shown in FIG. 2 1 et, a high concentration impurity is implanted into the p-type silicon substrate 11 using the oxide N17 of the polysilicon film and the spacer of the silicon oxide film 19 as a mask to form an n-type high concentration diffusion 91B. A source/drain double diffusion layer is formed at both ends of the gate electrode.

[Problem to be solved by the invention]

However, in the above conventional method for manufacturing a MOS type semiconductor device, the surface of the polysilicon film 14 that becomes the gate electrode is oxidized! ! lli material (oxide layer 1 of polysilicon film)
7), the effective conductive gate length is shortened, and furthermore, the gate has a bird's beak shape, which causes the problem that the channel length of the MOS type semiconductor device changes.

In addition, the polysilicon film 14 in which phosphorus is diffused at a high concentration has a significantly faster oxidation rate than the p-type silicon substrate 11 due to the accelerated oxidation phenomenon, so it is necessary to control the oxidation with high precision, and as a result, the process If the control accuracy becomes complicated and the control accuracy is impaired, there is a problem in that the characteristics of the MO8 type semiconductor device vary.

The purpose of this invention is to oxidize the etching residue of the polysilicon film without changing the gate length of the MOS type semiconductor device (and without increasing the number of manufacturing steps), and to oxidize the etching residue of the polysilicon film without changing the gate length of the MOS type semiconductor device (and without increasing the number of manufacturing steps). It is an object of the present invention to provide a method for manufacturing a MOS type semiconductor device that can form a double diffusion layer of 1.

[Means to solve the problem]

The method for manufacturing a MOS type semiconductor device of the present invention involves implanting low concentration impurities into a silicon substrate in a self-aligned manner using a polysilicon film that will become a gate electrode as a mask, and then implanting a sidewall of the polysilicon film that will become a gate electrode. After covering with an oxidation-resistant film, the etching residue of the polysilicon film remaining on the gate oxide film is oxidized, and the polysilicon film whose sidewalls are covered with this oxidation-resistant film is used as a mask to attach the silicon substrate. High concentration impurities are implanted in a self-aligned manner.

[For production]

According to the method of the present invention, by covering the sidewalls of the polysilicon film that will become the gate electrode with an oxidation-resistant film, the sidewalls of the gate electrode will not be oxidized during the oxidation treatment of etching residue remaining on the gate oxide film. Therefore, the etching residue of the polysilicon film can be oxidized without reducing the width of the gate electrode due to oxidation.

In addition, before covering with an oxidation-resistant film, low concentration impurities are implanted into the silicon substrate using the polysilicon film that is the gate electrode as a mask, and then an oxidation-resistant film that covers the sidewalls of the polysilicon film that is the gate electrode is applied. By implanting high-concentration impurities into the silicon substrate using a polysilicon film, which serves as a spacer and whose sidewalls are covered with an oxidation-resistant film, as a mask, a source/drain double diffusion layer can be formed in a self-aligned manner. ,ru.

〔Example〕

Hereinafter, a method for manufacturing a MOS type semiconductor device according to the present invention will be explained with reference to the drawings. Here, a case of an N-channel transistor will be described as an example.

FIG. 1 ial to lel are M in one embodiment of this invention.
FIG. 3 is a step-by-step cross-sectional view showing a part of a method for manufacturing an O8-type semiconductor device. In the figure, l is a p-type silicon substrate, 2
is an element bone # region, 3 is a gate oxide film, 4 is a polysilicon film, 5 is an n-type low concentration diffusion layer, 6 is a silicon nitride film, 7 is an oxide layer of the polysilicon film, 8 is an n-type high concentration diffusion layer It is.

First, an element isolation region 2 made of a thick oxide film is formed on a p-type silicon substrate l having a concentration of, for example, 5XlO"ell-" using a known technique. Next, p-type silicon substrate l
The gate oxide film 3 is grown to a thickness of, for example, 20 nm.
On top of that, a polysilicon film 4 that will become a gate electrode is placed, for example, at 0.
．． Grow to a thickness of 4 μm.

Next, the polysilicon film 4 is coated with high concentration phosphorus, for example, 10
Gas phase diffusion occurs at 00°C, for example, at a concentration of 3×10” (Jl −
” to form a low resistance film.Furthermore, the resist film is spin-coated and formed into a desired resist pattern using light exposure technology, electron beam exposure technology, X-ray exposure technology, or ion beam exposure technology, Using this resist pattern as a mask, polysilicon film 4 is selectively removed by dry etching to form a gate electrode, and then the resist is removed.

The state at this time is shown in FIG. 1 (al).

Next, as shown in FIG. 1 (bl), using the polysilicon film 4 that is the gate electrode as a mask,
For example, phosphorus ion at 60KeV, 10X IQ”
cs-" to form an n-type low concentration diffusion layer 5 (low concentration ion implantation step).

Next, as shown in FIG. 1 (C1), a silicon nitride film 6 is grown to a thickness of, for example, 0.1 μm on the silicon substrate by the well-known CVD method.

Next, as shown in FIG. 1(d), the silicon nitride film 6
By anisotropically etching the silicon nitride film 6 to leave the silicon nitride film 6 on the sidewalls of the polysilicon film 4 that will become the gate electrode, a spacer of 0.1 μm on one side is added to both ends of the gate electrode (covering process). ).

Next, in order to prevent the etching residue of the polysilicon film 4 that could not be removed due to the steps at the edges of the element isolation region 2 from causing an electrical short circuit between the eyebrows of the polysilicon film, etching is performed at, for example, 900° C. for 30 minutes. The etching residue is then thermally oxidized to become an insulator (thermal oxidation process).

Next, as shown in FIG. 1(e), the silicon nitride film 6
A polysilicon film 4 whose side walls are covered with polysilicon film 4 serves as a gate electrode.
Using as a mask, arsenic ions, for example, are implanted into the p-type silicon substrate 1 under the conditions of 40 KeV and 4 A diffusion layer is formed (high concentration ion implantation process).

Thereafter, an N-channel transistor is formed using a known technique.

In this example, silicon nitride was used as the oxidation-resistant coating that covers the sidewalls of the polysilicon film 4 that will serve as the gate electrode, but any oxidation-resistant coating such as silicon carbide or aluminum oxide may be used. Needless to say, it is effective.

Note that the thermal oxidation step may be performed after the step of forming the n-type high concentration diffusion N8.

As described above, according to this embodiment, by covering the side walls of the polysilicon film 4, which will become the gate electrode, with an oxidation-resistant film, such as a silicon nitride film, the polysilicon film 4, which will become the gate electrode of the MO8 type semiconductor device, The etching residue can be oxidized without changing the width of the 1114, and by implanting low and high concentration impurities before and after forming the oxidation-resistant film, the double diffusion layers of the source and drain can be self-aligned. can be obtained.

〔Effect of the invention〕

According to the method of manufacturing a MOS type semiconductor device of the present invention, etching residue of the polysilicon film remaining on the gate oxide film can be oxidized without oxidizing the sidewall portion of the polysilicon film that becomes the gate electrode, Since the gate length does not change due to oxidation, stability of device characteristics can be achieved.

In addition, as a mask for two impurity implantations when forming source/drain double diffusion layers, the polysilicon film that will become the gate electrode is used before being covered with an oxidation-resistant film, and after the sidewalls are covered with an oxidation-resistant film. Since the polysilicon film is used, the source/drain double diffusion layers can be formed in a self-aligned manner, and a MOS type semiconductor device with excellent characteristics can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) to 1(a) are step-by-step cross-sectional views showing a method for manufacturing an MO5 type semiconductor device according to an embodiment of the present invention, and FIG.
1 to 1e) are step-by-step cross-sectional views showing a conventional method for manufacturing a MOS type semiconductor device. l...p-type silicon substrate, 2...element M region, 3
...Gate oxide film, 4...Polysilicon film, 5...
・N-type low concentration diffusion layer, 6... silicon nitride film, 7...
- Oxidized layer of polysilicon film, 8... n-type high concentration diffusion layer (e)

Claims (1)

[Claims of Claims] When forming a source/drain double diffusion layer of a MOS type semiconductor device, a polysilicon film formed on a silicon substrate via a gate oxide film and serving as a gate electrode is used as a mask to form a polysilicon film on the silicon substrate. a low-concentration ion implantation step for forming a low-concentration diffusion layer in a self-aligned manner; a coating step for covering the sidewalls of the polysilicon film with an oxidation-resistant film after the low-concentration ion implantation step; A thermal oxidation step in which the surface of the silicon substrate is thermally oxidized to convert the etching residue of the polysilicon film remaining on the gate oxide film into an insulator, and the polysilicon film whose sidewalls are covered with the oxidation-resistant film is masked. and a high concentration ion implantation step of forming a high concentration diffusion layer in the silicon substrate in a self-aligned manner.