JPS61252667A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a TFT, which has excellent contact characteristics and high performance, by forming two semiconductor layers in a region, in which contact with a source region, a drain region and wiring material is provided, and determining the thickness of a semiconductor layer, in which a channel is formed at a specified value or less. CONSTITUTION:On a transparent insulating substrate 100, a first polycrystalline silicon layer 101 is formed at a position, which is to become a part of source and drain regions, and machined in a specified pattern. Then a second polycrystalline layer 102, in which a channel region is formed, is formed and machined in a specified pattern. After a gate oxide film 103 is formed by a thermal oxidation process, a gate electrode 104 is formed with polycrystalline silicon having N-type impurities. Thereafter, with a gate electrode as a mask, N-type impurities are implanted, and source and drain regions 107 are formed. At this time, the thickness of the semiconductor layer, in which the channel is formed, is made to be 600Angstrom . Then, an interlayer insulating film 105 is formed on the entire surface and the impurities are activated. Thereafter, windows are formed, and wirings are formed with a wiring material 106. Thus the high performance TFT having a large ON/OFF ratio can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) and a method for manufacturing the same, and more particularly to a TPT that provides high performance characteristics.

[Conventional technology]

The structure, manufacturing method, and characteristics of conventional TPT will be explained.

The second problem is a cross-sectional view of a conventional TPT.

In FIG. 2 (al), a polycrystalline silicon layer 201t is formed on a transparent insulating substrate 200 and processed into a predetermined pattern.

$2 Figure 11) In the thermal oxidation process, the gate oxide film 2 is
After forming 02, a gate electrode 205t- is formed from polycrystalline silicon having N type (P type) impurities. Thereafter, using the gate electrode as a mask, an impurity of N-(Pa) is implanted by an ion implantation method to form a source region and a drain region 204t.

Figure 2 (cl) After forming an interlayer insulating film 205 such as an NH3 film on the entire surface using the CVD method and activating the impurities implanted in the ions through a high-temperature heat treatment process, a window for maintaining contact is formed. @ 21st slope, wiring material 20 such as At, At-81, etc.
6, wiring is formed.

FIG. 2 (61) shows the characteristics of 72 transistors formed by the above-mentioned manufacturing method.The size of the transistor is 20 μm in channel length and 10 μm in channel width W.

X@ is the thickness T(H) of the polycrystalline silicon layer in the channel region
The drain current tOg is shown at Y+m+ (Al?).

The data is shown as the 11ER value when the gate voltage va8 is 20'V, OV with the drain-source voltage VDBK4Vt- applied. According to this, vGB”
The current value Off at OV decreases as the thickness of the polycrystalline silicon layer decreases.

This is because the film resistance in the channel region increases as the film thickness decreases. Regarding the current value at Vcia = 20V, the OH decreases in proportion to the film thickness until the film thickness reaches 60OA, but when it becomes 6OOA or less, the OH tends to increase. This is due to the following reasons. The maximum thickness of the depletion layer is determined by a known method from the defect density of the polycrystalline silicon film, about 10 to 10"/cs, to be approximately 600 a. Therefore, when the film thickness becomes 600 A or less, the thickness of the depletion layer also decreases, and the threshold hold voltage required for TPT'i operation also decreases proportionally. Therefore, ■O
N increases as the film thickness becomes smaller than 600'A.

From the above results, by setting the thickness of the polycrystalline silicon tank to 600A or less, a TPT'i with a high property of 11 with a larger 0N10FF ratio can be obtained.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has the following problems. In other words, if the thickness of the polycrystalline silicon that is the semiconductor layer is made smaller in order to maintain the same characteristics, the thickness of the source and drain regions will also become smaller, making it possible to obtain good contact with the wiring material. becomes difficult, and the work ON decreases as shown in the second section tel. For example, in the case of A4AtSi etc., it is possible to penetrate polycrystalline silicon NI, and in the case of a transparent conductive film such as ITO, the sheet resistance of the source region and drain region and the contact resistance are in a proportional relationship, so A certain degree of film thickness must be ensured. Therefore, in the conventional technology, although it is possible to completely improve the characteristics by making the film thickness of the semiconductor layer smaller, in the end, the film thickness is reduced due to the problem of contact between the source region, the drain region, and the wiring material. You will be restricted.

The present invention is intended to solve these problems, and its purpose is to have good contact characteristics and
TFTs with high performance characteristics are provided.

[Problem t-Means for solving]

The TPT according to the present invention includes a source region, a drain region,
Contact with wiring material)'t-! area or
-f5 of the source region and drain region including the above region
The semiconductor layer is formed of two semiconductor layers in the region or the source region and the drain region 1, and the semiconductor layer having the channel region gold is one of the two semiconductor layers.

At this time, as a matter of course, the thickness of the semiconductor layer including the channel region is smaller than the thickness of the other 10,000 semiconductor layer.

[Effect]

According to the above structure of the present invention, the region having contact between the source region, the drain region, and the wiring material has a semiconductor layer having a sufficient thickness to obtain better contact characteristics, and By making the semiconductor layer 26ooX or less, it is possible to obtain a flat one-hair TFτ'5t4 with a larger 0N10FF ratio. Characteristics of TPT of this structure t-g2 (shown by broken line in el).

〔Example〕

FIG. 1 (al (bl is T in one embodiment of the present invention)
It is a structural sectional view of PT. Here, 100 is a transparent insulating substrate, 101 is a polycrystalline silicon layer, 102 is a polycrystalline silicon layer, 103 is a gate oxide film, 104 is a gate electrode formed of polycrystalline silicon, and 105 is a gate electrode formed by a CVD method. I-insulating film, 106 is At, At-8
It is a first-class wiring metal.

According to FIG. 3, the detailed manufacturing method of FIG. 1 (al) will be fully explained.

FIG. 3 (Al) A transparent insulating substrate 100 has a source region,
A first polycrystalline silicon layer 101 is formed at a position that will become a part of the drain region, and processed into a predetermined pattern. Third
In Figure Cbl, a second polycrystalline silicon layer 102 in which a channel region will be formed is formed and processed into a predetermined pattern.

51g (at, after forming a gate oxide film 103t- by a thermal oxidation process, a gate electrode 104't- is formed from polycrystalline silicon having N-type (P-type) impurities. Thereafter, the gate electrode is masked. By implanting N-type (P-type) impurities using the ion implantation method,
A source region and a drain region 107t are formed. At this time, the shape of the channel is bY, and the thickness of the semiconductor layer is t-60.
Keep it below 0A.

@Figure 3 (At +11, a glabellar insulating film 105 such as an NSG film is formed on the entire surface using the O'VD method, and after activating the aforementioned ion-implanted impurities through a high-temperature heat treatment process, a window for making contact is formed. do.

At tel in Figure 3, wiring is formed using a wiring material 106 such as At or At-81.

〔Effect of the invention〕

As described above, according to the present invention, two semiconductor layers are formed in the entire source region, drain region, and the region having contact with the wiring material, and the thickness of the semiconductor layer in which the channel is formed is reduced. By making it 600λ or less, a TFTt with higher performance can be obtained. Therefore, the TPT with this structure has sufficient characteristics to be used as a tertiary element or a switching element for driving the pixel'wL pole in an active matrix panel, or as an integrated circuit element for driving a shift register or the like. It is something that you have.

[Brief explanation of the drawing]

Figure 1 (a+, (1)l is a main cross-sectional view showing an embodiment of TF"r of the present invention. @ Figure 2 (a1 to (+11 is a process cross-sectional view showing conventional 'rlFT'i), Figure 2 (el is an electrical characteristic diagram of TF'T, FIG. 43 (aJ~(el is a process cross-sectional view showing the TIFT of the present invention. 100 Transparent insulating substrate 101.102 Polycrystalline silicon layer 103 Gate oxide film 104 Gate Electrode 105 Interlayer insulating film 106 Wiring metal.

Claims (1)

[Claims] 1) In a thin film transistor having a source region, a drain region, a gate insulating film, and a gate electrode in contact with the gate insulating film, at least the source region, the drain region,
A thin film transistor characterized in that a region having contact with a wiring material is formed of two semiconductor layers, and a semiconductor layer in which a channel region is formed is one of the two semiconductor layers. 2) The thin film transistor according to claim 1, wherein a part of the region including the source region and the drain region and a region having contact with a wiring material is formed of two semiconductor layers. 3) The thin film transistor according to claim 1, wherein the source region and the drain region are formed of two semiconductor layers. 4) The thin film transistor according to claim 1, wherein the two semiconductor layers are formed of the same semiconductor layer. 5) A thin film transistor according to claim 1, wherein the two semiconductor layers are formed of polycrystalline silicon layers. 6) The thin film transistor according to claim 1, wherein the thickness of the semiconductor layer in which the channel region is formed is smaller than the thickness of the other semiconductor layer. 7) The thickness of the semiconductor layer in which the channel region is formed is 60 mm.
2. The thin film transistor according to claim 1, wherein the thin film transistor has a thickness of 0 Å or less. 8) The thin film transistor according to claim 1, which is used as a switching element for driving a pixel electrode of an active matrix liquid crystal display device. 9) The thin film transistor is used as a pixel electrode driving switching element and a driving integrated circuit of an active matrix liquid crystal display device having a driving integrated circuit on the same substrate. The thin film transistor described in Section 1. 10) Forming a first semiconductor layer that will become part of the source and drain regions on an electrically insulating substrate and processing it into a predetermined pattern, and laminating a second semiconductor layer that will form a channel region. , a step of processing into a predetermined pattern;
A gate insulating film is formed by thermal oxidation, a conductive layer is stacked in contact with the gate insulating film to form a gate electrode, and an N-type or P-type impurity is added to the channel by ion implantation or thermal diffusion. 1. A method of manufacturing a thin film transistor, comprising the step of diffusing into first and second semiconductor layers excluding regions to form source and drain regions. 11) Forming a first semiconductor layer on which a channel region will be formed on an electrically insulating substrate and processing it into a predetermined pattern, and forming a second semiconductor layer that will become part of a source region and a drain region. , a step of processing into a predetermined pattern;
The process of forming a gate insulating film by thermal oxidation and stacking a conductive layer in contact with the gate insulating film to form a gate electrode can also be done by adding N-type or P-type impurities to the channel region using ion implantation or thermal diffusion. 1st layer and 2nd layer excluding
1. A method for manufacturing a thin film transistor, comprising the step of diffusing into a semiconductor layer to form source and drain regions.