JPS6020578A - Insulated gate semiconductor device and manufacture thereof - Google Patents
Insulated gate semiconductor device and manufacture thereofInfo
- Publication number
- JPS6020578A JPS6020578A JP12763883A JP12763883A JPS6020578A JP S6020578 A JPS6020578 A JP S6020578A JP 12763883 A JP12763883 A JP 12763883A JP 12763883 A JP12763883 A JP 12763883A JP S6020578 A JPS6020578 A JP S6020578A
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- source
- substrate
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052796 boron Inorganic materials 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 230000015654 memory Effects 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は絶縁ゲート電界効果トランジスタ（ＭＯＳＦＥ
Ｔ）を有する半導体装置のショート（短）チャネル化技
術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to an insulated gate field effect transistor (MOSFE).
This invention relates to short channel technology for semiconductor devices having T).
メモリの高密度化、微細化に伴い、ＭＱＳＦＥＴにおい
てショート・チャネル化がすすみ、ゲート・ドレイン容
量増大、■ｔｈ低下あるいはパンチスルーなどとショー
ト、チャネル効果が問題となっている。With the increasing density and miniaturization of memories, short channels in MQSFETs are progressing, and short and channel effects such as increased gate-drain capacitance, decreased th, and punch-through have become problems.
第１図にプレーナ型のｎチャネルＭＱＳＦＥＴが示され
、１はｐｆｉｓｉ基体、２はソースｎ＋型領域、３はド
レインｎ１型領域、４はゲート絶縁膜、５はゲート電極
となる導体（金属又はポ１Ｊｓｉ）層であって、ゲート
電圧■。が印加される。ソース・ドレイン表面にＡ、ｌ
アルミニウム）電極Ｓ。A planar type n-channel MQSFET is shown in FIG. 1Jsi) layer with gate voltage ■. is applied. A, l on the source/drain surface
aluminum) electrode S.
Ｄが設けられる。D is provided.
このよりな４昔造のＭＱＳＦＥＴにおいて、チャネル長
しが２μｍ以下であるとすると、ドレイン電圧ＶＤを大
きくしていくと、ドレイン端の反転層がなく、 １ｘす
、空乏層のみができる状態となる。Assuming that the channel length of this 4-year-old MQSFET is 2 μm or less, as the drain voltage VD is increased, there will be no inversion layer at the drain end, and only a 1x depletion layer will be formed. .
ツレで、ドレインに接する絶縁膜４が薄い（５００〜８
００ｋ）ことによりゲート・ドレイン間容量Ｃ６Ｄが太
き（、したがって周波数特性ｆＴを大きくとることが困
難である。又、ドレイン端での電界集中により降伏電圧
ＢｖＤｓが低下し、ｖＴが低下する。さらにゲート電圧
印加によって空乏層７が第１図に破線で示すような形に
伸びてパンチスルーが起りやすく、十分な飽和特性が得
られない。すなわち、この場合第２図において破線で示
すような■ＤＢ ’８Ｄ特性を生じることになった。Due to distortion, the insulating film 4 in contact with the drain is thin (500 to 8
00k), the gate-drain capacitance C6D is large (therefore, it is difficult to obtain a large frequency characteristic fT. Also, due to the electric field concentration at the drain end, the breakdown voltage BvDs decreases, and vT decreases. When the gate voltage is applied, the depletion layer 7 expands into the shape shown by the broken line in FIG. 1, and punch-through tends to occur, making it impossible to obtain sufficient saturation characteristics.In other words, in this case, the depletion layer 7 expands into the shape shown by the broken line in FIG. This resulted in DB'8D characteristics.
本発明の目的とするところは、上記したＭＱＳＦＥＴに
おけるショート・チャネル効果を低減するためのもので
あって、すなわち、ショート・チャネルＭＯ８ＦＥＴに
おいてｆＴを向上し、降伏電圧を高めるとともに飽和特
性を改善することにある。An object of the present invention is to reduce the short channel effect in the above-mentioned MQSFET, that is, to improve fT, increase the breakdown voltage, and improve the saturation characteristics in the short channel MO8FET. It is in.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ＭＱＳＦＥＴにおいて、チャネル部直下の基
体内にこの基体（たとえばｐ−型）と同導電型高濃度（
たとえばｐ＋型）の埋込領域を形成することによって空
乏層のパンチスルーを抑えるようにし、又、ゲートが形
成された絶縁膜の少なくともドレインと接する部分を選
択酸化による厚膜部とすることにより、ゲート・ドレイ
ン容量を低減し、もづてショートチャネル効果の低減を
図ったものである。That is, in an MQSFET, there is a high concentration (for example, p-type) and the same conductivity type in the substrate directly under the channel part.
For example, by forming a p+ type buried region to suppress the punch-through of the depletion layer, and by making at least the portion of the insulating film in which the gate is formed, which is in contact with the drain, a thick film portion by selective oxidation. This is intended to reduce the gate/drain capacitance and thereby reduce the short channel effect.
第３図は本発明の一実施例であって、チャネル長２μｍ
のｎチャネｆｉｖＭＱｓＦＥＴの原理的構造を示す断面
図である。FIG. 3 shows an embodiment of the present invention, with a channel length of 2 μm.
FIG. 2 is a cross-sectional view showing the basic structure of an n-channel fivMQsFET.
同図における構成部分であって前掲第１図における構成
部分と共通する部分は、第１図と同一指示番号記号が用
いられる。The same designation numbers and symbols as in FIG. 1 are used for components in this figure that are common to those in FIG. 1 above.
この実施例では、ソース・ドレイン端（少なくともドレ
イン端）とゲート電極５との間に選択酸化による１μ！
ｎ程度の厚膜の絶縁膜８を形成することにより、ゲート
・ドレイン容量ＣＧＤを低減し、もってｆＴを向上させ
る。In this embodiment, the gap between the source/drain end (at least the drain end) and the gate electrode 5 is 1 μm by selective oxidation.
By forming the insulating film 8 with a thickness of about n, gate-drain capacitance CGD is reduced, thereby improving fT.
さらに、この実施例では、チャネル部直下のｐ−型半導
体基体内に基体の導電型よりも高濃度のｐ＋型型埋領領
域９たとえばＢ（ボロン）のイオン打込みにより形成す
ることにより、ゲート電圧ＶＧ印加時空乏層７が同図の
破線で示す形に伸びて、パンチスルーな抑制してシミー
トチャネルに特有の不飽和特性を低減する。このときの
ソース・ドレイン電流は、矢印■。方向にそってチャネ
ル部を通ってドレインに流れる。Furthermore, in this embodiment, a p+ type buried region 9 having a higher concentration than the conductivity type of the base material is formed in the p- type semiconductor substrate directly under the channel portion by ion implantation of B (boron), thereby increasing the gate voltage. When VG is applied, the depletion layer 7 extends in the shape shown by the broken line in the same figure, suppressing punch-through and reducing the unsaturated characteristics peculiar to the cimit channel. The source/drain current at this time is indicated by the arrow ■. flows along the direction through the channel portion to the drain.
なお、点線７′はｐ＋型領領域９形成しない場合の空乏
層ののびの形態を示し、ショートチャネル時に同図の矢
印■。′で示す電流成分が無視することができず、第２
図の破線で示す分のリーク特性となる。この■。成分は
、空乏層の断面積に比例するものである。実施例で説明
した本発明によれば空乏層のパンチスルーがおさえられ
ることでＩ、／成分が低減される。Note that the dotted line 7' indicates the form of the depletion layer in the case where the p+ type region 9 is not formed, and is indicated by the arrow ■ in the figure when a short channel is formed. ′ cannot be ignored, and the second
The leak characteristics are shown by the broken line in the figure. This ■. The component is proportional to the cross-sectional area of the depletion layer. According to the present invention described in the embodiments, punch-through of the depletion layer is suppressed, thereby reducing the I,/component.
第４図〜第８図は、本発明の一実施例であってエンハン
スモードｎチャネルＭＯ８ＦＥＴの製造プロセスを示す
工程断面図である。各工程は下記のように行われる。FIGS. 4 to 8 are process cross-sectional views showing the manufacturing process of an enhanced mode n-channel MO8FET, which is an embodiment of the present invention. Each step is performed as follows.
（１）ｐ−型Ｓｉ基体（サブストレート）１の−生表面
上に形成したＳ ｉ Ｂ Ｎ４（シリコン窒化物）膜１
０をマスクとしてＡｓ （ヒフ４）＋Ｐ（リン）等を高
濃度イオン打込みし拡散することによりｎ＋型領領域２
３を、ソース・ドレインとして形成する。(1) S i B N4 (silicon nitride) film 1 formed on the raw surface of p-type Si substrate 1
By implanting high-concentration ions of As (Hif 4) + P (phosphorus), etc. using 0 as a mask and diffusing them, the n+ type region 2 is formed.
3 is formed as a source/drain.
（第４図）。(Figure 4).
ｔ２１ Ｓｉ、Ｎ４膜１０を取り除き、口１型領域２．
３上に新たに形成したＳｉ、Ｎ４膜１１をマスクとして
ｎ＋型領領域はさまれた基体表面に酸化膜１２を通して
低濃度にＡｓ等をイオン打込みしチャネル部となる部分
にｘｌ−型層１３を形成する（第５図Ｘ（３） 前記Ｓ
ｉ３Ｎ４膜１１を取り除き、新たにＳ ｉ３Ｎ。t21 The Si, N4 film 10 is removed and the mouth 1 type region 2.
Using the Si, N4 film 11 newly formed on 3 as a mask, ions of As or the like are implanted at a low concentration through the oxide film 12 onto the surface of the substrate between the n+ type regions, and an xl- type layer 13 is formed in the part that will become the channel part. (Fig. 5 X (3))
Remove the i3N4 film 11 and add new Si3N.
膜１４を形成しＳｉ基体の一部を窓開した状態で８１表
面を０．５μｍ程度エッチした後高圧酸化を行なって上
記窓開部分のＳｉを選択酸化し、厚さ１μｍ程度の厚膜
酸化膜（Ｓ ｉ０２ ’１１！’％）８を形成する。After forming the film 14 and etching the surface of 81 by about 0.5 μm with a window open in a part of the Si substrate, high-pressure oxidation is performed to selectively oxidize the Si in the window open area to form a thick film oxidation with a thickness of about 1 μm. A film (S i02 '11!'%) 8 is formed.
この厚い酸化ｆｌｕ ８は第６図に示すようにドレイン
側においてはゲートとの境界部（ｎ＋型領領域３チャネ
ルｎ−型層１３との境）に形成される力ｔ、ソース側で
はｎ＋型領領域２内側にくるように形成される。As shown in FIG. 6, this thick oxidized flu 8 is caused by a force t formed at the boundary with the gate (border with the n+ type region 3 channel n- type layer 13) on the drain side, and an n+ type on the source side. It is formed so as to be located inside the territory area 2.
（４）ソース・ドレイン表面のＳｉ、Ｎ４膜を取り除℃
・て酸化しフィールド酸化膜１５を形成する（第７図）
。(4) Remove the Si and N4 films on the source and drain surfaces ℃
・Oxidize to form field oxide film 15 (FIG. 7)
.
（５）チャネル部上のＳｉ”Ｎ４膜を取り除き、表面エ
ッチ後ゲート酸化を行りてゲート絶縁膜（厚さ８００Ａ
）を形成する。この後、ゲート絶縁膜４を通してＢイオ
ン打込みし、チャネル部となるｎ−型層１３直下のＳｉ
基体内に深く高濃度に導入したＢをアニールにより拡散
して第８図に示すようにｐ＋型領領域９高圧酸化膜で囲
まれた領域内にセルファラインで形成する。(5) Remove the Si''N4 film on the channel part, perform gate oxidation after surface etching, and remove the gate insulating film (thickness: 800A).
) to form. After that, B ions are implanted through the gate insulating film 4, and Si
B is introduced deeply into the substrate at a high concentration and is diffused by annealing to form a p+ type region 9 in a region surrounded by a high-pressure oxide film in a self-aligned manner as shown in FIG.
この後、ソース−ドレイン表面のコンタクトホトエッチ
を行いＡ感（アルミニウム）を蒸着しノくターニングす
ることにより第３図に示すような電極Ｓ、Ｄを有するｎ
チャネ、ｒｙＭＱｓＦＥＴを完成するＯ
第１０図〜第１４図は本発明の他の一実施例であって、
テプレツションモードｎチャネｙｖ Ｍ Ｏ５ＦＥＴの
製造プロセスを示す工程断面図である。After that, contact photoetching is performed on the source-drain surface, and A-type (aluminum) is deposited and then turned to form electrodes S and D as shown in FIG.
10 to 14 show another embodiment of the present invention,
FIG. 3 is a process cross-sectional view showing a manufacturing process of a depression mode n-channel YV MO5FET.
各工程は下記のように行われる。Each step is performed as follows.
（１） 第１０図に示すようにｐ−型Ｓｉ基体１の一主
表面上に薄℃□・酸化膜（ｓｉｏ、 ｌ１ｆｆ、）’
２を介してナイトライド膜（Ｓｉ、Ｎ、膜）１４を形成
したものを用意する。(1) As shown in FIG. 10, a thin ℃□・oxide film (sio, l1ff, )' is formed on one main surface of the p-type Si substrate 1.
A nitride film (Si, N, film) 14 formed thereon via 2 is prepared.
（２）第１１図に示すようにホトレジスト処理により上
側のＳｉ、Ｎ４膜１４の一部を窓開し、Ｐ（リン）をイ
オン打込みしてＳｉＱ、膜１２を通してＳｉ基体表面に
Ｐを導入しアニールすることによりｎ＋型領領域１６形
成する。(2) As shown in FIG. 11, a part of the upper Si, N4 film 14 is opened by photoresist treatment, and P (phosphorus) is ion-implanted to introduce P into the Si substrate surface through the SiQ film 12. By annealing, an n+ type region 16 is formed.
＋
（３１５１ｓＮ４膜をマスクにして高圧酸化を行ってｎ
型領域１６の上に厚い酸化膜８を形成した後、第１２図
に示すようにソース−ドレインとなる領域上にホトレジ
スト等によるマスク１７を形成した状態で高濃度Ｂ（ボ
ロン）をイオン打込みしＳｉＱ。+ (N
After forming a thick oxide film 8 on the mold region 16, as shown in FIG. 12, high concentration B (boron) is ion-implanted with a mask 17 made of photoresist or the like formed on the region that will become the source-drain. SiQ.
膜１２を通してｐ−型基体内に深くＢを導入する。B is introduced deeply into the p-type substrate through the membrane 12.
（４）アニールすることによりｐ−型基板１内のＢを拡
散してｐ＋型領領域９形成する。この後、第１３図に示
すようにＳｉをデポジットしてポリＳｉ層１８を形成し
、ホトエッチすることによりポリＳｉゲート１８を形成
する。(4) By annealing, B is diffused in the p − type substrate 1 to form a p + type region 9 . Thereafter, as shown in FIG. 13, Si is deposited to form a poly-Si layer 18 and photo-etched to form a poly-Si gate 18.
（５）厚い酸化膜８及びポリＳｉゲート１８をマスクと
してＰ（リン）をイオン打込み、アニールして第１４図
に示すように基体表面にｎ＋型領領域２３を拡散しセル
７アラインでソースｌドレインを形成する。(5) Using the thick oxide film 8 and poly-Si gate 18 as a mask, P (phosphorus) is ion-implanted and annealed to diffuse an n+ type region 23 on the substrate surface as shown in FIG. Form a drain.
この後、全面にＰＳＧ（リン・シリケートガラス）膜（
図示されない）を形成し、コンタクトホトエッチの後、
Ａ［を蒸着しバター二／グすることによりｎチャネルＭ
Ｏ８ＦＥＴを完成する。After this, PSG (phosphorus silicate glass) film (
(not shown) and after contact photoetch,
n-channel M by evaporating and buttering A[
Complete O8FET.
以上実施例により説明した本発明によれば、下記の効果
が得られる。According to the present invention explained in the examples above, the following effects can be obtained.
（１） ソース・ドレイン端、又は少なくともドレイン
端とゲート電極との間に高圧酸化による厚い酸化膜を形
成することによりゲート・ドレイ／容量を小さくするこ
とができ高周波特性ｆＴを向上することができる。(1) By forming a thick oxide film by high-pressure oxidation between the source/drain end, or at least between the drain end and the gate electrode, the gate/drain/capacitance can be reduced and the high frequency characteristics fT can be improved. .
（２）チャネル部直下に基体と同じ導電型のｐ＋型領領
域形成したことにより、空乏層のバンチスルーを抑え、
飽和特性を向上できる。(2) By forming a p+ type region of the same conductivity type as the substrate directly under the channel part, bunch-through of the depletion layer is suppressed,
Saturation characteristics can be improved.
（３） ソース−ドレイン端とゲート電極との間に形成
した厚膜酸化膜をマスクとして基体内深く不純物を導入
することにより、チャネル部直下に基体と同じ導電型高
濃度領域をセルファラインで形成することかでき、ショ
ートチャネルＭＯ８ＦＥＴであってショートチャネル効
果を低減することができる。第９図はゲート長りとソー
ス・ドレイン電圧■Ｄ８との関係を示し、実線はチャネ
ル下にｐ＋領領域形成する本発明のＭＱ Ｓ Ｆ ＥＴ
の場合、破腺はチャネル下にｐ＋領領域形成しない場合
のＶＤ８曲線を示す。(3) By introducing impurities deep into the substrate using the thick oxide film formed between the source-drain end and the gate electrode as a mask, a high concentration region of the same conductivity type as the substrate is formed directly under the channel region using self-line. It is a short channel MO8FET and can reduce the short channel effect. FIG. 9 shows the relationship between gate length and source/drain voltage D8, and the solid line represents the MQ SFET of the present invention in which a p+ region is formed under the channel.
In this case, the gland shows a VD8 curve when no p+ region is formed under the channel.
（４）チャネル部直下に基体と同じ導電型のｐ４−型領
域を形成したことより、この部分の比抵抗が低下し、降
伏電圧を向上できる。(4) Since a p4-type region of the same conductivity type as the substrate is formed directly under the channel portion, the specific resistance of this portion is lowered and the breakdown voltage can be improved.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
本発明は、ショートチャネルＭＱＳＦＥＴを有するＩＣ
（ＬＳＩ）の全てに適用でき、特にメモリ、ＭＱＳオペ
アンプ用のＩＣ（ＬＳＩ）に応用して有効である。The present invention provides an IC with a short channel MQSFET.
(LSI), and is particularly effective when applied to ICs (LSI) for memory and MQS operational amplifiers.
第１図はショートチャネルＭＯ８ＦＥＴの一例を示す断
面図である。
第２図はＭＱＳＦＥＴにおけるショートチャネル効果を
示すｖＤｓ’８Ｄ特性を示す曲線図である。
第３図は本発明の一実施例であってショートチャネルＭ
Ｏ８ＦＥＴの原理的構造を示す断面図である。
第４図〜第８図は本発明の一実施例であってＭＱＳＦＥ
Ｔの製造プロセスを示す工程断面図である。
第９図は、ショートチャネルＭＱＳＦＢＴにおけるゲー
ト長とソース・ドレイン電圧との関係を示す曲線図であ
る。
第１０図〜第１４図は、本発明の他の一実施例であって
、Ｍ□５ＦＥＴの製造プロセスを示す工程断面図である
。
１・・・ｐ型Ｓｉ基体、２・・・ソースｎ＋型領域、３
・・・ドレインｎ＋型領域、４・・・ゲート絶縁膜（Ｓ
ｉＱ。
膜）、５・・・ゲート電極、６・・・チャネル部、７・
・・空乏層、８・・・厚膜絶縁膜、９・・・高濃度ｐ＋
型型埋領領域１０．１１・・・Ｓｉ、Ｎ４膜、１２・・
・酸化膜、１３・・・チャネル部ｎ−型層、１４・・・
Ｓｉ、Ｎ、膜、１５・・・フィールド酸化膜、１６・・
・ｎ＋型領領域１７・・・ホトレジストマスク、１８・
・・ポリシリコンゲート。
第 １ 図
第 ２ 図
Ｄ３
第 ３ 図
第 ４ 図
第 ７ 図FIG. 1 is a cross-sectional view showing an example of a short channel MO8FET. FIG. 2 is a curve diagram showing vDs'8D characteristics showing the short channel effect in MQSFET. FIG. 3 shows an embodiment of the present invention, in which the short channel M
1 is a cross-sectional view showing the basic structure of an O8FET. FIG. 4 to FIG. 8 show an embodiment of the present invention, in which MQSFE
It is a process sectional view showing the manufacturing process of T. FIG. 9 is a curve diagram showing the relationship between gate length and source/drain voltage in a short channel MQSFBT. FIGS. 10 to 14 are process cross-sectional views showing the manufacturing process of an M□5FET, which is another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2...source n+ type region, 3
...Drain n+ type region, 4...Gate insulating film (S
iQ. membrane), 5... gate electrode, 6... channel part, 7...
...Depletion layer, 8...Thick film insulating film, 9...High concentration p+
Mold buried region 10.11...Si, N4 film, 12...
- Oxide film, 13... Channel part n-type layer, 14...
Si, N, film, 15...field oxide film, 16...
・N+ type region 17...photoresist mask, 18・
...Polysilicon gate. Figure 1 Figure 2 Figure D3 Figure 3 Figure 4 Figure 7
Claims (1)
の領域がソース・ドレインとして形成され、このソース
・ドレイン間の半導体基体表面をチャネル部としてその
上に絶縁膜を介してゲート電極が形成された絶縁ゲート
電界効果トランジスタを有する半導体装置であって、上
記ゲート電極が形成された絶縁膜の少な（ともドレイン
と接する部分は選択酸化により形成された厚膜であると
ともに、チャネル部直下の半導体基体内に基体と同じ導
電型の高濃度埋込領域が形成されていることを特徴とす
る絶縁ゲート半導体装置。 ２、半導体基体は低濃度ｐ型シリコンからなり、ソース
・ドレインとなる半導体領域は高濃度ｎ型領域である特
許請求の範囲第１項に記載の絶縁ゲート半導体装置。 ３、半導体基体の一主表面に基体の導電型と逆の導電型
の領域をソース、ドレインとして形成する工程と、上記
ソース、ドレインにはさまれた基体の表面上に半導体酸
化膜を介してゲート電極を形成する工程とを含む絶縁ゲ
ート半導体装置の製造法であって、ゲートとソース、ド
レインとなる領域の間に選択酸化による厚膜酸化膜を形
成し、この厚膜酸化膜をマスクとしてソース・ドレイン
間の基体内に高濃度の不純物を導入し、基体と同じ導電
型の高濃度埋込領域を形成することを特徴とする絶縁ゲ
ート半導体装置の製造法。 ４、上記厚膜酸化膜は半導体基体表面上に部分的に形成
した半導体窒化膜をマスクとして半導体基体表面の一部
を高圧酸化することにより選択的に形成する特許請求の
範囲第３項に記載の絶縁ゲート半導体装置の製造法。[Claims] 1. A region having a conductivity type opposite to that of the substrate is formed on one main surface of a semiconductor substrate as a source/drain, and the surface of the semiconductor substrate between the source and drain is used as a channel portion on top of the main surface. A semiconductor device having an insulated gate field effect transistor in which a gate electrode is formed through an insulating film, wherein a portion of the insulating film on which the gate electrode is formed (in both cases, the portion in contact with the drain is a thick film formed by selective oxidation). An insulated gate semiconductor device characterized in that a heavily doped buried region of the same conductivity type as the base is formed in the semiconductor base directly under the channel portion. 2. The semiconductor base is made of low concentration p-type silicon. , the insulated gate semiconductor device according to claim 1, wherein the semiconductor regions serving as sources and drains are highly doped n-type regions. 3. A semiconductor substrate having a conductivity type opposite to that of the substrate on one main surface of the semiconductor substrate. A method for manufacturing an insulated gate semiconductor device, comprising the steps of forming regions as a source and drain, and forming a gate electrode on the surface of a base sandwiched between the source and drain via a semiconductor oxide film, the method comprising: , a thick oxide film is formed by selective oxidation between the gate and the regions that will become the source and drain, and using this thick oxide film as a mask, high concentration impurities are introduced into the substrate between the source and drain. A method for manufacturing an insulated gate semiconductor device characterized by forming a conductive type high concentration buried region. 4. The thick oxide film is formed on the semiconductor substrate using a semiconductor nitride film partially formed on the surface of the semiconductor substrate as a mask. 4. The method of manufacturing an insulated gate semiconductor device according to claim 3, wherein the insulated gate semiconductor device is selectively formed by high-pressure oxidation of a part of the surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12763883A JPS6020578A (en) | 1983-07-15 | 1983-07-15 | Insulated gate semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12763883A JPS6020578A (en) | 1983-07-15 | 1983-07-15 | Insulated gate semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020578A true JPS6020578A (en) | 1985-02-01 |
Family
ID=14965044
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12763883A Pending JPS6020578A (en) | 1983-07-15 | 1983-07-15 | Insulated gate semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020578A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0374068U (en) * | 1989-11-15 | 1991-07-25 | ||
| US7301241B2 (en) * | 2002-07-31 | 2007-11-27 | Fujitsu Limited | Semiconductor device for preventing defective filling of interconnection and cracking of insulating film |
-
1983
- 1983-07-15 JP JP12763883A patent/JPS6020578A/en active Pending
Cited By (30)
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