JPS63292679A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To suppress the injection of hot carriers into a sidewall layer and to obtain a highly reliable MOS transistor, by forming a first diffused region in a substrate, forming a first sidewall layer comprising an insulating film, forming a metal silicide layer on a gate electrode and the first diffused region, and forming a second sidewall layer furthermore. CONSTITUTION:A shallow low concentration diffused region 5 is formed in a substrate 1 by ion implantation and the like, Thereafter, a thin insulating film 9 is formed on the entire surface. The insulating film 9 is etched by RIE. A first sidewall layer 9 is made to remain on the side surfaces of a gate electrode 2 and a gate insulating film 3. Then, heat treatment is performed, and a metal silicide layer 7 are formed on the part of the gate electrode 2 (only in the case of polysilicon) and source and drain regions 10 and 11. Thereafter, the metal at a non-reacted part is removed. An insulating film is formed. RIE is carried out immediately, and a second sidewall layer 8 is formed on the side surface of the first sidewall layer 9. A deep high-concentration diffused region 4 (second diffused region) is formed in the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a MOS transistor.

[Conventional technology]

FIG. 2 shows the cross-sectional structure of a conventional MOS transistor, in which 1 is a substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a high concentration diffusion region (toilet region 11), 1
0 is the source area.

In a MOS transistor with this structure, as the gate length L1 becomes shorter due to the progress of miniaturization, bunch-through phenomenon occurs.
A characteristic deterioration phenomenon of a decrease in threshold voltage (vth) occurred. Further, the reduction in the effective channel length L2 due to the deep diffusion depth XJ of the high concentration diffusion region 4 further promoted the deterioration of the characteristics.

The transistor shown in FIG. 3 has been proposed for the purpose of suppressing such characteristic deterioration.
It has an extremely doped drain structure.

That is, in this transistor, after forming the gate electrode 2, a shallow low concentration diffusion region 5 with a relatively low impurity concentration is formed.
is formed, and then CVD ((:chemical Vap
An insulating film is then formed using a method such as RI E (Reactive!
A sidewall layer 8 is formed by performing a process (n+ijching), and then a high impurity concentration diffusion region 4 is formed.

In this structure, the low concentration diffusion region 5 suppresses electric field concentration in the vicinity of the drain, and the actual channel length is difficult to shorten, so that the above problem does not occur.

However, the charges (carriers) traveling from the source region 10 side obtain maximum energy near the train region 11 and then have to pass through the low concentration diffusion region 5. At this time, the charges (carriers) that have obtained sufficient energy (Hot carriers) are injected into the id wall layer 8 with a certain probability (13 in the figure). Note that 12 is a traveling carrier path. This causes changes in the reliability and characteristics of the transistor.

In order to suppress such a phenomenon peculiar to the LDD structure, the concentration of the low concentration diffusion region 5 is slightly increased to
(Moderately Lightly Doped
Drain) WI structure, or as shown in FIG. 4, a medium concentration diffusion region 6 is provided below a low concentration diffusion region 5.
A method such as a DD (Illuried LDD) structure has been adopted.

[Problem that the invention seeks to solve]

However, even in these structures, an electric field exists at the interface between the sidewall layer 8 and the drain region 11, and since there is a relatively high resistance layer directly under the sidewall layer 8, hot carriers in the sidewall layer 8 injection is not completely suppressed.

This invention was made in order to solve the above-mentioned problems, and it is possible to suppress injection of hot carriers into the sidewall layer, and therefore, it is possible to suppress the injection of hot carriers into the sidewall layer.
It is an object of the present invention to provide a method for manufacturing an S transistor by which an S transistor can be obtained.

[Means for solving problems]

The method for manufacturing a MOS transistor according to the present invention includes the following six steps.

1) Forming a gate insulating film and a gate electrode on the substrate 2) Forming a first diffusion region on the substrate 3) Forming a first sidewall layer made of an insulating film on the sides of the gate insulating film and gate electrode 4) Forming a metal silicide layer on the gate electrode and the first diffusion region 5) Forming a second sidewall layer made of an insulating film on the side surface of the first sidewall layer 6) Forming a metal silicide layer on the substrate Step of Forming the Second Diffusion Region [Operation] According to the present invention, the metal silicide layer is formed directly under the sidewall layer, so that the metal silicide layer forms the interface between the sidewall layer and the drain region. An extremely low-resistance layer is formed on the sidewall layer, which helps hot carriers travel to the drain region and suppresses injection of hot carriers into the sidewall layer.

At the same time, this metal silicide layer forms an equipotential surface directly under the sidewall layer, relaxes the electric field directly under the sidewall layer, gives energy to hot carriers near the drain region, and transfers the hot carriers to the sidewall layer. injection is suppressed.

〔Example〕

Hereinafter, a manufacturing method according to an embodiment of the present invention will be explained in order of steps with reference to FIG. Note that the same or equivalent parts as in FIG. 3 are given the same reference numerals.

(1) First, a gate insulating film 3 and a polysilicon or metal gate electrode pi2 are formed on one part of the substrate 1 using techniques such as thermal oxidation, CVD, photolithography, etching, etc. (Fig. 1(a) )).

(2) After forming a shallow low-concentration diffusion region 5 (first diffusion region) on the substrate l by ion implantation or the like, a thin insulating film 9 is formed over the entire surface (preferably with the same thickness as the gate insulating film 3). (Fig. 1(b)).

(3) This insulating film 9 is etched by RIE to leave it as a first sidewall layer 9 on the 1ilJ plane of the gate electrode 2 and gate insulating film 3 (FIG. 1(C)).

(4) Titanium (Ti), dried buden (Mo), platinum (p
A metal film 14 forming a silicide compound such as t) is formed over the entire surface (FIG. 1(d)).

(5) Immediately thereafter, heat treatment is applied to the gate electrode 2 portion (only in the case of polysilicon) and the source and train regions 10.
A metal silicide layer 7 is formed on 11, and then the metal in unreacted portions is removed (FIG. 1(e)).

(6) After forming the insulation 11i, RIE is immediately performed to form the second sidewall layer 8 on the side surface of the first sidewall layer 9 (FIG. 1(f)).

(7) Form a deep high concentration diffusion region 4 (second diffusion region) in the substrate 1 (FIG. 1(g)).

(8) Remove the metal silicide layer 7 except directly under the sidewall layer 8 (FIG. 1(h)).

In addition, as shown in FIG. 1(i), the sidewall layer 8
Directly below and Kate 7? The metal silicide layer 7 other than the f-pole 2 can be removed, or the metal silicide layer 7 other than the source and train regions 10.degree. 11 can be removed as shown in FIG. 1(j).

Note that this step is performed as necessary.

(9) Thereafter, an integrated circuit is formed by performing metal wiring and forming a final protective film (not shown).

As mentioned above, in this embodiment, the metal silicide layer 7 is formed directly under the sidewall layer 8, and this layer 7 is formed between the sidewall layer 8 and the drain region 11.
An extremely low-resistance layer is formed at the interface to help hot carriers travel to the drain region 11. Therefore, injection of hot carriers into the sidewall layer 8 is suppressed.

At the same time, the metal silicide layer 7 forms an equipotential surface directly under the sidewall layer 8, and by relaxing the electric field directly under the sidewall layer,
It functions so as not to give energy to hot carriers in the vicinity. Therefore, in this respect as well, injection of hot carriers into the sidewall layer 8 is suppressed.

〔Effect of the invention〕

As described above, according to the present invention, since a low resistance metal silicide layer is formed directly under the sidewall layer,
Injection of hot carriers into the sidewall layer can be suppressed, and therefore a highly reliable MOS transistor can be obtained.

[Brief explanation of drawings]

FIGS. 1A to 1J are cross-sectional views for explaining the manufacturing process of a MOS transistor according to an embodiment, and FIGS. 2 to 4 are cross-sectional views of a conventional MOS transistor. 1 is a substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a high concentration diffusion region (second diffusion region), 5 is a low concentration diffusion region (first diffusion region), 8 is a second sidewall layer, 9
is a first sidewall layer, IO is a source region, and 11 is a drain region. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1) Step of forming a gate insulating film and a gate electrode on the substrate 2) Step of forming a first diffusion region on the substrate 3) Step of forming a first diffusion region on the side surfaces of the gate insulating film and the gate electrode 4) Step of forming a metal silicide layer on the gate electrode and the first diffusion region 5) Forming a second sidewall layer made of an insulating film on the side surface of the first sidewall layer Step 6) Forming a second diffusion region on the substrate A MOS characterized by having the steps 1) to 6) above.
Method of manufacturing transistors.