JPS60136376A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent mutual conductance among elements from reduction and improve the performance characteristics thereof in an MISFET of an LDD structure by a method wherein source/drain regions are made of a first, second, third layers diffused with different density of impurities. CONSTITUTION:A field insulating film 4 and thin oxide film 5 are selectively formed on the surface of a substrate. A polycrystalline Si layer 6 to act as gate is given treatment to be ready to serve as a conductive layer and is subjected to etching for the oxidation of its surface. An N type impurity, typically P, is injected into the oxidized surface. Next, an SiO2 film is deposited to cover the entire surface. The SiO2 film is exposed to anistropic etching for the formation of a side wall 8, composed of retained SiO2 film, on the sides of the gate 6. In a following process for the formation of an N<+> type impurity layer 2, the side wall 8 and gate electrode 6 serve as a mask for the introduction of an N type impurity into the Si substrate. The source/drain layers are constituted of three impurity-diffused layers, that is, an N<+> type layer 2, N<-> type layer 12, and an N<--> type layer 3.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to the structure of a semiconductor device, and in particular to the structure of a semiconductor device.
D (Light; Doped Drain) structure insulated gate field effect transistor (hereinafter referred to as MISFFT)
It relates to techniques that are effective when applied to

[Background technology]

In a semiconductor device having an M I S FET, the impurity concentration gradient of the source/drain layer having a conductivity type opposite to that of the substrate becomes steep from the electrode end portion to the electrode end portion, and the electric field is concentrated in this portion. This causes generation of hot carriers that deteriorate device characteristics. A technology to prevent the generation of hot carriers was developed in 1982 by Sun+p.
VLSI Technol.

Digest of Technical Paper
s, page 42. This is a traditional source
In addition to the drain layer, an impurity layer with a lower concentration than the source/train layer is formed near the relatively shallow gate end surface [hereinafter referred to as L D D (Lig++t: Do
pedDrain). If a low concentration region is formed at the end of the gate 1, the electric field will be less concentrated and the generation of hot carriers will be suppressed. A concrete example of such a technique is shown in FIG.

In FIG. 1, a gate electrode 6 and source/drain layers are formed in a region defined by a field insulating film 4 on a semiconductor substrate 1. The source train layer is N
It is formed of two layers: a 4 impurity layer 2 and an N- impurity layer 3. In the technique of such a structure, the low concentration impurity layer 3 is formed to protrude a certain length in the direction of the gate electrode.

Therefore, it is possible to reduce the electric field concentration in the source/drain layer at the end of the gate. Therefore, compared to the case where the source/drain layer is formed only with the impurity layer 2, the generation of hot carriers can be sufficiently prevented.

However, the present inventor discovered that the source/drain layer of the above structure has the following serious drawbacks. In other words, since the presence of the low concentration impurity layer 3 protrudes by an amount Q toward the goo 1- side, the resistance becomes high by the area Q, and the MI
The transconductance (g m ) of the SFET deteriorates. Therefore, there is a problem in that the operating speed of the device is greatly affected.

[Purpose of the invention]

The object of the present invention is to provide a MISFET having an LDD4i1 structure.
An object of the present invention is to provide a technique for preventing a decrease in mutual conductance (gm) and improving device characteristics.

Another object of the present invention is to provide an MIS system that prevents hot carriers.
The purpose of the present invention is to provide a technology having a FET structure.

Another object of the present invention is to provide a technique for preventing short channel effects in MISFETs.

Another object of the present invention is to provide an effective technique for miniaturizing elements.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the source/drain regions are formed by three impurity layers: a first impurity layer, a second impurity layer, and a third impurity layer with different impurity concentrations.
By making the impurity distribution at both ends of the gate electrode gentle, the region of the high-resistance, low-concentration impurity layer can be made small, and the transconductance (gm
) to improve.

This improves device characteristics.

〔Example〕

An embodiment according to the present invention will be described below.

FIG. 2 is a sectional view of a MISFET showing an embodiment of the present invention.

On the P-type silicon semiconductor substrate 1, each MISFE
A field insulating film 4 made of silicon oxide (SiO□) is formed to isolate the T, and the active region is partitionedly surrounded by the field insulating film.

MI S FETQ+ exists. MI 5FETQ*
A gate 6 made of polysilicon and a gate insulating film 5 made of SiO□ which insulates the substrate 1 and the gate 6 are formed. The N-type source/drain region is 2 (N
It consists of three layers, 3 (N + layer), 3 (N single layer), and 12 (N single layer), and each has an aluminum wiring 10 and a through hole 1.
4, making ohmic contact. Also, gate 6
is covered and protected by a 5iO7 film 7 and a sidewall 8 made of SiO□. 9 is an interlayer insulating film 1
0 is the final passivation film.

The present invention is characterized in that the source/drain layer is formed of three layers: an N4 type impurity layer 2, an N- type impurity layer 12, and an N- type impurity layer 3. The N- type impurity layer 12 is formed so as to surround the N4 type impurity layer 2, and the N- type impurity layer 3 is formed at the end of the electrode 1.
A mold that protrudes the impurity layer and is formed near the surface of the substrate. What is the concentration difference in the impurity layer?

N">N->N-1. What differs from the one in FIG. 1 is the N- type impurity layer 12.
is formed between the N+ type impurity layer 2 and the N− type impurity layer 3. Therefore, the concentration distribution of the source/drain layer increases in the order of N- type impurity layer 3, N- type impurity layer 12, and N3 type impurity layer 2. Since the long low concentration region α indicated by Q as shown in FIG. 1 does not exist in the present invention, it does not become a high resistance region and the mutual conductance (gm) of M I S F E T Q * does not decrease.

The impurity concentration distribution of the source/drain regions according to the present invention can be explained in detail as shown in the graph (channel direction position vs. impurity concentration distribution graph from the gate end) in FIG. The solid line indicates MI in the present invention.
This is the source/drain impurity concentration distribution of SFETQs. The dotted line is the source-train impurity concentration distribution of the MISFET having the LDD structure shown in FIG. M I S F E T Q in the present invention
Due to the presence of the N''-type impurity layer 12, the distribution of * is formed in such a way that the shape is less steep in the center and overall less steep than the curve of the LDD structure shown by the dotted line. As shown by the one-dot line, low concentration regions such as the (,) region are reduced.As a result, an appropriate concentration distribution with no bias in the concentration gradient can be obtained. There is almost no resistance region.Therefore, deterioration of mutual fundance (gm) is suppressed, and deterioration of device operating speed is also eliminated.

The manufacturing method of the present invention will be explained below with reference to FIGS. 3 to 7.

First, a P-conductivity type silicon substrate I having a (100) plane is prepared.
A field insulating film 4 is selectively formed on the surface of the substrate using a well-known technique. After forming a thin oxide film 5 to serve as a gate insulating film 5 and making the polysilicon layer to be a gate insulating film conductive in the area defined by the gate insulating film 4, etching is performed using a well-known technique. , by oxidizing its surface.

Form as shown in Figure 3. Then, N- as shown in FIG.
In order to form the type impurity layer (first impurity layer) 3, N
A type impurity, for example, phosphorus (P) is applied at an energy of about 50 KeV and a dose of about 1×1 using the gate electrode 3 as a mask.
Introduce it by hammering it in at about 2/cm. 13 areas are N
This is the part where type impurities are introduced. In this case, N-type impurities are introduced through the thin oxide film 5 to protect the silicon substrate surface.

Next, after depositing a 5in2 film with a thickness of about 400OA over the entire surface, the Si0° film was anisotropically etched.
A sidewall 8, which is the residue of the Si0° film, is formed on the side surface of the gate 6. Next, after depositing a thin SiO□ film 15 in the region where the source/drain will be formed, in order to form the N- type impurity layer 12 shown in FIG. 2 using the sidewall 8 and gate electrode 6 as a mask, N-type impurity,
For example, when phosphorus (P) is implanted, the energy is about 50 KeV,
The ion implantation layer 13 is introduced into the substrate at a dose of approximately 1.times.I O"/cJ. Of the ion implantation layer 13 shown in FIG. 4, the one indicated by the short dotted line becomes the N" type impurity N12. N because sidewall 8 is used as a mask
- Impurity layer implanted to form type impurity layer 3 (
It is distributed in a narrower area than the dotted line extending to game 1-6). After introducing impurities as described above, a high temperature diffusion treatment is performed to stretch out the introduced impurities.

The structure thus formed is as shown in FIG.

Thereafter, in order to form an N+ type impurity N2, an N type impurity is similarly introduced into the silicon substrate using the sidewall 8 and gate electrode 6 as a mask. N+
As shown in FIG.
It must be formed so that it exists inside of 2 and has a higher concentration. Therefore, N-type impurity layer 12 has a smaller diffusion coefficient than the impurity for forming the N-type impurity layer 12.
A type impurity, for example arsenic (, As), is introduced. Arsenic is implanted with an energy of approximately 80 KeV and a dose of 5X.
It is implanted under conditions of about 10"/cJ, and is appropriately diffused by high temperature treatment to form a shape as shown in FIG. 6.

In this way, the source/drain layers are doped with N3 type impurities [2, N- type impurities N12 . It is formed by three layers of N- type M3. The N- type layer 12 and the N+ type layer 2 are formed in this order so that the concentration increases gradually. Therefore, the generation of hot carriers at the edge of the gate is significantly reduced, and the number of high resistance regions is reduced, so deterioration of mutual conductance can be prevented and device characteristics can be improved.

After forming as described above, a glabellar insulating film 9 is formed of phosphosilicate glass (PSG) or the like, and contacts 1 to holes 14 are formed as shown in FIG. Thereafter, a final passivation film 11 is formed on the aluminum wiring 14° using a well-known technique, and the structure is completed as shown in FIG.

〔effect〕

(1) In the present invention, the source/drain layer is formed from three layers: an N-1 type impurity layer, an N- type impurity layer, and an N+ type impurity layer, so that the impurity concentration gradient at the gate edge becomes gentle. , fti field concentration can be prevented, so it is possible to significantly reduce the generation of hot carriers.

(2) Similar to (1) above, since the impurity concentration gradient is gentle and there are few high resistance regions, deterioration of the mutual inductance (g m ) of MISFE 1 can be prevented. Therefore, the operating speed is improved.

(3) Since the sidewalls formed on the sides of the gate 1 are used to form the N- type impurity layer and the N+ type impurity layer, a short channel effect (a phenomenon in which the channel becomes shorter than the actual gate III) ) can be prevented.

(4) Since the short channel effect can be prevented, it is possible to realize fine introduction of the element.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, gate 6 may be silicide or metal, and furthermore, A, Q
The wiring may be made of other metals. Furthermore, as the interlayer insulating film and the final passivation film, Si0□ or the like can be used in addition to PSG.

[Application field]

The above explanation will mainly focus on the invention made by the present inventor and the field of application in which it is based.
Although the case where it is applied to a T semiconductor device has been described, it is not limited thereto, and for example, a complementary MISFE device.
It can be applied to T, bipolar complementary MISFET, etc.

[Brief explanation of drawings]

FIG. 1 shows an M having an LDD structure, which is the premise of the present invention.
FIG. 2 is a cross-sectional view of an MI S FET showing an embodiment of the present invention; FIGS. 3 to 7 are cross-sectional views showing manufacturing steps of a MI S FET according to the present invention; FIG. FIG. 8 is a graph showing the position in the channel direction from the gate end and the impurity concentration distribution. DESCRIPTION OF SYMBOLS 1... P- type semiconductor substrate, 2... N+ type source/drain layer, 3... N- type source/drain layer, 4...
・Field insulation n! (Si0□), 5...Gate insulating film (Sin2), 6...Goo 1~insulating film (polysilicon), 7...Ge-1, silicon oxide film for protection (Sin2), 8...・・Side wall (Si0□
), 9... Interlayer insulating film (PSG), IO... Aluminum wiring, 11... Final passivation film, 12... N- type source/drain layer, 13...
Arsenic implant layer, 14...Hole to contact 1, 15
...Silicon oxide film (Sin2) for substrate protection Fig. 1 Fig. 2 Fig. ρl Fig. 3 (transfer) Fig. 6 Fig. 7 Fig. 8

Claims (1)

[Claims] A semiconductor device characterized in that a source/drain layer is made up of three impurity layers: an equal number of 16 impurity layers with different impurity concentrations, a second impurity layer, and a third impurity layer. . 2. The semiconductor device according to claim 1, wherein the first impurity layer, the second impurity layer, and the third impurity layer are of a conductivity type opposite to that of the semiconductor substrate. 3. The semiconductor device according to claim 1 or 2, wherein the concentration of the impurity layer increases in the order of the first impurity layer, the second impurity layer, and the third impurity layer. 4. The semiconductor device according to claim 1, 2, or 3, wherein the second impurity layer is present so as to cover the third impurity layer. 5. A part of the first impurity layer is connected to the second impurity layer at the gate end.
The semiconductor device according to claim 1, 2, 3, or 4, wherein the semiconductor device extends to the outside of the impurity layer. 6. A field insulating film on the first conductivity type semiconductor substrate;
After forming the gate insulating film and the polysilicon layer of the gate 1, a step of introducing a first impurity of a second conductivity type opposite to that of the semiconductor substrate using the polysilicon layer as a mask; A process of forming a sidewall on the side,
A step of introducing a second impurity of a second conductivity type using the sidewall as a mask, a step of forming a first impurity layer from the introduced first impurity, and a step of forming a second impurity layer from the introduced second impurity. a step of introducing a third impurity of a second conductivity type using a sidewall as a mask; and a step of forming a third impurity layer from the introduced third impurity. Method of manufacturing the device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the first impurity is phosphorus. 8. The method of manufacturing a semiconductor device according to claim 6 or 7, wherein the second impurity is phosphorus. 9. The method for manufacturing a semiconductor device according to claim 6, 7, or 8, wherein the third impurity is arsenic. 10. Claims 6 and 7, characterized in that the third impurity has the largest amount, followed by the second impurity, and then the first impurity. Item 8 or a method for manufacturing a semiconductor device according to Item 8.