JPH0789587B2 - Insulated gate field effect transistor and manufacturing method thereof - Google Patents
Insulated gate field effect transistor and manufacturing method thereofInfo
- Publication number
- JPH0789587B2 JPH0789587B2 JP60296001A JP29600185A JPH0789587B2 JP H0789587 B2 JPH0789587 B2 JP H0789587B2 JP 60296001 A JP60296001 A JP 60296001A JP 29600185 A JP29600185 A JP 29600185A JP H0789587 B2 JPH0789587 B2 JP H0789587B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain region
- source region
- source
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000002265 prevention Effects 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- -1 boron ions Chemical class 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、絶縁ゲート型の電界効果トランジスタ（以
下、FETという）の構造およびその製造方法に関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a structure of an insulated gate field effect transistor (hereinafter referred to as FET) and a manufacturing method thereof.
例えば、従来のLDD（lightly doped drain）nMOS FETの
構造およびその製造方法を第２図を参照しながら説明す
る。For example, a structure of a conventional LDD (lightly doped drain) nMOS FET and a manufacturing method thereof will be described with reference to FIG.
まず、５Ω−cmのＰ型シリコン基板１の表面に熱酸化膜
２を約200Åの厚みに形成し、その上に燐ドープト多結
晶シリコン３を4000Å程度堆積し、これを写真蝕刻法等
によりパターニングしてゲート電極を形成する（同図
（ａ））。その後、ボロンイオンおよびリンイオンを基
板１へイオン注入してパンチスルー防止用のP-層４およ
びn-層５を形成する（同図（ｂ））。次に、全表面にCV
D二酸化シリコン６を3000Å程度堆積し、これをRIEでエ
ッチングして、多結晶シリコン３の側壁のみに二酸化シ
リコン６を残す（同図（ｃ））。次に、ゲート耐圧向上
のため、多結晶シリコン３を酸化した後、ひ素をイオン
注入してここにソース・ドレイン各領域となるn+層７を
形成し、これでLDD nMOS FETが出来上がる（同図
（ｄ））。First, a thermal oxide film 2 having a thickness of about 200 Å is formed on the surface of a 5 Ω-cm P-type silicon substrate 1, and about 4000 Å phosphorus-doped polycrystalline silicon 3 is deposited thereon, and this is patterned by a photo-etching method or the like. Then, a gate electrode is formed ((a) in the same figure). After that, boron ions and phosphorus ions are ion-implanted into the substrate 1 to form punch-through preventing P - layers 4 and n - layers 5 (FIG. 7B). Next, CV on all surfaces
D About 3000 Å of silicon dioxide 6 is deposited, and this is etched by RIE to leave the silicon dioxide 6 only on the side wall of the polycrystalline silicon 3 (FIG. 2C). Next, in order to improve the gate breakdown voltage, the polycrystalline silicon 3 is oxidized, and then arsenic is ion-implanted to form the n + layers 7 which will be the source and drain regions, respectively, thereby completing the LDD nMOS FET. Figure (d)).
かかる構造のLDD FETは、チャネル部の不純物濃度が低
く、かつソース・ドレイン両領域付近のＰ型不純物の濃
度は高いため（P-層４）、しきい値電圧の基板バイアス
効果を抑え、かつパンチスルー耐圧も高い等の多くの利
点を有する。Since the LDD FET having such a structure has a low impurity concentration in the channel portion and a high P-type impurity concentration near both the source and drain regions (P − layer 4), it suppresses the substrate bias effect of the threshold voltage, and It has many advantages such as high punch-through breakdown voltage.
しかし、第２図（ｂ）に示すように、ドレインエッジか
ら濃度の比較的高いP-層４が延びているため、ドレイン
バイアスを印加した時の空乏層の広がりが抑えられドレ
ンエッジからピンチオフ点までの距離が短くなるため
に、ドレイン側の電界が高くなってホットエレクトロン
が多く発生し、トランジスタの信頼性が悪化するという
問題が、素子の微細化に伴って大きくなって来ている。However, as shown in FIG. 2B, since the P − layer 4 having a relatively high concentration extends from the drain edge, the expansion of the depletion layer when the drain bias is applied is suppressed, and the pinch off point from the drain edge. As the distance between the device and the device becomes shorter, the electric field on the drain side becomes higher, so that a lot of hot electrons are generated and the reliability of the transistor is deteriorated.
本発明は、上記に鑑みなされたもので、しきい値電圧の
基板バイアス効果が少なく、パンチスルー耐圧も高く、
かつ信頼性も高い絶縁ゲート型FETの構造およびこの構
造を簡単に作ることができる製造方法を提供することを
目的とする。The present invention has been made in view of the above, the substrate bias effect of the threshold voltage is small, the punch-through breakdown voltage is high,
It is an object of the present invention to provide a structure of an insulated gate FET having high reliability and a manufacturing method capable of easily manufacturing this structure.
上記目的を達成するために本発明は、ソース領域および
ドレイン領域の各一方からそれぞれゲート電極の下へ延
びた、チャネル領域と同導電型でかつそれより高不純物
濃度のパンチスルー防止用の半導体層を備え、この各半
導体層のゲート電極の下へ延びた長さはソース領域から
のものは比較的長く、ドレイン領域からのものは比較的
短いことを特徴とする絶縁ゲート型FETを提供するもの
である。このFETはLDD構造を有する、つまり、ソース・
ドレイン領域が、高濃度の主部分と、この主部分からチ
ャネル領域へ向って延出した低濃度部分とを有する。こ
こで、主部分と低濃度部分の基板表面からの深さを比較
すると、主部分は比較的深い位置まで形成され、低濃度
部分は比較的浅く形成されている。主部分からは、パン
チスルー防止用半導体層がチャネル領域に向かって延出
している。そして、ソース領域側のパンチスルー防止用
半導体層は、ソース領域の主部分からチャネル領域へ向
って、低濃度部分よりも長く延出し、一方、ドレイン側
のパンチスルー防止用半導体層は、ソース領域の主部分
からチャネル領域へ向って、低濃度部分よりも短く延出
している。In order to achieve the above object, the present invention provides a semiconductor layer for preventing punch-through, which extends from each one of a source region and a drain region below a gate electrode and has the same conductivity type as the channel region and a higher impurity concentration than that. And a length extending below the gate electrode of each semiconductor layer from the source region is relatively long and from the drain region is relatively short. Is. This FET has LDD structure, that is, the source
The drain region has a high-concentration main portion and a low-concentration portion extending from the main portion toward the channel region. Here, comparing the depths of the main portion and the low concentration portion from the substrate surface, the main portion is formed to a relatively deep position, and the low concentration portion is formed to be relatively shallow. A punch-through prevention semiconductor layer extends from the main portion toward the channel region. The punch-through prevention semiconductor layer on the source region side extends from the main portion of the source region toward the channel region longer than the low-concentration portion, while the punch-through prevention semiconductor layer on the drain side is the source region. Extending from the main part of the channel region toward the channel region shorter than the low concentration part.
また、本発明はかかる構造の絶縁ゲート型FETを製造す
るために、半導体基体の表面にゲート電極を形成した後
に、基体表面に対し、この基体と同導電型の不純物イオ
ンを、ソース領域側へ傾斜した入射角度で注入する工程
を備えたことを特徴とする絶縁ゲート型電界効果トラン
ジスタの製造方法を提供するものである。Further, according to the present invention, in order to manufacture an insulated gate FET having such a structure, after forming a gate electrode on the surface of a semiconductor substrate, impurity ions of the same conductivity type as the substrate are transferred to the source region side to the surface of the substrate. The present invention provides a method for manufacturing an insulated gate field effect transistor, which is characterized by including a step of implanting at an inclined incident angle.
以下、本発明に係る絶縁ゲート型FETの一実施例の断面
構造をその製造過程に従って示した第１図（ａ）〜
（ｄ）を参照して本発明を説明する。尚、同図において
第２図と同一物には同一符号を付してある。Hereinafter, a cross-sectional structure of one embodiment of an insulated gate FET according to the present invention is shown according to a manufacturing process thereof.
The present invention will be described with reference to (d). In the figure, the same parts as those in FIG. 2 are designated by the same reference numerals.
まず、第２図の場合と同様に、５Ω−cmのＰ型シリコン
基板１の表面に熱酸化膜２を約200Åの厚みに形成し、
その上に燐ドープト多結晶シリコン３を4000Å程度の厚
みに堆積し、これを写真蝕刻法等によりパターニングし
てチャネル領域８となるべきところに対応する位置にゲ
ート電極を形成する（第１図（ａ））。その後、基板１
の表面に対して、リンをほぼ垂直方向からイオン注入
し、またボロンをソース領域を形成すべき側へ例えば45
゜だけ傾斜した入射角度でイオン注入してLDD用の比較
的浅い深度のn-層５および基板１より高不純物濃度の比
較的い深い深度のパンチスルー防止用のP-層４を形成す
る（同図（ｂ））。このとき、ボロンイオンがソース領
域側へ傾いた方向から注入されることにより、ソース領
域側には多くのボロンイオンが注入されソース領域側の
P-層4sはゲート電極（多結晶シリコンＳ）の下へ長く延
び、またドレイン領域側はゲート電極の影となるためイ
オンはあまり注入されずドレイン領域側のP-層4dの延び
はn-層よりも短くなる。次に、全表面にCVD二酸化シリ
コン６を3000Å程度の厚みに堆積し、これをRIEでエッ
チングして、多結晶シリコン３の側壁のみに二酸化シリ
コン６を残す（同図（ｃ））。その後、ゲート耐圧向上
のため、多結晶シリコン３を酸化した後、ひ素をイオン
注入してソース・ドレイン各領域となる比較的深い深度
のn+層7s,7dを形成し、これで本発明の特徴を備えたLDD
nMOS FETが製作される（同図（ｄ））。First, as in the case of FIG. 2, a thermal oxide film 2 is formed on the surface of a 5Ω-cm P-type silicon substrate 1 to a thickness of about 200Å,
Phosphorus-doped polycrystalline silicon 3 is deposited thereon to a thickness of about 4000 Å, and this is patterned by photolithography or the like to form a gate electrode at a position corresponding to where the channel region 8 is to be formed (see FIG. 1 ( a)). Then substrate 1
Phosphorus is ion-implanted from a direction substantially perpendicular to the surface of, and boron is implanted to the side where the source region is to be formed, for example, 45
Ion implantation is performed at an incident angle inclined by deg. To form an n - layer 5 having a relatively shallow depth for LDD and a P - layer 4 having a higher impurity concentration than the substrate 1 for preventing punch-through to a relatively deep depth ( The same figure (b)). At this time, by implanting boron ions from the direction inclined to the source region side, a large amount of boron ions are implanted in the source region side and
The P − layer 4 s extends long below the gate electrode (polycrystalline silicon S), and since the drain region shadows the gate electrode, ions are not implanted so much and the P − layer 4 d on the drain region side extends. Shorter than n - layers. Next, CVD silicon dioxide 6 is deposited on the entire surface to a thickness of about 3000 Å, and this is etched by RIE to leave the silicon dioxide 6 only on the side walls of the polycrystalline silicon 3 (FIG. 7C). After that, in order to improve the gate breakdown voltage, the polycrystalline silicon 3 is oxidized, and then arsenic is ion-implanted to form the n + layers 7 s and 7 d having a relatively deep depth to be the source and drain regions, respectively. LDD with inventive features
An nMOS FET is manufactured (Fig. (d)).
かかる構造のLDD nMOS FETの特徴は、パンチスルー防止
用P-層4s,4dのうちソース領域側のもの4sはゲート電極
（多結晶シリコン３）とのオーバーラップ部分が長く、
ドレイン領域側のもの4dのそれは短いところにある。つ
まり、このFETはソース領域側の方がドレイン領域側よ
りも濃いＰ型不純物層を有していることになる。より詳
細に説明すれば、ソース領域側のパンチスルー防止用P-
層4sは、ソース領域のn-層５よりも長くチャネル領域８
へ向って延びており、そのため、ソース領域のn-層５は
完全にP-層4sに覆われている。一方、ドレイン領域側の
パンチスルー防止用P-層4dは、ドレイン領域のn-層５よ
りも短くチャネル領域８へ向って延びており、そのた
め、ドレイン領域のn-層５はその先端がチャネル領域８
に直接接合している。このため、このFETを五極管動作
させてドレイン電圧を上げると、ドレイン領域側の空乏
層がより延び易いために、ドレイン領域近傍の電界が緩
和されてホットエレクトロンの発生が低減され、よって
トランジスタの信頼性の悪化を防ぐことができる。ま
た、ドレイン領域側の空乏層が延びて行っても、ソース
領域側の濃いP-層4sのためにソース領域付近で空乏層の
延びは止まり、よってパンチスルーも防ぐことができ
る。しかも、チャネル領域８の不純物濃度は薄いので、
しきい値電圧の基板バイアス効果も防ぐことができるの
である。The feature of the LDD nMOS FET having such a structure is that the punch-through prevention P − layers 4 s and 4 d on the source region side 4 s have a long overlapping portion with the gate electrode (polycrystalline silicon 3).
The one on the side of the drain region, 4d , is short. That is, this FET has a P-type impurity layer that is denser on the source region side than on the drain region side. In detail, P for preventing punch-through of the source region side -
The layer 4s is longer than the n − layer 5 of the source region and the channel region 8
To the source region, so that the n − layer 5 in the source region is completely covered by the P − layer 4s. On the other hand, the punch-through preventing P − layer 4d on the drain region side extends toward the channel region 8 shorter than the n − layer 5 in the drain region, so that the tip of the n − layer 5 in the drain region is the channel. Area 8
Is directly bonded to. Therefore, when this FET is operated as a pentode to raise the drain voltage, the depletion layer on the drain region side is more easily extended, and the electric field in the vicinity of the drain region is relaxed to reduce the generation of hot electrons. It is possible to prevent the deterioration of reliability. Further, even if the depletion layer on the drain region side extends, the depletion layer stops extending near the source region due to the deep P − layer 4 s on the source region side, and therefore punchthrough can also be prevented. Moreover, since the impurity concentration of the channel region 8 is low,
The substrate bias effect of the threshold voltage can also be prevented.
また、かかる長さの異なるP-層4s,4dを形成するため
に、ゲート電極の形成後に、ソース領域側へ傾斜した方
向から基板表面へイオン注入を行うという上述の方法
は、マスクなどを用いる方法に比較して、第２図に示し
た従来のFETの製造工程をそのまま利用して行えるとい
う点で大きなメリットを有するものである。尚、上記実
施例ではイオン注入の入射角度を45゜としたが、この角
度に限られるわけではなく、ドレイン領域側のP-層4dの
ゲート電極とのオーバーラップ長が必要な短さ、例えば
n-層５のそれより短くなるような入射角度であればよ
い。Further, in order to form the P − layers 4 s and 4 d having different lengths, the above method of performing ion implantation on the substrate surface from the direction inclined to the source region side after forming the gate electrode is a mask or the like. Compared with the method using, there is a great advantage in that the conventional FET manufacturing process shown in FIG. 2 can be used as it is. In addition, although the incident angle of the ion implantation is set to 45 ° in the above embodiment, it is not limited to this angle, and the overlap length with the gate electrode of the P − layer 4 d on the drain region side is required to be short, For example
The incident angle may be shorter than that of the n − layer 5.
また、本発明に係るFETの構造およびその製造方法は、L
DD MOS FETに限られるわけではなく、もちろんGDDなど
の他のドレイン・ソース構造を持つFETやMOS以外の他の
絶縁ゲート型FETにも適用でき、その場合にも上記と同
様の効果を得ることができる。Further, the structure of the FET according to the present invention and the manufacturing method thereof are
The present invention is not limited to DD MOS FETs. Of course, it can be applied to FETs with other drain / source structures such as GDD and other insulated gate FETs other than MOS, and in that case the same effect as above can be obtained. You can
以上説明したように、本発明によれば、ソース領域およ
びドレイン領域のそれぞれに設けられたパンチスルー防
止用の半導体層のチャネル領域へ延出した長さを、ソー
ス領域側のものはソース領域の低濃度部分よりも長く、
ドレイン領域側ものはドレイン領域の低濃度部分よりも
短くしているため、パンチスルーやしきい値電圧の基板
バイアス効果を防止できるという従来からの効果に加え
て、ホットエレクトロンによる信頼性の悪化も防止でき
るという効果が得られる。As described above, according to the present invention, the length of the punch-through prevention semiconductor layer provided in each of the source region and the drain region extending to the channel region is set to Longer than the low density area,
Since the drain region side is made shorter than the low concentration part of the drain region, in addition to the conventional effect of preventing punch-through and substrate bias effect of threshold voltage, the reliability of hot electrons also deteriorates. The effect that it can be prevented is obtained.
また、本発明の製造方法によれば、ゲート電極形成後に
ソース領域側へ傾斜した入射角度で基体表面へイオン注
入を行うことにより、ソース領域側とドレイン領域側と
で長さの異なるパンチスルー防止用の半導体層を形成す
るようにしているので、従来からのFETの製造工程をそ
のまま利用して上記構造のFETを簡単に作ることができ
るという効果が得られる。Further, according to the manufacturing method of the present invention, ion implantation is performed on the surface of the substrate at an incident angle inclined to the source region side after forming the gate electrode, thereby preventing punch-through having different lengths on the source region side and the drain region side. Since the semiconductor layer for use in forming the FET is formed, it is possible to obtain the effect that the FET having the above-described structure can be easily manufactured by using the conventional FET manufacturing process as it is.
第１図は本発明に係る絶縁ゲート型FETの一実施例の構
造をその製造過程に従って示した断面図、第２図は従来
のLDD MOS FETの構造をその製造過程に従って示した断
面図である。 １……Ｐ型基板、２……熱酸化膜、３……燐ドープト多
結晶シリコン（ゲート電極）、4s,4d……パンチスルー
防止用P-層、５……n-層、６……CVD二酸化シリコン、7
s……n+層（ソース領域）、7d……n+層（ドレイン領
域）、８……チャネル領域。FIG. 1 is a sectional view showing the structure of one embodiment of an insulated gate FET according to the present invention in accordance with its manufacturing process, and FIG. 2 is a sectional view showing the structure of a conventional LDD MOS FET in accordance with its manufacturing process. . 1 ...... P-type substrate, 2 ...... thermal oxide film, 3 ...... phosphorous doped polycrystalline silicon (gate electrode), 4 s, 4 d ...... punchthrough prevention P - layer, 5 ...... n - layer, 6 ...... CVD silicon dioxide, 7
s ... n + layer (source region), 7d ... n + layer (drain region), 8 ... channel region.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭56−126970（ＪＰ，Ａ) 特開 昭58−93279（ＪＰ，Ａ) 特開 昭53−119686（ＪＰ，Ａ) 特開 昭58−147074（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-56-126970 (JP, A) JP-A-58-93279 (JP, A) JP-A-53-119686 (JP, A) JP-A-58- 147074 (JP, A)
Claims (2)
基体の表面にチャネル領域をはさんで形成された第２導
電型のソース領域およびドレイン領域、ならびに前記チ
ャネル領域の上に絶縁膜を介して形成されたゲート電極
とを有するものにおいて、 前記ソース領域およびドレイン領域はそれぞれ、比較的
深く形成された主部分と、比較的浅く形成されかつ前記
主部分から前記チャネル領域へ向って延出している、前
記主部分より低不純物濃度の低濃度部分とを有し、 さらに、前記ソース領域およびドレイン領域の主部分か
らそれぞれ前記チャネル領域へ向って、前記第１導電型
の比較的高不純物濃度のパンチスルー防止用半導体層が
延出しており、前記ソース領域からのパンチスルー防止
用半導体層は前記ソース領域の低濃度部分よりも長く延
出し、前記ドレイン領域からのパンチスルー防止用半導
体層は前記ドレイン領域の低濃度部分よりも短く延出し
ていることを特徴とする絶縁ゲート型電界効果トランジ
スタ。1. A source / drain region of a second conductivity type formed with a channel region on the surface of a semiconductor substrate of a first conductivity type and a relatively low impurity concentration, and an insulating film on the channel region. A source electrode and a drain region, the source region and the drain region each being formed relatively deep and the region relatively shallow and extending from the main portion toward the channel region. A low-concentration portion having an impurity concentration lower than that of the main portion, and further, from the main portion of the source region and the drain region toward the channel region, respectively, a relatively high impurity of the first conductivity type. The semiconductor layer for preventing punch-through of the concentration extends, and the semiconductor layer for preventing punch-through from the source region is higher than that of the low-concentration portion of the source region. Ku extending therefrom, the insulated gate field effect transistor is punchthrough semiconductor layer, characterized in that out shorter extension than the low concentration portion of the drain region from the drain region.
基体のチャネル領域とすべき部分の上に絶縁膜を介して
ゲート電極を形成する工程と、前記基体の表面に前記チ
ャネル領域をはさんで第２導電型のソース領域およびド
レイン領域を形成する工程とを有し、前記ソース領域お
よびドレイン領域はそれぞれ、比較的深く形成された主
部分と、比較的浅く形成されかつ前記主部分から前記チ
ャネル領域へ向って延出している、前記主部分より低不
純物濃度の低濃度部分とを有する電界効果トランジスタ
の製造方法において、 前記ソース領域およびドレイン領域の主部分からそれぞ
れ前記チャネル領域へ向って延出した、前記第１導電型
の比較的高不純物濃度のパンチスルー防止用半導体層を
形成する工程をさらに備え、この工程は、前記半導体層
のうち前記ソース領域からのものは前記ソース領域の低
濃度部分よりも長く延出させ、前記ドレイン領域からの
ものは前記ドレイン領域の低濃度部分よりも短く延出さ
せるように、前記ゲート電極の形成後に、前記基体の表
面に対して前記第１導電型の不純物イオンを、前記ソー
ス領域の側へ傾斜した入射角度で注入する工程を備えた
ことを特徴とする絶縁ゲート型電界効果トランジスタの
製造方法。2. A step of forming a gate electrode on a portion of a first conductivity type semiconductor substrate having a relatively low impurity concentration to be a channel region with an insulating film interposed therebetween, and the channel region being formed on the surface of the substrate. Forming a source region and a drain region of the second conductivity type by sandwiching the source region and the drain region, each of the source region and the drain region being relatively deep and relatively shallow. In the method of manufacturing a field effect transistor having a low-concentration portion having a lower impurity concentration than the main portion, extending from the main portion of the source region and the drain region toward the channel region, respectively. The step of forming a semiconductor layer for punch-through prevention of the first conductivity type having a relatively high impurity concentration, which is extended. The gate of the body layer extends from the source region so as to extend longer than the low concentration portion of the source region, and the drain region extends shorter than the low concentration portion of the drain region. An insulated gate field effect transistor comprising a step of implanting the first conductivity type impurity ions into the surface of the substrate after forming the electrode at an incident angle inclined to the source region side. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60296001A JPH0789587B2 (en) | 1985-12-27 | 1985-12-27 | Insulated gate field effect transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60296001A JPH0789587B2 (en) | 1985-12-27 | 1985-12-27 | Insulated gate field effect transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62155565A JPS62155565A (en) | 1987-07-10 |
| JPH0789587B2 true JPH0789587B2 (en) | 1995-09-27 |
Family
ID=17827843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60296001A Expired - Fee Related JPH0789587B2 (en) | 1985-12-27 | 1985-12-27 | Insulated gate field effect transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0789587B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5258319A (en) * | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
| JP2578662B2 (en) * | 1989-05-19 | 1997-02-05 | 三洋電機株式会社 | Method for manufacturing semiconductor device |
| JPH045861A (en) * | 1990-04-23 | 1992-01-09 | Mitsubishi Electric Corp | Semiconductor device |
| JPH04206933A (en) * | 1990-11-30 | 1992-07-28 | Nec Corp | Semiconductor device |
| KR100269280B1 (en) * | 1992-12-07 | 2000-10-16 | 윤종용 | Manufacture method of ldd type mos transistor |
| JP2000507390A (en) * | 1994-11-16 | 2000-06-13 | 松下電器産業株式会社 | Semiconductor device and manufacturing method thereof |
| EP0814502A1 (en) * | 1996-06-21 | 1997-12-29 | Matsushita Electric Industrial Co., Ltd. | Complementary semiconductor device and method for producing the same |
| JP4763555B2 (en) * | 2006-08-30 | 2011-08-31 | 新日本無線株式会社 | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6032992B2 (en) * | 1977-03-29 | 1985-07-31 | 工業技術院長 | Manufacturing method of semiconductor device |
| JPS56126970A (en) * | 1980-03-11 | 1981-10-05 | Nippon Telegr & Teleph Corp <Ntt> | Mos field effect transistor and manufacture thereof |
| JPS5893279A (en) * | 1981-11-30 | 1983-06-02 | Fujitsu Ltd | Manufacture of semiconductor device |
| DE3279662D1 (en) * | 1981-12-30 | 1989-06-01 | Thomson Components Mostek Corp | Triple diffused short channel device structure |
-
1985
- 1985-12-27 JP JP60296001A patent/JPH0789587B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62155565A (en) | 1987-07-10 |
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