JPH02208942A - Manufacture of thin film transistor - Google Patents

Manufacture of thin film transistor

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Publication number
JPH02208942A
JPH02208942A JP2895089A JP2895089A JPH02208942A JP H02208942 A JPH02208942 A JP H02208942A JP 2895089 A JP2895089 A JP 2895089A JP 2895089 A JP2895089 A JP 2895089A JP H02208942 A JPH02208942 A JP H02208942A
Authority
JP
Japan
Prior art keywords
thin film
semiconductor layer
layers
impurity
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2895089A
Other languages
Japanese (ja)
Inventor
Masatoshi Yazaki
矢崎 正俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2895089A priority Critical patent/JPH02208942A/en
Publication of JPH02208942A publication Critical patent/JPH02208942A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To reduce the number of times of irradiation with a laser beam by a method wherein impurity thin films are formed on source and drain regions and impurities are diffused in semiconductor layers fused by irradiation with the laser beam. CONSTITUTION:First semiconductor layers 2 are left on source and drain regions 4 and 5 of a thin film transistor in an insulative substrate 1 and a second semiconductor layer 3 is left on the regions 4 and 5 and a channel region 6. Moreover, impurity thin film layers 7 are constituted on the regions 4 and 5 and the thin film layers 7 contain phosphorus and boron, which are used as an impurity for diffusion use, in a high concentration. Here, the layers 2 and 3 are fused by irradiation with a laser beam 20, the impurities in the layers 7 are diffused, ohmic contact layers 8 are formed and the layer 3 is recrystallized. Moreover, a gate insulating film 9 is deposited, a gate electrode 10 is constituted, contact holes are respectively formed in the regions 4 and 5 and source and drain electrodes 11 and 12 are formed. Thereby, the constitution of the thin film transistor, which is formed by an impurity diffusion, becomes possible by one time of irradiation with the beam 20 and the high-efficiency thin film transistor can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、絶縁性基体上の薄膜トランジスタの製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a thin film transistor on an insulating substrate.

〔従来の技術〕[Conventional technology]

従来の技術としては特開昭63−136673号公報に
記載されたものがある。これは第2図(a)に示すよう
に絶縁基体13上に第1半導体膜14を成膜した後、エ
ネルギービーム15を照射し第1半導体膜14を再結晶
化し再結晶半導体膜16とし、第2図(b)に示すよう
に、ソースとドレイン領域に低抵抗な第2半導体膜17
と絶縁膜18を残し、再びエネルギービーム15を照射
し、第2半導体膜17中の不純物の活性化を行ない、さ
らに低抵抗化し、第2図(c)に示すようにゲート絶縁
WA9を堆積した後、低抵抗な第3半導体膜を積層し、
ソース及びドレイン領域にコンタクトホールを形成して
、ゲート電極10とソース電極11及びドレイン電極1
2を製作する工程からなるものである。
As a conventional technique, there is one described in Japanese Unexamined Patent Publication No. 136673/1983. As shown in FIG. 2(a), a first semiconductor film 14 is formed on an insulating substrate 13, and then an energy beam 15 is irradiated to recrystallize the first semiconductor film 14 to form a recrystallized semiconductor film 16. As shown in FIG. 2(b), a second semiconductor film 17 with low resistance is provided in the source and drain regions.
The energy beam 15 was irradiated again, leaving the insulating film 18, to activate the impurities in the second semiconductor film 17, further lowering the resistance, and depositing the gate insulating WA9 as shown in FIG. 2(c). After that, a third semiconductor film with low resistance is laminated,
Contact holes are formed in the source and drain regions to form gate electrodes 10, source electrodes 11, and drain electrodes 1.
It consists of the process of manufacturing 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、かかる従来の薄膜トランジスタの製造方法は、
第2図(a)と第2図(b)に示すように2回のエネル
ギービームの照射が必要であった。
However, the conventional manufacturing method of thin film transistors is
As shown in FIG. 2(a) and FIG. 2(b), two energy beam irradiations were required.

さらに第2図(b)に示すように低抵抗な第2半導体膜
17にエネルギービーム15を照射する際には、第2半
導体11!117中の不純物の活性化が進むとともに、
再結晶半導体膜16への不純物の拡散が起き、第2半導
体膜17中の不純物の濃度が減少し膜が劣化し、かえっ
て第2半導体膜17の抵抗が高くなるという問題点を有
していた。
Furthermore, as shown in FIG. 2(b), when the low-resistance second semiconductor film 17 is irradiated with the energy beam 15, the impurities in the second semiconductor 11!117 are activated and
There was a problem in that impurity diffusion into the recrystallized semiconductor film 16 occurred, the impurity concentration in the second semiconductor film 17 decreased, the film deteriorated, and the resistance of the second semiconductor film 17 increased. .

そこで、本発明は従来のこのような問題点を解決するた
め、エネルギービームの照射回数を減らし、ソース領域
とドレイン領域の低抵抗性を得ることが可能な薄膜トラ
ンジスタの製造方法を提供することを目的とする。
Therefore, in order to solve these conventional problems, an object of the present invention is to provide a method for manufacturing a thin film transistor that can reduce the number of times of energy beam irradiation and obtain low resistance of the source region and drain region. shall be.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するため、本発明の薄膜トランジスタの
製造方法は、絶縁性基体上に第1半導体層を堆積し、ソ
ース領域とドレイン領域に前記第1半導体層を島状に残
す工程と、第2半導体層を堆積し、前記ソース領域と前
記ドレイン領域にある前記第1半導体層上とチャネル領
域に前記第2半導体層を残す工程と、前記第1半導体層
と前記第2半導体層を積層した前記ソース領域上と前記
ドレイン領域上に不純物を高濃度に含有する不純物薄膜
層を島状に形成する工程と、レーザ・ビームを照射して
前記ソース領域と前記ドレイン領域に前記不純物薄膜層
中の前記不純物を前記第2半導体層と前記第1半導体層
へ拡散し活性化してオーミック接触層を構成し、チャネ
ル領域の第2半導体層を再結晶化する工程と、ゲート絶
縁膜を堆積する工程と、ゲート電極を構成し、前記ソー
ス領域と前記ドレイン領域にコンタクト・ホールを形成
してソース電極とドレイン電極を製作する工程からなる
ことを特徴とする。
In order to solve the above problems, a method for manufacturing a thin film transistor according to the present invention includes a step of depositing a first semiconductor layer on an insulating substrate and leaving the first semiconductor layer in an island shape in a source region and a drain region; depositing a semiconductor layer and leaving the second semiconductor layer on the first semiconductor layer in the source region and the drain region and in the channel region; and the step of stacking the first semiconductor layer and the second semiconductor layer. forming an island-shaped impurity thin film layer containing impurities at a high concentration on the source region and the drain region; Diffusing and activating impurities into the second semiconductor layer and the first semiconductor layer to form an ohmic contact layer, recrystallizing the second semiconductor layer in the channel region, and depositing a gate insulating film; The present invention is characterized in that it comprises the steps of forming a gate electrode and forming contact holes in the source region and the drain region to fabricate the source electrode and the drain electrode.

〔実 施 例〕〔Example〕

以下に本発明の薄膜トランジスタの製造方法の一実施例
を縦断面図にもとづいて説明する。第1図(a)におい
て、絶縁性基体1上に薄膜トランジスタのソース領F!
A4とドレイン領域5に第1半導体層2を残す。次に、
第1図(b)において、薄膜トランジスタのチャネル領
域を構成す第2半導体層3をソース領域4上とドレイン
領域5上とチャネル領域6上に残し、第1図(C)に示
すように、ソース領域4上とドレイン領域5上に不純物
薄膜7を構成する。この不純物薄膜7は、プラズマCV
D (化学的気相成長)法や減圧CVDにより成膜され
た拡散用不純物となるリンやボロンなどを高濃度に含ん
だ膜である。第1半導体層2と第2半導体層3が不純物
を含有しない非晶質シリコン層よりなる場合、不純物薄
膜@7の膜厚は300オングストローム以下でよく、第
1図(C)に示したレーザ・ビーム20の照射によって
融解した第2半導体層3と第1半導体層2の中へ不純物
薄膜層7を構成する不純物が拡散し、第1図(d)に示
すようにオーミック接触層8ができあがる。また、第1
図(C)に示したレーザ・ビーム20の照射により、チ
ャネル領域6の第2半導体層3の融解及び再結晶化がお
こり、第1図(d)に示すように再結晶半導体膜16が
構成できる。
An embodiment of the method for manufacturing a thin film transistor of the present invention will be described below based on longitudinal cross-sectional views. In FIG. 1(a), a source region F! of a thin film transistor is formed on an insulating substrate 1!
The first semiconductor layer 2 is left in A4 and the drain region 5. next,
In FIG. 1(b), the second semiconductor layer 3 constituting the channel region of the thin film transistor is left on the source region 4, the drain region 5, and the channel region 6, and as shown in FIG. An impurity thin film 7 is formed on the region 4 and the drain region 5. This impurity thin film 7 is formed by plasma CV
It is a film containing a high concentration of phosphorus, boron, etc., which serve as diffusion impurities, and is formed by a D (chemical vapor deposition) method or low-pressure CVD. When the first semiconductor layer 2 and the second semiconductor layer 3 are made of amorphous silicon layers that do not contain impurities, the thickness of the impurity thin film @ 7 may be 300 angstroms or less, and the laser beam shown in FIG. The impurities constituting the impurity thin film layer 7 are diffused into the second semiconductor layer 3 and the first semiconductor layer 2 melted by the irradiation with the beam 20, and an ohmic contact layer 8 is formed as shown in FIG. 1(d). Also, the first
Irradiation with the laser beam 20 shown in FIG. 1(C) causes melting and recrystallization of the second semiconductor layer 3 in the channel region 6, forming a recrystallized semiconductor film 16 as shown in FIG. 1(d). can.

このときのレーザ・ビーム20の強度は、第2半導体層
3が250℃プラズマCVD法により構成された100
OA非晶質シリコン層の場合には、およそ平方センチメ
ートル当り400ミリジユールから800ミリジユール
の強度で十分である。
The intensity of the laser beam 20 at this time is 100% when the second semiconductor layer 3 is formed by the 250°C plasma CVD method.
For OA amorphous silicon layers, an intensity of approximately 400 to 800 millijoules per square centimeter is sufficient.

このレーザ・ビーム20の照射によって第1図(d)に
示した再結晶半導体膜16の結晶粒径は数千オングスト
ロームから数ミクロンメートルに致る大きな結晶粒とな
る。この大きな結晶粒の構成により、薄膜トランジスタ
の電界効果移動度は向上し高性能なものとなる。
By irradiating the laser beam 20, the crystal grain size of the recrystallized semiconductor film 16 shown in FIG. 1(d) becomes large, ranging from several thousand angstroms to several micrometers. This structure of large crystal grains improves the field effect mobility of the thin film transistor, resulting in high performance.

以下の工程は、通當の薄膜トランジスタの製造方法と同
様で、第1図(d)に示すようにゲート絶縁膜9を積層
した後、第1図(e)におけるようにゲート電極10を
構成し、第1図(f)のようにソー′7.電極11とド
レイン電極12を形成し薄膜トランジスタが完成する。
The following steps are similar to the manufacturing method of a conventional thin film transistor, and after stacking the gate insulating film 9 as shown in FIG. 1(d), the gate electrode 10 is formed as shown in FIG. 1(e). , as shown in FIG. 1(f). An electrode 11 and a drain electrode 12 are formed to complete a thin film transistor.

〔発明の効果〕〔Effect of the invention〕

本発明の薄膜トランジスタの製造方法は、以上説明した
ように、チャネル領域の結晶化とオーミック接触層の不
純物拡散による構成を1回のレーザ・ビームによって可
能とし、高性能な薄膜トランジスタを実現しうるという
効果を有する。
As explained above, the method for manufacturing a thin film transistor of the present invention enables the crystallization of the channel region and the impurity diffusion of the ohmic contact layer with a single laser beam, and has the effect of realizing a high-performance thin film transistor. has.

法の一実施例を示す工程順の縦断面図。FIG. 3 is a vertical cross-sectional view of the process order showing an example of the method.

第2図は、従来の薄膜トランジスタの製造方法の工程順
の縦断面図。
FIG. 2 is a vertical cross-sectional view of the process order of a conventional thin film transistor manufacturing method.

1・・・絶縁性基体 2・・・第1半導体層 3・・・第2半導体層 4 ◆ 寺 5寺・ 6・ ・ 7 ・ ・ 8日 9・ ・ 10・ ・ 11 ・ ◆ 12 φ ・ 13 ・ 争 14 番 Φ 15・ ・ 16・ φ 17 ・ ・ 18− ・ 19・ ・ 20 ・ ・ ・ソース領域 ・ドレイン領域 ・チャネル領域 ・不純物薄膜層 ・オーミック接触層 ・ゲート絶縁膜 ・ゲート電極 ・ソース電極 ・ドレイン電極 ・絶縁基板 ・第1半導体膜 ・エネルギービーム ・再結晶半導体膜 ・第2半導体膜 ・絶縁膜 ・第3半導体膜 ・レーザψビーム 第1口1... Insulating substrate 2...first semiconductor layer 3... Second semiconductor layer 4 ◆ Temple 5 temples 6・・ 7・・・ 8th day 9・・ 10・・ 11・◆ 12 φ ・ 13. Conflict No. 14 Φ 15・・ 16・φ 17・・ 18-・ 19・・ 20・・ ・Source area ・Drain area ・Channel area ・Impurity thin film layer ・Ohmic contact layer ・Gate insulation film ・Gate electrode ・Source electrode ・Drain electrode ・Insulating substrate ・First semiconductor film ・Energy beam ・Recrystallized semiconductor film ・Second semiconductor film ・Insulating film ・Third semiconductor film ・Laser ψ beam 1st mouth

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁性基体上に第1半導体層を堆積し、ソース領
域とドレイン領域に前記第1半導体層を島状に残す工程
と、第2半導体層を堆積し、前記ソース領域と前記ドレ
イン領域にある前記第1半導体層上とチャネル領域に前
記第2半導体層を残す工程と、前記第1半導体層と前記
第2半導体層を積層した前記ソース領域上と前記ドレイ
ン領域上に不純物を高濃度に含有する不純物薄膜層を島
状に形成する工程と、レーザ・ビームを照射して前記ソ
ース領域と前記ドレイン領域に前記不純物薄膜層中の前
記不純物を前記第2半導体層と前記第1半導体層へ拡散
し活性化してオーミック接触層を構成し、チャネル領域
の第2半導体層を再結晶化する工程と、次にゲート絶縁
膜を堆積する工程と、次にゲート電極を構成し、前記ソ
ース領域と前記ドレイン領域にコンタクト・ホールを形
成してソース電極とドレイン電極を製作する工程からな
ることを特徴とする薄膜トランジスタの製造方法。
(1) A step of depositing a first semiconductor layer on an insulating substrate and leaving the first semiconductor layer in an island shape in the source region and the drain region, and depositing a second semiconductor layer in the source region and the drain region. leaving the second semiconductor layer on the first semiconductor layer and the channel region, and doping impurities at a high concentration on the source region and the drain region where the first semiconductor layer and the second semiconductor layer are laminated. a step of forming an island-shaped impurity thin film layer containing an impurity in the second semiconductor layer and the first semiconductor layer by irradiating a laser beam to transfer the impurities in the impurity thin film layer to the source region and the drain region; to form an ohmic contact layer, recrystallize the second semiconductor layer in the channel region, deposit a gate insulating film, form a gate electrode, and form an ohmic contact layer in the source region. and forming a contact hole in the drain region to fabricate a source electrode and a drain electrode.
JP2895089A 1989-02-08 1989-02-08 Manufacture of thin film transistor Pending JPH02208942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2895089A JPH02208942A (en) 1989-02-08 1989-02-08 Manufacture of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2895089A JPH02208942A (en) 1989-02-08 1989-02-08 Manufacture of thin film transistor

Publications (1)

Publication Number Publication Date
JPH02208942A true JPH02208942A (en) 1990-08-20

Family

ID=12262689

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2895089A Pending JPH02208942A (en) 1989-02-08 1989-02-08 Manufacture of thin film transistor

Country Status (1)

Country Link
JP (1) JPH02208942A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512494A (en) * 1993-11-29 1996-04-30 Nec Corporation Method for manufacturing a thin film transistor having a forward staggered structure
US5618741A (en) * 1994-04-07 1997-04-08 U.S. Philips Corporation Manufacture of electronic devices having thin-film transistors
US5648276A (en) * 1993-05-27 1997-07-15 Sony Corporation Method and apparatus for fabricating a thin film semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5648276A (en) * 1993-05-27 1997-07-15 Sony Corporation Method and apparatus for fabricating a thin film semiconductor device
US5512494A (en) * 1993-11-29 1996-04-30 Nec Corporation Method for manufacturing a thin film transistor having a forward staggered structure
US5618741A (en) * 1994-04-07 1997-04-08 U.S. Philips Corporation Manufacture of electronic devices having thin-film transistors

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