JP2779492B2 - Thin film transistor device and method of manufacturing the same - Google Patents
Thin film transistor device and method of manufacturing the sameInfo
- Publication number
- JP2779492B2 JP2779492B2 JP21296785A JP21296785A JP2779492B2 JP 2779492 B2 JP2779492 B2 JP 2779492B2 JP 21296785 A JP21296785 A JP 21296785A JP 21296785 A JP21296785 A JP 21296785A JP 2779492 B2 JP2779492 B2 JP 2779492B2
- Authority
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- Japan
- Prior art keywords
- thin film
- semiconductor thin
- resistance semiconductor
- region
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 123
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 92
- 239000010408 film Substances 0.000 claims description 67
- 238000000137 annealing Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 15
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 13
- 239000002184 metal Substances 0.000 description 7
- 238000010894 electron beam technology Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜トランジスタ（TFT）装置、特に多結
晶もしくは単結晶半導体薄膜をチヤンネル領域をもつ第
１のTFTと、より粒径の小さい多結晶もしくは非晶質半
導体薄膜をチヤンネル領域にもつ第２のTFTの２種のTFT
を有する装置と、その製造方法に関するものである。
〔発明の概要〕
第１のTFTのチヤンネル領域、ソース及びドレイン領
域、さらに第２のTFTのソース及びドレイン領域にビー
ムアニールされた半導体薄膜を用いる。第２のTFTは、
その後堆積された第２半導体薄膜のチヤンネル領域、そ
の上のゲート絶縁膜及びゲート電極を有する。第１のTF
Tは、ゲート絶縁膜として第２半導体薄膜及び第２のTFT
のゲート絶縁膜の２層膜を有している。このことによ
り、第2TFTのソースドレイン直列抵抗が小さくできると
共に、２種のTFTをもつTFT装置の製造が容易になる。
〔従来の技術〕
非晶質シリコン（ａ−Si）を用いたTFTは低温で大面
積に形成できるため、液晶表示装置等に応用されつつあ
る。しかし、ａ−Siのキヤリア移動度が小さいため高速
動作に限界があり、応用範囲が限られていた。これを解
決するための一手段として、レーザ光や電子線等のエネ
ルギービームを用いたアニールによつてａ−Siを結晶化
することがある。第２図に、ビームアニールによるTFT1
とａ−Siを用いたTFT2を混載するTFT装置の断面例を示
し、問題点につき説明する。ガラス、石英等の絶縁基板
１上にTFT1は、ビームアニールされた第１高抵抗半導体
薄膜10、その上の第１低抵抗半導体薄膜からなる第１ソ
ース領域11、第１ドレイン領域12、第１ゲート絶縁膜1
3、その上の第１ゲート電極14から成り、必要に応じ第
１ソース配線31、第１ドレイン配線32が設けられる。ビ
ームアニールの均一性向上や不純物再拡散を防止するた
め、最初に第１高抵抗薄膜10を形成することが望まし
く、TFT1のこの構造例が最適なものの１つである。一
方、TFT1と混載しやすい構造のTFT2は第２高抵抗半導体
膜（ａ−Si膜）110上の第２低抵抗薄膜である第２ソー
ス領域111、第２ドレイン領域と、第２ゲート絶縁膜11
3、第２ゲート電極114から成る。一般に第２低抵抗薄膜
をａ−Si膜で形成すると抵抗は充分小さくないので、そ
の上に金属等の第２ソース電極121、第２ドレイン電極1
22が必要である。この構造例では第１ゲート絶縁膜13と
第２ゲート絶縁膜113、第１及び第２ソース領域11、111
と第１及び第２ドレイン領域12、112、第１ゲート電極1
4と第２ゲート電極114はそれぞれ同時に形成できる利点
があるが、次の様な問題がある。
（１） 第１高抵抗半導体薄膜10と第２高抵抗半導体薄
膜110の厚みが異なるとき、同時に堆積できないので堆
積工程が増えると共に、マスク工程が増える。
（２） 第２半導体薄膜110と第２ゲート絶縁膜113を連
続して堆積できないので、TFT2の特性上問題がある。
（３） 第１低抵抗薄膜11、12にａ−Si膜を用いると抵
抗が大きく、TFT1の特性に問題がある。
（４） （３）の問題を避けるため第１低抵抗薄膜11、
12をビームアニールすると、TFT2の第２ソース及びドレ
イン電極121、122をいつ形成するかが問題となり、やは
り工程増につながる。
TFT2としてａ−Si TFTで従来良く用いられるゲート電
極が下の逆スタガー構造をとると堆積層数、マスク数が
増加してしまう。
〔発明が解決しようとする問題点〕
本発明は叙上の問題点に鑑みてなされ、その目的は、
ビームアニールされたTFTとそうでないTFTを混載しやす
いそれぞれの構造とその製造方法を提供することであ
る。上記２種のTFTの特性が充分良好にすることを他の
目的として有する。
〔問題点を解決するための手段〕
絶縁基板上に設けられた第１のTFTと第２のTFTを少な
く共有するTFT装置に関し、第１のTFTは基板上の第１高
抵抗半導体薄膜から成る第１チヤンネル領域と、一導電
型の第１低抵抗半導体薄膜より成る第１ソース領域と第
１ドレイン領域と、前記第１高抵抗薄膜上の第１ゲート
絶縁膜と、その上の第１ゲート電極とから少なく共成
る。第２のTFTは、基板上に設けられた一導電型の第２
低抵抗半導体薄膜より成る第２ソース領域と第２ドレイ
ン領域と、両領域に接する第２高抵抗半導体薄膜による
第２チヤンネル領域と、第２高抵抗薄膜上の第２ゲート
絶縁膜とその上の第２ゲート電極とから成る。第２高抵
抗薄膜が非晶質もしくは多結晶であるのに対し、第１高
抵抗薄膜、第１及び第２低抵抗薄膜はビームアニール等
により第２高抵抗薄膜より粒径の大きい多結晶または単
結晶になつている。また、第１ゲート絶縁膜は第２ゲー
ト絶縁膜と同時に設けられた絶縁膜と第２高抵抗薄膜と
の２層膜から成り、第１ゲート電極と第２ゲート電極は
同時に形成されている。
製造においては、絶縁基板上に高抵抗半導体薄膜を堆
積してビームアニールし第１高抵抗半導体薄膜を形成
し、一導電型不純物を選択的に添加して第１ソース及び
ドレイン領域と第２ソース及びドレイン領域を設けて第
１高抵抗半導体薄膜を第1TFTの第１ソース及びドレイン
領域と第１チヤンネル領域と第2TFTの第２ソース及びド
レイン領域を残すべく選択エツチする。次に、第２高抵
抗半導体薄膜、絶縁膜を連続堆積し、さらに第１及び第
２ゲート電極を形成する。
〔作用〕
上記の様に第2TFTの第２ソース及びドレイン領域には
粒径の大きい多結晶または単結晶を用いることができる
ので、直列抵抗の小さく良好な特性が得られると共に、
第２図のTFT2の如く金属から成る第２ソース電極121、
第２ドレイン電極122を第２ソース及びドレイン領域11
1、112と同じ形状に設ける必要がない。第１高抵抗半導
体薄膜とは独立に第２高抵抗半導体薄膜を堆積できるた
め、各厚みは各TFTの最適な値を選ぶことができる。第2
TFTの第２高抵抗薄膜と第２ゲート絶縁膜は連続して堆
積できるため、両者の界面の汚染や損傷に原因するしき
い値電圧やオン電流のバラツキを低く抑えることができ
る。さらに、第1TFTの第１ゲート絶縁膜には第２高抵抗
半導体薄膜が付加されるが、一般には薄くて誘電率が大
きくかつ第１高抵抗薄膜よりも数桁以上抵抗率が高いた
め充分第１ゲート絶縁膜の一部として使用できる。
〔実施例〕
以下に図面を用い本発明を詳述する。
a. 実施例１（第１図）
第１図は本発明による第1TFT（TFT1）と第2TFT（TFT
2）を混載したTFT装置の断面構造例である。ガラス、石
英、絶縁膜コートした半導体や導体基板等の絶縁基板１
上にTFT1とTFT2の２種が搭載されている。TFT1は、基板
１上に設けられた第１高抵抗半導体薄膜から成る第１チ
ヤンネル領域とその両側に設けたｐ型またはｎ型の第１
低抵抗半導体薄膜から成る第１ソース領域11、第１ドレ
イン領域12と、第１チヤンネル領域10上の第１ゲート絶
縁膜13、その上の第１ゲート電極14から成つている。TF
T2は、基板１上に設けられ互に離間したｐ型またはｎ型
の第２低抵抗半導体薄膜による第２ソース領域111、第
２ドレイン領域112と、両領域に接する第２高抵抗半導
体薄膜による第２チヤンネル領域110と、その上の第２
ゲート絶縁膜113及び第２ゲート電極114から成る。第１
ソース及びドレイン領域11、12と第２ソース及びドレイ
ン領域111、112は同導電型を有しており、第１チヤンネ
ル領域10と共に第２チヤンネル領域110より粒径が大き
い多結晶か単結晶でビームアニール等で設けられる。第
２チヤンネル領域110（第２高抵抗薄膜）は非晶質また
は粒径の小さい多結晶から成る。第１ゲート絶縁膜13は
第２高抵抗半導体薄膜33と第２ゲート絶縁膜113と同時
に堆積された絶縁膜23の２層膜から成る。第１及び第２
ゲート電極14、114は同時に金属膜等で形成されている
が、必要に応じTFT1の第１ソース配線31、第１ドレイン
配線32、TFT2の第２ソース配線131、第２ドレイン配線1
32も設けられている。また、第１及び第２ソース領域1
1、111や第１及び第２ドレイン領域12、112はビームア
ニールされた第１及び第２低抵抗半導体薄膜を用いるた
めに抵抗が充分低く、必要に応じ金属等で設けられた第
１及び第２ソース電極21、121や第１及び第２ドレイン
電極22、122は前記各領域11、111、12、112の一部に接
触していればよい。第２高抵抗半導体薄膜110、33は非
常に薄いことがTFT2の光特性及びTFT1のゲート電圧印加
等の点で望ましく、例えば500Å以下の値が選ばれる。
一方第１高抵抗半導体薄膜10はTFT1の必要特性と共にビ
ームアニールされやすさからその厚みが選ばれ、例えば
0.2〜0.5μに選ばれる。第１及び第２高抵抗半導体薄膜
10、110（33）の導電型や抵抗率は、TFT1及び２の所望
特性によつて選ばれる。
b. 実施例２ 製造工程（第３図）
第３図には本発明によるTFT装置の製造工程に沿つた
断面図を示す。第３図（ａ）は絶縁基板１上に非晶質ま
たは多結晶の高抵抗半導体薄膜２を堆積し、ビームアニ
ールして粒径の大きい多結晶または単結晶の第１高抵抗
半導体薄膜10を形成した状態を示す。高抵抗半導体薄膜
２にはａ−Si膜や多結晶Si膜が主に用いられる。ビーム
アニールには、Ar、YAG、エキシマーレーザ、電子線、
ランプ、ヒーター等のエネルギービームが用いられ、第
３図（ａ）の例では必要場所を選択的にアーニルした例
を示した。CWレーザや電子線等を用いる場合、選択アニ
ールがスループツト向上のために有効である。第３図
（ｂ）は、不純物を含む低抵抗半導体薄膜３を堆積し
て、少なく共第1TFT（TFT1）のチヤンネル領域上の低抵
抗薄膜３を除去した状態を示す。不純物としてはＰ、A
s、Sb、Ｂ等が用いられ、低抵抗半導体薄膜３にはａ−S
i膜または多結晶Si膜が用いられ、厚みは100〜1000Åで
ある。第３図（ｃ）は、第３図（ｂ）の状態で再度ビー
ムアニールして低抵抗半導体薄膜３を結晶化すると共に
不純物を第１高抵抗半導体薄膜10内に拡散し、さらに少
なく共TFT1の第１ソース及びドレイン領域11、12とその
間の第１高抵抗半導体薄膜（チヤンネル領域）10及びTF
T2の第２ソース及びドレイン領域111、112を残して選択
エツした状態を示す。再度のビームアニールは、低抵抗
半導体薄膜３が溶融しない様な低パワー、高走査速度で
行なうことが不純物の横方向再分布を大きくしない上で
望ましい。第３図（ｄ）は、第２高抵抗半導体薄膜４及
び絶縁膜５を連続的に堆積した状態を示す。第２高抵抗
半導体薄膜４には例えばａ−Si:H膜等を100〜500Åの厚
みで、絶縁膜５には例えばSiOx膜またはSiNx膜を1000〜
3000Åの厚みにプラズマCVD、光CVD等で堆積する。第３
図（ｅ）は、TFT1及びTFT2の完成断面図である。第３図
（ｄ）の状態から、必要部分例えば第１ソース及びドレ
イン領域11、12や第２ソース及びドレイン領域111、112
に少なく共絶縁膜５にコンタクト開孔を設け、Al等の金
属膜を堆積、選択エツチして、第１ゲート電極14、第２
ゲート電極114、第１ソース及びドレイン配線31、32、
第２ソース及びドレイン配線131、132を形成したもので
ある。TFT1の第１ゲート絶縁膜13は絶縁膜５（23）と第
２半導体薄膜４（33）の２層で、TFT2の第２ゲート絶縁
膜113は絶縁膜５でのみ形成される。本装置に不要な第
２高抵抗半導体薄膜４は、前記コンタクト開孔時に除去
できるし、または第３図（ｅ）の状態後に第１及び第２
ゲート電極13、113等金属膜をマスクにしても除去でき
る。
本例以外に、ソース及びドレイン領域の形成には不純
物のイオン注入も利用できる。また第１高抵抗半導体薄
膜10の抵抗率や導電型は、ビームアニール前または後の
イオン注入によつても制御できる。
c. 実施例３（第４図）
第４図は、本TFT装置を液晶表示装置に適用した場合
の構造断面例を示す。ビームアニールされたTFT1は例え
ば表示駆動の周辺回路に、ａ−Siを用いたTFT2は各画素
部のスイツチに用いることができる。各画素電極はTFT2
の第２ソース電極121としてITO等の透明導電膜で容易に
形成される。第２ソース及びドレイン領域111、112を形
成後、第２高抵抗半導体薄膜110、33堆積前にITOを堆
積、選択エツチして上記の第２ソース電極（画素電極）
121、必要に応じ第２ドレイン電極122、第１ソース及び
ドレイン電極21、22を設けることにより可能である。本
例では、不要な第２高抵抗半導体薄膜（110、33）はコ
ンタクト開孔時または表面保護膜７形成時に除去でき
る。この例では、TFT1の第１ドレイン配線32とTFT2の第
２ゲート電極114を接続した構造を示した。
d. 実施例４（第５図）
第５図は第４図と同様、画素電極121を設けた例を示
した。この例では、TFT1とTFT2の第１及び第２ドレイン
領域12、112、第１及び第２ドレイン電極22、122、その
配線32、132を連続させて接続させている。不要な第２
高抵抗半導体薄膜（110、33）は、コンタクト開孔時に
除去した例である。
〔発明の効果〕
以上の様に本発明によれば、ａ−Siを用いた第2TFTの
（第２）ソース及びドレイン領域は多結晶または単結晶
Siを用いるので、オン抵抗の小さい良好な特性が得られ
ると共に、金属電極の位置に従来例（第２図）の様な制
約がない。そのため金属との反応のためTFT特性が劣化
することが少ない利点をもつ。また、ビームアニールさ
れた第1TFTの（第１）ゲート絶縁膜の一部に第２高抵抗
半導体薄膜を挿入することにより、第２高抵抗半導体薄
膜の選択エツチによる第１高抵抗半導体薄膜表面の損傷
をなくすことができると共に、マスク工程数も減少でき
る利点がある。さらに第２高抵抗薄膜は非常に薄いた
め、第2TFTの遮光も不要にできる。この様な利点を有し
ているため、本発明は周辺駆動回路を同一基板上に有し
たTFT液晶表示装置やイメージセンサ等ａ−SiTFTと高速
TFTを混在するTFT装置に最適である。
以上に主に、第2TFTにａ−Siを利用する例を述べてき
たが多結晶Siでもよい。またSi薄膜を用いるだけでなく
他の半導体薄膜を用いる場合、また第１高抵抗半導体薄
膜と第２高抵抗半導体薄膜が異なる材料の場合にも適用
される。The present invention relates to a thin film transistor (TFT) device, in particular, a polycrystalline or single-crystal semiconductor thin film formed of a first TFT having a channel region and a polycrystalline semiconductor having a smaller grain size. Or two kinds of TFTs, the second TFT having an amorphous semiconductor thin film in the channel region
And a method for manufacturing the same. [Summary of the Invention] A semiconductor thin film that has been subjected to beam annealing is used for the channel region, source and drain regions of the first TFT, and for the source and drain regions of the second TFT. The second TFT is
A channel region of the second semiconductor thin film deposited thereafter, a gate insulating film and a gate electrode thereon are provided. First TF
T is a second semiconductor thin film and a second TFT as a gate insulating film.
Has a two-layered film of the gate insulating film. This makes it possible to reduce the source-drain series resistance of the second TFT and to facilitate the manufacture of a TFT device having two types of TFTs. [Prior Art] A TFT using amorphous silicon (a-Si) can be formed in a large area at a low temperature, and is being applied to a liquid crystal display device and the like. However, since the carrier mobility of a-Si is small, the high-speed operation is limited, and the application range is limited. One solution to this problem is to crystallize a-Si by annealing using an energy beam such as a laser beam or an electron beam. Fig. 2 shows TFT1 by beam annealing.
A cross-sectional example of a TFT device in which TFT 2 using a-Si and TFT2 are mounted will be described, and problems will be described. The TFT 1 on the insulating substrate 1 made of glass, quartz, or the like includes a first high-resistance semiconductor thin film 10 that has been subjected to beam annealing, a first source region 11, a first drain region 12, and a first drain region 12 made of a first low-resistance semiconductor thin film thereon. Gate insulating film 1
3, a first gate electrode 14 thereon, and a first source wiring 31 and a first drain wiring 32 are provided as necessary. In order to improve the uniformity of beam annealing and prevent impurity re-diffusion, it is desirable to first form the first high-resistance thin film 10, and this structural example of the TFT 1 is one of the most suitable. On the other hand, TFT2 having a structure that is easy to be mounted together with TFT1 includes a second source region 111 and a second drain region, which are second low-resistance thin films on a second high-resistance semiconductor film (a-Si film) 110, and a second gate insulating film. 11
3. It comprises the second gate electrode 114. In general, when the second low-resistance thin film is formed of an a-Si film, the resistance is not sufficiently small, so that a second source electrode 121 and a second drain electrode 1 made of metal or the like are formed thereon.
22 is required. In this structural example, the first gate insulating film 13 and the second gate insulating film 113, the first and second source regions 11, 111
And the first and second drain regions 12, 112, the first gate electrode 1
The fourth and second gate electrodes 114 have the advantage that they can be formed simultaneously, but have the following problems. (1) When the thickness of the first high-resistance semiconductor thin film 10 and the thickness of the second high-resistance semiconductor thin film 110 are different, they cannot be simultaneously deposited, so that the number of deposition steps increases and the number of mask steps increases. (2) Since the second semiconductor thin film 110 and the second gate insulating film 113 cannot be continuously deposited, there is a problem in TFT2 characteristics. (3) If an a-Si film is used for the first low-resistance thin films 11 and 12, the resistance is large and there is a problem in the characteristics of the TFT1. (4) In order to avoid the problem (3), the first low-resistance thin film 11,
When beam annealing 12 is performed, it becomes a problem when to form the second source and drain electrodes 121 and 122 of TFT2, which also leads to an increase in the number of steps. If the gate electrode conventionally used in a-Si TFTs as the TFT 2 has an inverted staggered structure below, the number of deposited layers and the number of masks increase. [Problems to be Solved by the Invention] The present invention has been made in view of the problems described above,
An object of the present invention is to provide a structure in which a beam-annealed TFT and a non-beam-annealed TFT are easily mixed and a manufacturing method thereof. Another object is to make the characteristics of the two TFTs sufficiently satisfactory. [Means for Solving the Problems] The present invention relates to a TFT device in which a first TFT and a second TFT provided on an insulating substrate are shared less, and the first TFT comprises a first high-resistance semiconductor thin film on the substrate. A first channel region, a first source region and a first drain region made of a first low resistance semiconductor thin film of one conductivity type, a first gate insulating film on the first high resistance thin film, and a first gate thereon It is at least composed of electrodes. The second TFT is a second type of one conductivity type provided on the substrate.
A second source region and a second drain region made of a low-resistance semiconductor thin film, a second channel region made of a second high-resistance semiconductor thin film in contact with both regions, a second gate insulating film on the second high-resistance thin film, and a second gate insulating film on the second gate insulating film And a second gate electrode. Whereas the second high-resistance thin film is amorphous or polycrystalline, the first high-resistance thin film, the first and second low-resistance thin films are made of polycrystalline or polycrystalline having a larger particle size than the second high-resistance thin film by beam annealing or the like. It is a single crystal. The first gate insulating film is formed of a two-layer film of an insulating film provided simultaneously with the second gate insulating film and a second high-resistance thin film, and the first gate electrode and the second gate electrode are formed simultaneously. In the manufacture, a high-resistance semiconductor thin film is deposited on an insulating substrate, beam-annealed to form a first high-resistance semiconductor thin film, and selectively doped with one conductivity type impurity to form a first source / drain region and a second source. And the first high-resistance semiconductor thin film is selectively etched to leave the first source and drain regions of the first TFT, the first channel region, and the second source and drain regions of the second TFT. Next, a second high-resistance semiconductor thin film and an insulating film are successively deposited, and first and second gate electrodes are formed. [Function] As described above, since the second source and drain regions of the second TFT can be made of polycrystal or single crystal having a large grain size, good characteristics with small series resistance can be obtained,
A second source electrode 121 made of a metal like TFT2 in FIG. 2;
The second drain electrode 122 is connected to the second source / drain region 11
It is not necessary to provide the same shape as 1 and 112. Since the second high-resistance semiconductor thin film can be deposited independently of the first high-resistance semiconductor thin film, each thickness can select an optimal value of each TFT. No. 2
Since the second high-resistance thin film and the second gate insulating film of the TFT can be continuously deposited, variations in threshold voltage and on-current caused by contamination or damage of the interface between them can be suppressed. Further, a second high-resistance semiconductor thin film is added to the first gate insulating film of the first TFT, but is generally thin, has a large dielectric constant, and is several orders of magnitude higher in resistivity than the first high-resistance thin film. It can be used as a part of one gate insulating film. EXAMPLES The present invention will be described below in detail with reference to the drawings. a. First Embodiment (FIG. 1) FIG. 1 shows a first TFT (TFT1) and a second TFT (TFT) according to the present invention.
2 is an example of a sectional structure of a TFT device in which 2) is mounted. Insulating substrate 1 such as glass, quartz, semiconductor or conductor substrate coated with insulating film
Two types of TFT1 and TFT2 are mounted on the top. The TFT 1 includes a first channel region formed of a first high-resistance semiconductor thin film provided on a substrate 1 and a first p-type or n-type first region provided on both sides thereof.
It comprises a first source region 11, a first drain region 12 made of a low resistance semiconductor thin film, a first gate insulating film 13 on the first channel region 10, and a first gate electrode 14 thereon. TF
T2 is defined by a second source region 111 and a second drain region 112 formed of a p-type or n-type second low-resistance semiconductor thin film provided on the substrate 1 and separated from each other, and a second high-resistance semiconductor thin film in contact with both regions. A second channel region 110 and a second
It comprises a gate insulating film 113 and a second gate electrode 114. First
The source and drain regions 11 and 12 and the second source and drain regions 111 and 112 have the same conductivity type, and the first and second channel regions 10 and 10 are made of a polycrystalline or single crystal having a larger particle size than the second channel region 110. It is provided by annealing or the like. The second channel region 110 (second high-resistance thin film) is made of amorphous or polycrystal having a small grain size. The first gate insulating film 13 is formed of a two-layer film of the insulating film 23 deposited simultaneously with the second high-resistance semiconductor thin film 33 and the second gate insulating film 113. First and second
The gate electrodes 14 and 114 are simultaneously formed of a metal film or the like, but if necessary, the first source wiring 31 and the first drain wiring 32 of the TFT 1, the second source wiring 131 of the TFT 2, and the second drain wiring 1
There are also 32. The first and second source regions 1
1, 111 and the first and second drain regions 12, 112 have sufficiently low resistance to use the beam-annealed first and second low-resistance semiconductor thin films. The two source electrodes 21 and 121 and the first and second drain electrodes 22 and 122 only need to be in contact with a part of each of the regions 11, 111, 12, and 112. It is desirable that the second high-resistance semiconductor thin films 110 and 33 are very thin in view of the optical characteristics of the TFT2 and the application of the gate voltage of the TFT1, and a value of, for example, 500 ° or less is selected.
On the other hand, the thickness of the first high-resistance semiconductor thin film 10 is selected based on the required characteristics of the TFT 1 and the ease of beam annealing.
0.2-0.5μ is selected. First and second high resistance semiconductor thin films
The conductivity type and resistivity of 10, 110 (33) are selected according to the desired characteristics of TFT1 and TFT2. b. Example 2 Manufacturing Process (FIG. 3) FIG. 3 is a cross-sectional view along a manufacturing process of the TFT device according to the present invention. FIG. 3A shows an amorphous or polycrystalline high-resistance semiconductor thin film 2 deposited on an insulating substrate 1 and subjected to beam annealing to form a polycrystalline or single-crystal first high-resistance semiconductor thin film 10 having a large grain size. This shows the formed state. As the high resistance semiconductor thin film 2, an a-Si film or a polycrystalline Si film is mainly used. For beam annealing, Ar, YAG, excimer laser, electron beam,
An energy beam such as a lamp or a heater is used, and the example of FIG. When using a CW laser or an electron beam, selective annealing is effective for improving throughput. FIG. 3B shows a state in which the low-resistance semiconductor thin film 3 containing impurities is deposited, and at least the low-resistance thin film 3 on the channel region of the first TFT (TFT1) is removed. P, A as impurities
s, Sb, B, etc. are used.
An i film or a polycrystalline Si film is used, and has a thickness of 100 to 1000 mm. FIG. 3 (c) shows that the low-resistance semiconductor thin film 3 is crystallized by beam annealing again in the state of FIG. 3 (b), and the impurities are diffused into the first high-resistance semiconductor thin film 10; First source and drain regions 11, 12 and a first high-resistance semiconductor thin film (channel region) 10 and TF between them.
The state where the second source and drain regions 111 and 112 of T2 are selectively etched is shown. It is desirable to perform the beam annealing again at a low power and a high scanning speed so as not to melt the low-resistance semiconductor thin film 3 in order not to increase the lateral redistribution of impurities. FIG. 3D shows a state in which the second high-resistance semiconductor thin film 4 and the insulating film 5 are continuously deposited. The second high-resistance semiconductor thin film 4 has an a-Si: H film or the like having a thickness of 100 to 500 °, and the insulating film 5 has an SiOx film or a SiNx film having a thickness of 1000 to 500 °.
Deposit by plasma CVD, optical CVD, etc. to a thickness of 3000mm. Third
FIG. 4E is a completed sectional view of TFT1 and TFT2. From the state of FIG. 3 (d), necessary parts such as the first source and drain regions 11, 12 and the second source and drain regions 111, 112
A contact opening is provided in the co-insulating film 5 and a metal film such as Al is deposited and selectively etched to form the first gate electrode 14 and the second gate electrode 14.
A gate electrode 114, first source and drain wirings 31, 32,
The second source and drain wirings 131 and 132 are formed. The first gate insulating film 13 of TFT1 is formed of two layers of the insulating film 5 (23) and the second semiconductor thin film 4 (33), and the second gate insulating film 113 of TFT2 is formed of only the insulating film 5. The second high-resistance semiconductor thin film 4 unnecessary for the present device can be removed at the time of opening the contact, or the first and second high-resistance semiconductor thin films 4 can be removed after the state shown in FIG.
The gate electrodes 13 and 113 can be removed using a metal film as a mask. In addition to this example, ion implantation of impurities can be used for forming the source and drain regions. The resistivity and conductivity of the first high-resistance semiconductor thin film 10 can also be controlled by ion implantation before or after beam annealing. c. Third Embodiment (FIG. 4) FIG. 4 shows an example of a structural cross section when the present TFT device is applied to a liquid crystal display device. The beam-annealed TFT 1 can be used, for example, as a peripheral circuit for display driving, and the TFT 2 using a-Si can be used as a switch in each pixel unit. Each pixel electrode is TFT2
The second source electrode 121 is easily formed of a transparent conductive film such as ITO. After the second source and drain regions 111 and 112 are formed, ITO is deposited and selectively etched before depositing the second high-resistance semiconductor thin films 110 and 33, and the second source electrode (pixel electrode) is formed.
121, if necessary, by providing a second drain electrode 122 and first source and drain electrodes 21 and 22. In this example, the unnecessary second high-resistance semiconductor thin films (110, 33) can be removed at the time of opening the contact or at the time of forming the surface protection film 7. In this example, a structure in which the first drain wiring 32 of TFT1 and the second gate electrode 114 of TFT2 are connected is shown. d. Embodiment 4 (FIG. 5) FIG. 5 shows an example in which the pixel electrode 121 is provided, as in FIG. In this example, the first and second drain regions 12 and 112 of TFT1 and TFT2, the first and second drain electrodes 22 and 122, and the wirings 32 and 132 thereof are continuously connected. Unnecessary second
The high-resistance semiconductor thin films (110, 33) are examples removed at the time of contact opening. [Effects of the Invention] As described above, according to the present invention, the (second) source and drain regions of the second TFT using a-Si are polycrystalline or single crystal.
Since Si is used, good characteristics with low on-resistance can be obtained, and the position of the metal electrode is not restricted as in the conventional example (FIG. 2). Therefore, there is an advantage that TFT characteristics are hardly deteriorated due to a reaction with a metal. In addition, by inserting the second high-resistance semiconductor thin film into a part of the (first) gate insulating film of the first TFT subjected to the beam annealing, the surface of the first high-resistance semiconductor thin film is selectively etched by the second high-resistance semiconductor thin film. There is an advantage that damage can be eliminated and the number of mask steps can be reduced. Further, since the second high-resistance thin film is very thin, light shielding of the second TFT can be unnecessary. Because of these advantages, the present invention is faster than a-Si TFTs such as TFT liquid crystal displays and image sensors that have peripheral driver circuits on the same substrate.
Most suitable for TFT devices with mixed TFTs. Although an example in which a-Si is used for the second TFT has been mainly described above, polycrystalline Si may be used. Further, the present invention is also applied to a case where not only the Si thin film is used but also another semiconductor thin film is used, and a case where the first high-resistance semiconductor thin film and the second high-resistance semiconductor thin film are made of different materials.
【図面の簡単な説明】
第１図は本発明によるTFT装置の構造断面図、第２図は
従来技術によるTFT装置の断面図、第３図（ａ）〜
（ｅ）は本発明によるTFT装置の製造工程順断面図、第
４図及び第５図はそれぞれ本発明によるTFT装置の応用
例の断面図である。
１……絶縁基板、10……第１高抵抗半導体薄膜または第
１チヤンネル領域、11……第１ソース領域、12……第１
ドレイン領域、13……第１ゲート電極、14……第１ゲー
ト電極、110……第２高抵抗半導体薄膜または第２チヤ
ンネル領域、111……第２ソース領域、112……第２ドレ
イン領域、113……第２ゲート絶縁膜、114……第２ゲー
ト電極BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural sectional view of a TFT device according to the present invention, FIG. 2 is a sectional view of a TFT device according to the prior art, and FIGS.
(E) is a sectional view of a TFT device according to the present invention in the order of the manufacturing process, and FIGS. 4 and 5 are sectional views of an application example of the TFT device according to the present invention. 1 ... insulating substrate, 10 ... first high-resistance semiconductor thin film or first channel region, 11 ... first source region, 12 ... first
A drain region, 13 a first gate electrode, 14 a first gate electrode, 110 a second high resistance semiconductor thin film or a second channel region, 111 a second source region, 112 a second drain region, 113: second gate insulating film, 114: second gate electrode
Claims (1)
と、第２の薄膜トランジスタを有する薄膜トランジスタ
装置であって、 前記第１の薄膜トランジスタは、第１高抵抗半導体薄膜
に互いに離間して設けられた一導電型の第１低抵抗半導
体薄膜よりなる第１ソース領域及び第１ドレイン領域
と、前記第１ソース領域と前記第１ドレイン領域の間の
前記第１高抵抗半導体薄膜よりなる第１チャンネル領域
と、前記第１チャンネル領域上に設けられた第１ゲート
絶縁膜と、前記第１ゲート絶縁膜上に設けられた第１ゲ
ート電極とを備え、 前記第２の薄膜トランジスタは、前記基板上に互いに離
間して設けられた一導電型の第２低抵抗半導体薄膜より
なる第２ソース領域及び第２ドレイン領域と、前記第２
ソース領域と前記第２ドレイン領域にまたがって非晶質
もしくは多結晶の第２高抵抗半導体薄膜により形成され
た第２チャンネル領域と、前記第２チャンネル領域上に
設けられた第２ゲート絶縁膜と、前記第２ゲート絶縁膜
上に設けられた第２ゲート電極と、を備え、 前記第１高抵抗半導体薄膜、前記第１低抵抗半導体薄
膜、および前記第２低抵抗半導体薄膜は、前記第２高抵
抗半導体薄膜より粒径の大きい多結晶もしくは単結晶の
半導体薄膜であり、 前記第１ゲート電極と前記第２ゲート電極が同一の導電
膜で形成されていることを特徴とする薄膜トランジスタ
装置。 ２．前記第１ゲート絶縁膜は、前記第２高抵抗半導体薄
膜と前記第２ゲート絶縁膜との同一材料で形成された二
層膜であることを特徴とする特許請求の範囲第１項記載
の薄膜トランジスタ装置。 ３．前記第１低抵抗半導体薄膜と前記第２低抵抗半導体
薄膜が同一の材料で形成されていることを特徴とする特
許請求の範囲第１項記載の薄膜トランジスタ装置。 ４．前記第１高抵抗半導体薄膜、前記第１低抵抗半導体
薄膜、および前記第２低抵抗半導体薄膜は、非晶質もし
くは多結晶の半導体薄膜をエネルギービームによりアニ
ールされた半導体薄膜であることを特徴とする特許請求
の範囲第１項または第２項記載の薄膜トランジスタ装
置。 ５．絶縁基板上に非晶質もしくは多結晶の高抵抗半導体
薄膜を堆積し、エネルギービームで第１アニールをして
粒径の大きい多結晶もしくは単結晶の半導体薄膜である
第１高抵抗半導体薄膜を形成する第１工程と、 第１ソース領域及び第１ドレイン領域と、第２ソース領
域及び第２ドレイン領域となる前記第１高抵抗半導体薄
膜の部分に一導電型不純物を選択的に添加する第２工程
と、 前記第１ソース領域、前記第１ドレイン領域、及び、両
領域に挟まれる前記第１高抵抗半導体薄膜からなる第１
チャネル領域、を含んだ島状領域を形成するとともに、
前記不純物が添加された第１高抵抗半導体薄膜から前記
第２ソース領域と前記第２ドレイン領域をそれぞれ島状
に形成する第３工程と、 非晶質もしくは多結晶の第２高抵抗半導体薄膜と絶縁膜
を連続して堆積する第４工程と、 前記島状領域の上に第１ゲート電極を、前記第２ソース
領域と前記第２ドレイン領域にまたがった絶縁膜上に第
２ゲート電極を形成する第５工程と、 を有することにより、 前記第１ソース領域、前記第１ドレイン領域、前記第１
チャネル領域、前記絶縁膜と前記第２高抵抗半導体薄膜
からなる第１ゲート絶縁膜、および、前記第１ゲート電
極と、を備える第１の薄膜トランジスタと、 前記第２ソース領域、前記第２ドレイン領域、前記第２
高抵抗半導体薄膜からなる第２チャンネル領域、前記絶
縁膜からなる第２ゲート絶縁膜、および、前記第２ゲー
ト電極と、を備える第２の薄膜トランジスタと、 を形成することを特徴とする薄膜トランジスタ装置の製
造方法。 ６．前記第２工程が、前記第１高抵抗半導体薄膜上に一
導電型の低抵抗半導体薄膜を堆積する工程と、前記第１
チャンネル領域上の前記低抵抗半導体薄膜を選択的に除
去する工程と、エネルギービームによる第２アニールに
よって前記低抵抗半導体薄膜を大粒径化するとともに前
記第１高抵抗半導体薄膜内に一導電型不純物を拡散させ
る工程と、を含むことを特徴とする特許請求の範囲第５
項記載の薄膜トランジスタ装置の製造方法。 ７．前記第１アニールが、前記第１ソース領域、前記第
１チャンネル領域、前記第１ドレイン領域、前記第２ソ
ース領域、および、前記第２ドレイン領域となるべき部
分を選択的に、粒径の大きい多結晶もしくは単結晶の第
１高抵抗半導体薄膜とすることを特徴とする特許請求の
範囲第５項または第６項記載の薄膜トランジスタ装置の
製造方法。(57) [Claims] A thin film transistor device including a first thin film transistor provided on an insulating substrate and a second thin film transistor, wherein the first thin film transistor is a one-conductivity type thin film transistor provided on a first high-resistance semiconductor thin film at a distance from each other. A first source region and a first drain region made of a first low-resistance semiconductor thin film; a first channel region made of the first high-resistance semiconductor thin film between the first source region and the first drain region; A first gate insulating film provided on the one channel region; and a first gate electrode provided on the first gate insulating film, wherein the second thin film transistor is provided on the substrate at a distance from each other. A second source region and a second drain region made of a second low-resistance semiconductor thin film of one conductivity type;
A second channel region formed of an amorphous or polycrystalline second high-resistance semiconductor thin film over the source region and the second drain region; and a second gate insulating film provided on the second channel region. A second gate electrode provided on the second gate insulating film, wherein the first high-resistance semiconductor thin film, the first low-resistance semiconductor thin film, and the second low-resistance semiconductor thin film are the second high-resistance semiconductor thin film. A thin film transistor device, which is a polycrystalline or single crystal semiconductor thin film having a larger particle diameter than a high resistance semiconductor thin film, wherein the first gate electrode and the second gate electrode are formed of the same conductive film. 2. 2. The thin film transistor according to claim 1, wherein the first gate insulating film is a two-layer film formed of the same material as the second high-resistance semiconductor thin film and the second gate insulating film. apparatus. 3. 2. The thin film transistor device according to claim 1, wherein said first low-resistance semiconductor thin film and said second low-resistance semiconductor thin film are formed of the same material. 4. The first high-resistance semiconductor thin film, the first low-resistance semiconductor thin film, and the second low-resistance semiconductor thin film are semiconductor thin films obtained by annealing an amorphous or polycrystalline semiconductor thin film with an energy beam. The thin film transistor device according to claim 1 or 2, wherein: 5. Depositing an amorphous or polycrystalline high-resistance semiconductor thin film on an insulating substrate and performing a first anneal with an energy beam to form a first high-resistance semiconductor thin film that is a polycrystalline or single-crystal semiconductor thin film having a large grain size A first step of selectively adding one-conductivity-type impurity to portions of the first high-resistance semiconductor thin film that will be the first source region and the first drain region and the second source region and the second drain region. A first source region, a first drain region, and a first high-resistance semiconductor thin film sandwiched between both regions.
Forming an island-like region including a channel region,
A third step of forming the second source region and the second drain region in an island shape from the first high-resistance semiconductor thin film to which the impurity is added, respectively, an amorphous or polycrystalline second high-resistance semiconductor thin film; A fourth step of continuously depositing an insulating film; forming a first gate electrode on the island-like region, and forming a second gate electrode on the insulating film over the second source region and the second drain region. A fifth step of forming the first source region, the first drain region, and the first
A first thin film transistor including a channel region, a first gate insulating film including the insulating film and the second high-resistance semiconductor thin film, and the first gate electrode; a second source region and a second drain region , The second
A second thin-film transistor comprising: a second channel region made of a high-resistance semiconductor thin film; a second gate insulating film made of the insulating film; and the second gate electrode. Production method. 6. The second step: depositing a one-conductivity-type low-resistance semiconductor thin film on the first high-resistance semiconductor thin film;
Selectively removing the low-resistance semiconductor thin film on the channel region, and enlarging the low-resistance semiconductor thin film by a second annealing with an energy beam, and adding one conductivity type impurity in the first high-resistance semiconductor thin film. And a step of diffusing
13. The method for manufacturing a thin film transistor device according to claim 10. 7. The first annealing selectively increases the grain size of the first source region, the first channel region, the first drain region, the second source region, and a portion to be the second drain region. 7. The method for manufacturing a thin film transistor device according to claim 5, wherein the first high resistance semiconductor thin film is made of polycrystal or single crystal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21296785A JP2779492B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21296785A JP2779492B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6273660A JPS6273660A (en) | 1987-04-04 |
| JP2779492B2 true JP2779492B2 (en) | 1998-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21296785A Expired - Lifetime JP2779492B2 (en) | 1985-09-26 | 1985-09-26 | Thin film transistor device and method of manufacturing the same |
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| Country | Link |
|---|---|
| JP (1) | JP2779492B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01136373A (en) * | 1987-11-24 | 1989-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin-film semiconductor device |
| JP2717234B2 (en) * | 1991-05-11 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | Insulated gate field effect semiconductor device and method of manufacturing the same |
| JP2717237B2 (en) * | 1991-05-16 | 1998-02-18 | 株式会社 半導体エネルギー研究所 | Insulated gate semiconductor device and method of manufacturing the same |
| JP2845303B2 (en) * | 1991-08-23 | 1999-01-13 | 株式会社 半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
| KR950003235B1 (en) * | 1991-12-30 | 1995-04-06 | 주식회사 금성사 | Semiconductor device structure |
| US5485019A (en) * | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US5266515A (en) * | 1992-03-02 | 1993-11-30 | Motorola, Inc. | Fabricating dual gate thin film transistors |
| JP3424891B2 (en) | 1996-12-27 | 2003-07-07 | 三洋電機株式会社 | Method of manufacturing thin film transistor and display device |
| JP4647889B2 (en) * | 2003-04-25 | 2011-03-09 | 富士通セミコンダクター株式会社 | Method for manufacturing field effect transistor having Schottky source / drain structure |
-
1985
- 1985-09-26 JP JP21296785A patent/JP2779492B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| JPS6273660A (en) | 1987-04-04 |
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