JPS59124165A - Insulated gate type transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an IGFET characterized by high stability and reliability, by forming a source and a drain, wherein lift off of a gate pattern is adopted, by self-alignment, further introducing a second gate, and controlling a threshold voltage. CONSTITUTION:On a glass plate 1, an Mo second gate film 13 is selectively formed. Si3N4 14, amorphous Si 4 and Si3N4 3 are continuously deposited, and the characteristics are stabilized. Mo 2 and an Al thin film 15 are laminated. Then a laminated body of films 15', 2', 3' is formed and coated by an amorphous thin film 5, to which impurities are added. Selective etching is performed together with the film 4. Lift off is performed and island shaped layers 4' and 5' are formed. The Al 15' is exposed at the side surface. The Al 15' is fused away and the Mo gate 2' is exposed. The surface is coated by Si3N4 17. Source and drain wirings of Al 7 and 8, a gate wiring 9, and a second gate taking out electrode 20 are attached. In this constitution, since there is no overlapped part at the end parts of source and drain 10 and 11 and the gate electrode 2', electrostatic capacity is less. The device is suitable for high speed operation. The layer 4 is protected by the insulating films 14, 17, and 2'. Threshold value control is easy. Stability and reliability are high.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an insulated gate type (MI'S) transistor and an amorphous silicon MIS transistor.

Conventional structure and its problems Amorphous silicon, which is formed by containing a few hydrogen or fluorine in its composition to compensate for imperfections in atomic bonding pairs, can be formed at low temperatures. Conductor materials are attracting attention as they are suitable for producing low-cost solar cells because they can be easily made into large-area materials.

However, compared to single-crystal silicon, the free electron mobility is 0.1 to 1 cr/V·turret, which is more than three orders of magnitude lower, making it impossible to obtain a rod conductor element worthy of integration. Even so, high-speed motion fi1' and large on-current are not required. For example, by combining it with a liquid crystal, it is possible to obtain a switching array of MIS transistors constituting an image display device.

Figures 1 and 2 are a plan view of an amorphous silicon MIS transistor developed to achieve the above purpose, and a cross-sectional view of the manufacturing process along the line A-A/ in Figure 1. is the same as described below.

First, as shown in FIG. 2a, a first metal layer, such as a molybdenum layer 2, constituting a gate electrode is selectively formed on an insulating substrate 1, such as a glass plate.

Next, a first insulating layer 3 made of silicon nitride, for example, is applied over the entire surface. An impurity-free amorphous silicon layer 4 serving as a donor or acceptor and an impurity-containing amorphous silicon layer 5 are successively formed. A simple method for forming these thin films is plasma deposition using gelatin discharge of a silane-based gas; ammonia is used to form the gate insulating layer 3, and diborane or diborane is used to form amorphous silicon containing impurities. Phosphine may be added to the production gas.

Thereafter, as shown in FIG. 2, the amorphous silicon layer 4.6 is selectively removed to form island-shaped amorphous silicon layers 4', 5.
' to form. Furthermore, although not shown in FIG. 2, an opening 6 (shown in FIG. 1) is formed in the gate insulating layer 3 of the first metal layer 2.
After forming a part of the first metal layer 2 and exposing a part of the first metal layer 2, as shown in FIG.
As shown in FIG. 2, a pair of source and drain wirings 7 and 8 made of a second metal layer partially overlapping the first metal layer 2 are selectively deposited to avoid an offset gate structure. Of course, at this time, a gate lead-out wiring 9 made of the second metal layer is also formed on the gate insulating layer 3 including the opening 6. Finally, as shown in FIG. 2d, the impurity-containing amorphous silicon layer 5' on the impurity-free amorphous silicon layer 4 is selectively removed using the source and drain wirings 7 and 8 as masks. An amorphous silicon MIS transistor with a conventional structure is completed.

In addition, the source and drain wirings 7 and 8 and the amorphous silicon layer 4'
The impurity-containing amorphous silicon layer 6' and the silicon layer 10.11 interposed between the amorphous silicon layer 10.11 are necessary for forming a good ohmic contact.
Although it is possible to operate as a MIS transistor even if 11 is not present, there is an unavoidable tendency for the operating voltage to increase, so in that case, be careful about the material and deposition method of the source and drain wirings 7 and 8. is necessary. If the amorphous silicon layer 10.11 containing impurities is present, common aluminum is sufficient for the source and drain wirings 7 and 8.

Now, in the structure shown in FIG. 2d, the gate metal layer 2 and the source and drain 10 and 11 are not in a self-aligned positional relationship;
The planar overlap of the gate metal layer 2 and the sources and drains 10 and 11 forms an overlap capacitance in which the impurity-free amorphous silicon 4' and the gate insulating layer 3 form a laminated dielectric. MIS) The channel width of the transistor is 100 μm, the amorphous silicon layer 4 and the gate insulating layer 3 made of silicon nitride.
When the film thicknesses of the gate and source are 6000A and 4000A, respectively, and the overlap between the gate, source, and drain is 5μm, the gate,
The overlap capacitance between the source, gate, and drain is only 1P at most. However, the effective area is 10○～
The capacitance component of a 150 μm square liquid crystal cell is only o,1
It is approximately equal to the overlapping capacity described above. For this reason, the potential of the liquid crystal cell, which is a load connected to the source or drain, varies significantly at the rise and fall of a gate pulse applied to turn on and off the MIS transistor. If you measure the potential stability and connect an auxiliary capacitor in parallel with the liquid crystal cell, which is much larger than the capacitor, the MI
The auxiliary capacitor will not be charged to a predetermined potential unless the ON current of the S transistor is increased or the write time is lengthened. However, the former requires an increase in the mobility of amorphous silicon, which is difficult at present, and the latter does not allow a large number of scanning lines, so currently the liquid crystal cell size is 1.
A small-scale image display device with a large stone corner and a number of picture elements of about 20×20 has not yet been obtained.

The next problem arises with passivation in Figure 2C.
The impurity-containing amorphous silicon layer 5 shown in FIG. 1 is selectively removed using the source and drain wirings 7 and 8 as a mask, but if the removal is insufficient, leakage current between the source and drain will increase. In addition, there is no etching method that etches only the amorphous silicon layer containing impurities.
An amorphous silicon layer 4' containing no impurities on the over-eaten side
Generally, a portion of the groove is removed to form the concave shape 12. As a result, the thickness of the channel portion is reduced. Furthermore, since the opposite side of the channel is exposed to the outside air, moisture in the atmosphere is likely to be adsorbed. The OH- group in the adsorbed water makes the channel part P
The threshold voltage of an n-channel MIS transistor increases over time. However, it was found that the adsorbed moisture was lost by heating in dry nitrogen gas at about 150 C, and the properties returned to the properties immediately after manufacture. Therefore, a passivation film is required to protect the amorphous silicon layer constituting the channel portion.

A further problem is that it is difficult to control the threshold voltage of MIS transistors.As is well known, the following methods are available for controlling the threshold voltage of single crystal silicon MO3) transistors. Common. First, in terms of process, it was possible to change the thickness of the gate oxide film or change the impurity concentration in the channel part, and for driving, it was possible to use a so-called substrate bias that changes the potential of the channel part. However, amorphous silicon, which does not contain impurities, has a high local level density, so even if impurities that serve as donors or acceptors are introduced, the Fermi level does not move easily, and although it is an intrinsic, it is a weak n-type flat conductor. be.

Therefore, if a large amount of impurity is introduced to increase the conductivity or change the conductivity type, a large number of impurity atoms will not enter lattice positions but will remain between the lattices, increasing the defect level density of amorphous silicon, and the film quality will be reversed. Therefore, it is meaningless to change the impurity concentration of the amorphous silicon layer constituting the channel portion. In addition, it is easy to understand that in amorphous silicon that does not contain impurities, the depletion layer changes less due to the apparent substrate bias, and the control range of the threshold voltage becomes narrower.゛The remaining method is to change the thickness of the gate insulating layer, but in amorphous silicon M-S transistors, hydrogen and fluorine to compensate for the incompleteness of atomic bond pairs can be easily removed by heating. Since the gate insulating layer is formed by low-temperature CV
Plasma deposition using D or glow discharge must be employed. However, these deposition methods have the drawback that the composition ratio is not stable when the film thickness is less than 1000 nm, and the threshold value of the MIS transistor increases. On the other hand, if it is thicker, MI
S) Since the mutual conductance of the transistor becomes small, this becomes a fatal constraint for amorphous silicon, which has low mobility.

Purpose of the Invention The present invention has been made in view of the above circumstances, and provides an MIS (MIS) which has passivation, has a source and drain formed in a self-aligned manner, and whose threshold voltage can be easily controlled.
The purpose is to provide transistors.

Structure of the Invention The present invention employs lift-off of the gate pattern so that the source 9 drain is formed in a self-aligned manner, and a second gate is introduced to control the threshold voltage. Let me explain with an example. For convenience, parts with the same functions are given the same numbers as in FIGS. 1 and 2.

DESCRIPTION OF EMBODIMENTS FIGS. 3 and 4 a to d show M according to an embodiment of the present invention.
These are a plan view of the IS transistor and a cross-sectional view of the manufacturing process along the line A-A' in FIG. 3, and the manufacturing process is as described below in C. First, as shown in FIG. 4a, a third metal layer 13 made of, for example, molybdenum and constituting the second gate is selectively formed. and a third insulating layer 14, for example silicon nitride. First amorphous silicon layer 4 containing no impurities
9. A first insulating layer 31 made of silicon nitride, for example, a first metal layer 2 made of molybdenum, for example, and a thin film layer 15 made of aluminum, for example, are successively deposited over the entire surface. At this time, the third insulating layer 14. If the first amorphous silicon layer 4 and the first insulating layer 3 are deposited continuously without being exposed to the atmosphere, it is possible to avoid contamination by the atmosphere between the insulating layer and the amorphous silicon layer. Instead, the adhesion between these thin films is strengthened, and the characteristics of the MIS transistor are stabilized.

Therefore, plasma deposition by glow discharge, as described above, is advantageous for the deposition of these thin films, and can be carried out in the same chamber or by using a vacuum conveyance path and a plurality of chambers.

Next, as shown in FIG. 4, a laminated portion consisting of a thin film layer 15', a first metal layer 2' and a first insulating layer 3' is formed. Thereafter, as shown in FIG. 4C, a second amorphous silicon layer containing an impurity serving as a donor or acceptor is deposited on the entire surface, and the first and second amorphous silicon layers, including the laminated portion, are deposited on the entire surface. The layers are selectively removed to form islands 4/ and 5/. Since the laminated portion has a thickness of 6,000 to 9,000 thick, if the second amorphous silicon layer 61 is 500 to 1,600 thick, the second amorphous silicon layer 61 is necessarily thin at the stepped portion 16 of the laminated portion. A step break occurs, and the side surface of the thin film layer 15' is exposed on the side surface of the laminated portion. Therefore, when left in hot phosphoric acid, the thin film layer 15' made of aluminum is dissolved, the second amorphous silicon layer on the thin film layer 15' is removed, and the gate metal layer 2 is removed.
' is exposed. Note that prior to depositing the second amorphous silicon layer, the butter width of the first insulating layer is adjusted to the first
If the pattern width is made smaller than the pattern width of the metal layer 2, the first insulating layer 3' becomes an eaves shape and the second amorphous silicon layer 5
Not only is the step-break at 10' ensured, but the phenomenon in which the second amorphous silicon layer 6' comes into contact with the first metal layer 21 along the side surface of the first insulating layer 3' is suppressed.

Subsequently, as shown in FIG. 4d, a second insulating layer 17 made of silicon nitride, for example, is applied over the entire surface, and an opening 18 is formed on the second amorphous silicon layer 10.11. An opening 6 is formed on the second metal layer 4', and an opening 6 is formed on the second metal layer 13'.
An opening 19 is formed above through the first and third insulators f@14, 17, and source and drain wirings 7°8, made of aluminum, for example, are formed through the openings 1B, 6 and 19, respectively. Amorphous silicon MI according to the present invention is formed by forming the first gate lead-out wiring 9 and the second gate lead-out wiring 20.
S) The transistor is completed.

As is clear from FIG. 4d, the amorphous silicon MIS transistor according to the present invention has a source.

The end of the drain 10.11 and the end of the first gate metal layer 2'' are on the same straight line and there is no planar overlap between them. This is because the source, drain io, ii This is because amorphous silicon containing impurities is formed by lift-off using a gate pattern.
The capacitance between the drains is reduced to ~1/loo compared to the conventional case without self-alignment, and the restrictions on pulsed operation are significantly relaxed.

Furthermore, an amorphous silicon layer 4' that does not contain impurities and constitutes a channel part of a transistor (MIS) is sandwiched between a first insulating layer 3' and a third insulating layer 14, and the source and drain wirings 7, 8, and further a second insulating layer 1
7, there is no possibility that the characteristics of the MIS transistor will be altered or changed due to the intrusion of moisture or impurities from the outside after the MIS transistor is manufactured. Also M
IS) Even during transistor manufacturing, the third insulating layer 14゜amorphous silicon layer 4' and first insulating layer 3' are formed continuously, so the connection between the most important insulating layer and the amorphous silicon layer is There is little fear of impurities entering the interface, and stability and reliability are dramatically improved.

When a DC potential is applied to the second gate metal layer 13, it is applied to the surface of the amorphous silicon layer 4' near the interface with the third insulating layer 13 via the third insulating layer 14, or to a DC potential supply source. When the value is large, charges corresponding to the sign of the DC potential can be excited in the entire amorphous silicon layer 4', so that the threshold value of the MIS transistor according to the present invention can be set to either positive or negative values.

This not only increases the degree of freedom in designing the E-E or E-D inverter circuit, but also increases or decreases the leakage current between the source and drain by one to two orders of magnitude when the potential of the first gate 4' is zero. It is also extremely easy.

The MIS transistor according to the present invention has a second gate 13 made of metal under the main surface in contact with the insulating substrate 1,
On the other main surface, there is a laminated portion composed of a gate insulating layer and a first gate 4' made of metal, and on a part thereof, source and drain wirings 10 and 11 having source and drain wirings are present. However, the sources and drains 10' and 11 are made of amorphous silicon containing impurities, and their absorption coefficient for visible light is as large as 10" cm-1, so they can be used for MIS transistors without particularly strict light shielding. Secondary effects such as no risk of increase in leakage current can also be obtained.

Effects of the Invention As stated above, the MI S transistor according to the present invention not only has excellent stability and reliability, but also
Low capacitance between source and drain, high on=off
It has an f-ratio and fast switching characteristics, and greatly contributes to the realization of an image display device.

It goes without saying that the gist of the present invention is not limited to amorphous silicon taken up in the embodiments, but is also applicable to microcrystalline silicon and polycrystalline silicon.

[Brief explanation of the drawing]

Fig. 1 is a plan view of an amorphous silicon MIS transistor with a conventional structure, Fig. 2 is a sectional view of the manufacturing process of the transistor shown in Fig. A plan view of a MIS transistor according to an embodiment of the present invention, and FIGS. 4a to 4d are cross-sectional views of the manufacturing process along line A-A' of the transistor in FIG. 3. 1. Insulating substrate; 2 .2'...1st
gate, 3.3'...first insulating layer, 4.4
'...First quality silicon, 5,5'...
...Second amorphous silicon, 7,8...Source, drain wiring, 9...First gate extraction wiring, 10,11...Source, drain , 13...
...Second gate, 14...Second insulating layer, 17...Third insulating layer, 20...Second gate lead wiring. Figure 1 Figure 2 Figure 2 Figure 3 Figure 4 Figure 5 (73

Claims (1)

[Scope of Claims] (Li) A first metal layer serving as a first gate is formed on an insulating substrate, and a first metal layer mainly composed of silicon is formed on the first metal layer via a first insulating layer. A first non-single-crystal semiconductor layer is formed in an island shape, and a laminated portion including a second insulating layer and a second metal layer serving as a second gate is formed on a part of the first non-single-crystal semiconductor layer. a second insulating layer containing impurities formed in a region other than the second insulating layer on the first non-single crystal semiconductor layer;
The non-single crystal semiconductor layer is used as a source and a drain, and a second metal layer is connected to the second metal layer through an opening formed in a third insulating layer deposited on the entire surface, and a second layer is connected to the source and drain, respectively.
A gate lead-out wiring and source and drain wiring are formed, and a first gate lead-out wiring is formed in the first metal through an opening formed by penetrating the third and first insulating layers. An insulated gate transistor characterized by: (2) The threshold voltage is controlled by applying a DC voltage to the first gate or the first gate lead wiring and changing the DC voltage. Insulated gate transistor. (3) A step of selectively forming a first metal layer on an insulating substrate, and a first insulating layer, a first non-single crystal semiconductor layer mainly composed of silicon, and a second insulating layer on the entire surface. , a step of sequentially forming a second metal layer and a thin film layer;
forming a laminated layer consisting of a metal layer and a second insulating layer to expose the first non-single crystal semiconductor layer; forming a second non-single crystal semiconductor layer containing impurities on the entire surface; ,
an island-shaped first layer including the laminated portion on the first metal layer;
≦− and a step of forming a second non-single crystal semiconductor layer, a step of selectively removing the second non-single crystal #: conductor layer on the thin film layer while removing the thin film layer, and a step of forming a third non-single crystal semiconductor layer on the entire surface. forming an insulating layer, forming the second non-single crystal semiconductor layer, a second metal layer, and a metal layer through an opening formed in the third insulating layer; forming a metal layer on a first metal layer through an opening formed through a first insulating layer. (4) Claim 3, characterized in that the first insulating layer, the first non-single crystal flat conductor layer, and the second insulating layer are formed continuously without being exposed to the atmosphere. As stated in? A method for manufacturing a three-edge gate type transistor.