JPH0544194B2 - - Google Patents
Info
- Publication number
- JPH0544194B2 JPH0544194B2 JP56201269A JP20126981A JPH0544194B2 JP H0544194 B2 JPH0544194 B2 JP H0544194B2 JP 56201269 A JP56201269 A JP 56201269A JP 20126981 A JP20126981 A JP 20126981A JP H0544194 B2 JPH0544194 B2 JP H0544194B2
- Authority
- JP
- Japan
- Prior art keywords
- inp
- film
- interface
- mis
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 22
- 150000001875 compounds Chemical class 0.000 claims description 9
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 238000010587 phase diagram Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910008065 Si-SiO Inorganic materials 0.000 description 1
- 229910006405 Si—SiO Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は、化合物半導体のMIS（Metal−
Insulator Semiconductor）型半導体装置に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention provides MIS (Metal-
Insulator Semiconductor) type semiconductor device.
GaAs，InP等化合物半導体は、Siより大きな
電子移動度、および飽和速度を有するため高速素
子に適しており、すでにGaAs MESFET（Metal
Semiconductor FET）が実用化されている。近
年これらの材料の高速性を生かして高速論理回路
の構成の試みが行われているが、回路構成、集積
度、低消費電力、論理振幅等を考慮すると、Si
MOS FETと同様の化合物半導体MISFETの開
発が望まれている。最近GaAsよりMIS特性の良
好なInPを用いてMISFETが形成されている。こ
こでゲート絶縁膜としてSiO2，Al2O3あるいは陽
極酸化膜等が用いられているが、界面にネイテイ
ブオキサイドが存在すること、界面の異常層の存
在等により、Si−SiO2界面のような良好な特性
を有するものは得られておらず、MIS型ダイオー
ドの容量−電圧特性にヒステリシスや周波数分散
が認められ、またMISFETが電流ドリフトを呈
し、いまだ問題が多い。 Compound semiconductors such as GaAs and InP have higher electron mobility and saturation speed than Si, making them suitable for high-speed devices.
Semiconductor FET) has been put into practical use. In recent years, attempts have been made to construct high-speed logic circuits by taking advantage of the high-speed properties of these materials, but considering the circuit configuration, degree of integration, low power consumption, logic amplitude, etc., Si
The development of compound semiconductor MISFETs similar to MOS FETs is desired. Recently, MISFETs have been formed using InP, which has better MIS characteristics than GaAs. Here, SiO 2 , Al 2 O 3 or an anodic oxide film is used as the gate insulating film, but due to the presence of native oxide at the interface, the presence of an abnormal layer at the interface , etc. However, there are still many problems such as hysteresis and frequency dispersion in the capacitance-voltage characteristics of MIS type diodes, and current drift in MISFETs.
本発明は、このような低質な化合物半導体の
MIS特性を改善するために成されたものであり、
良好な界面特性を有する新しい構造のMIS型半導
体装置を提供するものである。 The present invention aims to improve the quality of such low-quality compound semiconductors.
This was done to improve MIS characteristics,
The present invention provides a MIS type semiconductor device with a new structure having good interface characteristics.
本発明のMIS型半導体装置は、Siより電子親和
力の大きい化合物半導体能動層と、酸化物あるい
は窒化物の絶縁膜との間に、５原子層を越える厚
さの、固有の半導体層としての特性を有するSi薄
膜が設けられ、該絶縁膜上に金属電極が形成され
ていることを特徴とする。 The MIS type semiconductor device of the present invention has unique characteristics as a semiconductor layer with a thickness of more than 5 atomic layers between a compound semiconductor active layer having a higher electron affinity than Si and an oxide or nitride insulating film. The invention is characterized in that a Si thin film having the following characteristics is provided, and a metal electrode is formed on the insulating film.
この酸化物や窒化物としてはSiO2、Si3N4等の
酸化Siや窒化Siを用いることができる。他には
Al2O3やTa2O5等の絶縁膜を用いることができ
る。上記Siの薄膜を化合物半導体と絶縁膜との間
に界在させることによつて、良好なSiと化合物半
導体の界面および良好なSiとSiO2の界面を形成
することにより、総合的に良好なMIS特性を実現
しうるものである。 As this oxide or nitride, Si oxide or Si nitride such as SiO 2 or Si 3 N 4 can be used. Other than that
An insulating film such as Al 2 O 3 or Ta 2 O 5 can be used. By interfacing the above-mentioned Si thin film between the compound semiconductor and the insulating film, a good Si-compound semiconductor interface and a good Si-SiO 2 interface are formed, resulting in an overall good It is possible to realize MIS characteristics.
以下本発明の実施例について説明し、本発明の
効果について詳述する。 Examples of the present invention will be described below, and the effects of the present invention will be explained in detail.
第１図は本発明の一実施例であるエンハンスメ
ント型InP MISFETの断面構造を示すものであ
る。半絶縁性InP基板１１上およびその上に形成
されたソースのn+領域１２とドレインのn+領域
１３上に100Åの厚さの高純度Si膜１４がエピタ
キシヤル成長され、さらにこの上に1000Åの厚さ
のSiO2膜１５が設けられている。該SiO2膜上に
Alのゲート電極１６が形成される。また１７，
１８はそれぞれソースおよびドレイン電極であ
る。ここでゲートの垂直方向Ａ−A′に沿つた部
分のエネルギーバンド状態図は第２図のようであ
る。Siの電子親和力はInPよりも約0.5eV小さい
のでSiとInPの界面で伝導帯にエネルギーの段差
が生じる。第２図ａの熱平衡状態においてはInP
表面に電子はほとんど誘起されないが、第２図ｂ
のようにゲート電極に正電圧を印加すると、InP
の表面電位は、Siとの界面のInP表面に電子２１
が誘起される。一方界面において、Siの伝導帯は
InPより約0.5eV大きく、かつSi膜は極めて薄い
のでSiO2との界面のSi側に誘起される電子は極
めて少い。 FIG. 1 shows a cross-sectional structure of an enhancement type InP MISFET which is an embodiment of the present invention. A high purity Si film 14 with a thickness of 100 Å is epitaxially grown on the semi-insulating InP substrate 11 and on the source n + region 12 and drain n + region 13 formed thereon, and a 1000 Å thick Si film 14 is further grown on this. A SiO 2 film 15 having a thickness of . on the SiO2 film
A gate electrode 16 of Al is formed. Also 17,
18 are source and drain electrodes, respectively. Here, the energy band phase diagram of the portion along the vertical direction A-A' of the gate is as shown in FIG. Since the electron affinity of Si is approximately 0.5 eV smaller than that of InP, an energy step occurs in the conduction band at the interface between Si and InP. In the thermal equilibrium state shown in Figure 2a, InP
Although almost no electrons are induced on the surface, Fig. 2b
When a positive voltage is applied to the gate electrode as in
The surface potential of is 21 electrons on the InP surface at the interface with Si.
is induced. On the other hand, at the interface, the conduction band of Si is
Since it is about 0.5 eV larger than InP and the Si film is extremely thin, there are extremely few electrons induced on the Si side of the interface with SiO 2 .
したがつて、FETのチヤンネル伝導に寄与す
る電子はSiとの界面のInP側を走行する。ここは
半導体のヘテロ接合であり、絶縁物とInPとの界
面より良好であるので、表面による移動度の低下
は小さい。ここでSiO2とSiの界面の準位密度が
大きいと、InP表面に誘起される実効的な電子の
数は減少するが、Si／SiO2界面は良好であるの
で、その影響は小さい。したがつて総合的に本発
明のMIS構造は、InP上に直接絶縁膜を形成した
従来のMIS構造よりはるかに界面特性は良好であ
る。SiとInPは格子不整の大きいこと、およびSi
のほうがエネルギーギヤツプが小さくSi中の伝導
度を小さくすることのために、Si膜を薄くする必
要があり、200Å以下が良好な結果を与える。た
だし、Si膜が固有の半導体層としての特性を有
し、明解なSi／InPおよびSi／SiO2界面を形成す
るためには、Siは数原子層例えば５原子層以上の
厚さが必要である。 Therefore, electrons contributing to channel conduction in the FET travel on the InP side of the interface with Si. This is a semiconductor heterojunction and is better than the interface between an insulator and InP, so the decrease in mobility due to the surface is small. Here, if the level density at the interface between SiO 2 and Si is large, the effective number of electrons induced on the InP surface will decrease, but since the Si/SiO 2 interface is good, this effect is small. Therefore, overall, the MIS structure of the present invention has much better interface characteristics than the conventional MIS structure in which an insulating film is directly formed on InP. Si and InP have a large lattice mismatch, and Si
In order to reduce the energy gap and the conductivity in Si, it is necessary to make the Si film thinner, and a thickness of 200 Å or less gives good results. However, in order for the Si film to have unique properties as a semiconductor layer and to form clear Si/InP and Si/SiO 2 interfaces, the thickness of Si must be several atomic layers, for example, 5 atomic layers or more. be.
本発明の第２の実施例では、第１の実施例にお
ける高純度Si膜に代えて、ｎ型にドープしたSi膜
を用いる。 In the second embodiment of the present invention, an n-type doped Si film is used in place of the high purity Si film in the first embodiment.
この場合、第２図ａに対応する熱平衡状態にお
けるエネルギーバンド状態図は第３図のようにな
る。すなわちｎ型Siの薄膜はすべて空乏化し、そ
の電荷量に見合う電子がInP表面に誘起され、す
なわち、ノーマリオン型のFETが形成できる。 In this case, the energy band phase diagram in the thermal equilibrium state corresponding to FIG. 2a is as shown in FIG. 3. That is, the n-type Si thin film is completely depleted, and electrons corresponding to the amount of charge are induced on the InP surface, thereby forming a normally-on type FET.
本発明の第３の実施例では、Si膜は蒸着等で形
成した非晶質Siを用いる。本実施例においては、
SiとInP界面は厳密には良好はヘテロ接合でな
く、またInP表面にネイテイブオキサイドが存在
する。しかしながら、本装置を300℃において30
分間水素中で熱処理すれば、界面のネイテイブオ
キサイドはSi中に取り込まれ、良好な界面が形成
された。 In the third embodiment of the present invention, amorphous Si formed by vapor deposition or the like is used as the Si film. In this example,
Strictly speaking, the interface between Si and InP is not a good heterojunction, and native oxide exists on the InP surface. However, this device was
After heat treatment in hydrogen for a minute, the native oxide at the interface was incorporated into the Si, forming a good interface.
なお、Si膜として、その他のプラズマCVD等
による多結晶Siが使用でき、またSiO2膜はCVD
法、あるいはスパツタ法等により形成できる。さ
らに厚いSi膜を途中まで酸化してやればより良好
なSiO2／Si界面が形成されるが、InPの耐熱性が
低いので、該酸化はプラズマ酸化等による低温プ
ロセスが望ましい。 Note that polycrystalline Si produced by other plasma CVD methods can be used as the Si film, and SiO 2 films can be produced by CVD.
It can be formed by a sputtering method or a sputtering method. If a thicker Si film is further oxidized halfway, a better SiO 2 /Si interface will be formed, but since the heat resistance of InP is low, a low-temperature process such as plasma oxidation is preferable for the oxidation.
以上InPを用いたMIS型半導体装置について説
明したが、本発明は、Siより電子親和力の大きい
GaAs，InAs等他の化合物半導体およびそれらの
混晶を用いた場合にも適用できる。 Although the MIS type semiconductor device using InP has been described above, the present invention is based on InP, which has a higher electron affinity than Si.
It can also be applied to cases where other compound semiconductors such as GaAs and InAs and their mixed crystals are used.
本発明のMIS型化合物半導体装置では、化合物
半導体と絶縁膜との間にSiの薄膜を有することに
より、良好な界面特性が得られ、MIS型半導体装
置の特性を改善できる。 In the MIS type compound semiconductor device of the present invention, by having a thin Si film between the compound semiconductor and the insulating film, good interface characteristics can be obtained, and the characteristics of the MIS type semiconductor device can be improved.
第１図は本発明の一実施例であるエンハンスメ
ント型MISFETの断面構造を示す図である。第
２図は第１図中Ａ−A′線に沿うエネルギーバン
ド状態図で、ａは熱平衡状態、ｂはゲートに正電
圧を加えた場合を示す。第３図は第２の実施例の
場合の熱平衡状態でのエネルギーバンド状態図で
ある。
１１……半絶縁性基板、１２……ソースのn+
領域、１３……ドレインのn+領域、１４……Si
膜、１５……SiO2膜、１６……ゲート電極、１
７……ソース電極、１８……ドレイン電極、２１
……電子、EC……伝導帯、EV……価電子帯、EF
……フエルミレベル。
FIG. 1 is a diagram showing a cross-sectional structure of an enhancement type MISFET that is an embodiment of the present invention. FIG. 2 is an energy band state diagram along the line A-A' in FIG. 1, where a shows the state of thermal equilibrium and b shows the case where a positive voltage is applied to the gate. FIG. 3 is an energy band phase diagram in a thermal equilibrium state in the case of the second embodiment. 11... Semi-insulating substrate, 12... Source n +
Region, 13...Drain n + region, 14...Si
Film, 15... SiO 2 film, 16... Gate electrode, 1
7... Source electrode, 18... Drain electrode, 21
...Electron, E C ...Conduction band, E V ...Valence band, E F
...Fermi level.
Claims (1)
層と、酸化物あるいは窒化物の絶縁膜との間に、
５原子層を越える厚さの、固有の半導体層として
の特性を有するSi薄膜が設けられ、該絶縁膜上に
金属電極が形成されていることを特徴とするMIS
型半導体装置。1. Between the compound semiconductor active layer, which has a higher electron affinity than Si, and the oxide or nitride insulating film,
A MIS characterized in that a Si thin film having a thickness of more than 5 atomic layers and having unique characteristics as a semiconductor layer is provided, and a metal electrode is formed on the insulating film.
type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20126981A JPS58102561A (en) | 1981-12-14 | 1981-12-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20126981A JPS58102561A (en) | 1981-12-14 | 1981-12-14 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58102561A JPS58102561A (en) | 1983-06-18 |
| JPH0544194B2 true JPH0544194B2 (en) | 1993-07-05 |
Family
ID=16438148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20126981A Granted JPS58102561A (en) | 1981-12-14 | 1981-12-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58102561A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58188165A (en) * | 1982-04-28 | 1983-11-02 | Nec Corp | Semiconductor device |
| JPS63237475A (en) * | 1987-03-25 | 1988-10-03 | Seiko Instr & Electronics Ltd | Manufacture of mos type field effect transistor |
| JPS63274176A (en) * | 1987-05-06 | 1988-11-11 | Seiko Instr & Electronics Ltd | Insulated-gate field-effect transistor |
| JP2735718B2 (en) * | 1991-10-29 | 1998-04-02 | 三菱電機株式会社 | Compound semiconductor device and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0328055A (en) * | 1989-06-26 | 1991-02-06 | Nissan Motor Co Ltd | Wind shield wiper accommodating device for car |
-
1981
- 1981-12-14 JP JP20126981A patent/JPS58102561A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0328055A (en) * | 1989-06-26 | 1991-02-06 | Nissan Motor Co Ltd | Wind shield wiper accommodating device for car |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58102561A (en) | 1983-06-18 |
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