JPS63237475A - Manufacture of mos type field effect transistor - Google Patents
Manufacture of mos type field effect transistorInfo
- Publication number
- JPS63237475A JPS63237475A JP7101987A JP7101987A JPS63237475A JP S63237475 A JPS63237475 A JP S63237475A JP 7101987 A JP7101987 A JP 7101987A JP 7101987 A JP7101987 A JP 7101987A JP S63237475 A JPS63237475 A JP S63237475A
- Authority
- JP
- Japan
- Prior art keywords
- single crystal
- film
- field effect
- effect transistor
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000013078 crystal Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 19
- 150000001875 compounds Chemical class 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 239000010408 film Substances 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、化合物半導体のＭＯＳ型電界効果トランジス
タの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a compound semiconductor MOS field effect transistor.
本発明は、化合物半導体のＭＯＳ型電界効果トランジス
タを作製する際に、化合物半導体基板もしくはＳｉ単結
晶基板上の化合物半導体膜上にＳｉ単結晶Ｉ？ｌ！Ｉｇ
を形成し、次に酸化により該Ｓｉ薄膜を５ｉＱ２膜とす
る。このとき５ｉ０２膜厚はＳｉ薄膜の１９み以下どし
化合物半導体と５ｉＱ２膜の間にＳｉ￥１結晶薄膜が残
るようにする。次に前記酸化膜をゲート絶縁膜として用
いたＭＯＳ型電界効果トランジスタを作製するものであ
り、化合物半導体と５ｉＱ２膜間の界面準位をおさえて
、動作範囲を大きくすることができるようにしたもので
ある。In the present invention, when manufacturing a compound semiconductor MOS field effect transistor, Si single crystal I? l! Ig
is formed, and then the Si thin film is made into a 5iQ2 film by oxidation. At this time, the thickness of the 5i02 film is set to be 19 or less than that of the Si thin film so that the Si\1 crystal thin film remains between the compound semiconductor and the 5iQ2 film. Next, a MOS field effect transistor using the oxide film as a gate insulating film is fabricated, and the interface state between the compound semiconductor and the 5iQ2 film is suppressed to increase the operating range. It is.
（従来の技術）
従来、化合物半導体のＭＯＳ型電界効果トランジスタは
、化合物半導体上に表面準位の少ない酸化膜を形成でき
なかったので実現しえなかった。(Prior Art) Conventionally, a compound semiconductor MOS field effect transistor could not be realized because an oxide film with few surface states could not be formed on a compound semiconductor.
よって化合物゛￥尋体の電界効果トランジスタは、ショ
ットキ・バリア（ｍｅｔａｌ−３ｅｍｉＣＯｎｄｕＣｔ
Ｏｎ：ＨＥＳ）型や、ペテロ接合型などが実用化されて
いる。第２図は、ＧａＡｓを用いたＭＥＳ型電界効果ト
ランジスタの素子断面図である。ＨＥＳ型では、能動領
域層４を流れるチャネル電流をゲート電極１０に印加す
る電圧による空乏層の広がりによって制′御する。Therefore, the field effect transistor of the compound ゛
On:HES) type, Peter junction type, etc. have been put into practical use. FIG. 2 is a cross-sectional view of an MES field effect transistor using GaAs. In the HES type, the channel current flowing through the active region layer 4 is controlled by the expansion of the depletion layer due to the voltage applied to the gate electrode 10.
本発明は、表面準位の少ない化合物￥導体ＭＯＳ型電界
効果トランジスタを作製することを目的としている。An object of the present invention is to fabricate a compound conductor MOS type field effect transistor with a small number of surface states.
前記の問題点を解決するために、本発明では、化合物半
導体と５ｉ０２膜の間に、Ｓｉ単結晶膜を入れている。In order to solve the above problems, in the present invention, a Si single crystal film is inserted between the compound semiconductor and the 5i02 film.
本発明のようにして形成されたＭＯＳ型電界効果トラン
ジスタは、化合物半導体とＳｉ単結晶膜の界面に表面準
位が少ないので、良好なトランジスタを作製することが
できる。Since the MOS field effect transistor formed according to the present invention has few surface states at the interface between the compound semiconductor and the Si single crystal film, a good transistor can be manufactured.
以下に本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.
化合物半導体には、ＧａＡｓ、 ＩｎＰ 、 ＩｎＡｓ
、 ＩｎＳｂなどがあるが、ここではＧａＡｓについて
、Ｓｉ単結晶薄膜の成長方法には、ＭＢＥ法、ＣＶＯ法
、ＬＰＣＶＤ法、光ＣＶＤ法などがあるが、この場合Ｍ
ＢＥ法について説明する。またＳｉの酸化方法にも熱酸
化法や高圧酸化法などがあるが、この場合高圧酸化法に
よるものとする。以下ｎチャネル・ｎヂ１ノネルトラン
ジスタのうちｎチャネルの場合について説明する。Compound semiconductors include GaAs, InP, and InAs.
, InSb, etc., but for GaAs, methods for growing Si single crystal thin films include the MBE method, CVO method, LPCVD method, and photo-CVD method.
The BE method will be explained. There are also thermal oxidation methods and high-pressure oxidation methods for oxidizing Si, and in this case, the high-pressure oxidation method is used. The case of an n-channel transistor among n-channel/nji1 nonel transistors will be described below.
実施例１］
第１図はＧａＡｓＭ ＯＳ型電界効果トランジスタを半
絶縁性ＧａＡｓ単結晶基板１上に作製する工程を示して
いる。イオン注入によりｎ能動層４ｎ＋ソース領域２と
ｎ＋ドレイン領域３を形成した半絶縁性ＧａＡｓ塁板上
転板上単結晶膜５を形成する（第１図（ａ））、次に高
１３−酸化法により４００〜６００℃の比較的低温でＳ
ｉ単結晶膜を酸化する。このとき第１図（ｂ）のように
５ｉＱ２膜６がＧａＡｓ基板表面には達しないようにす
る。次にゲート絶縁膜部７を残してＳｉ、 ５ｉ０２を
除去し、ソース電極８．ドレイン電極９．ゲート電極′
１０を形成する（第１図（Ｃ））。Example 1] FIG. 1 shows a process of manufacturing a GaAsM OS type field effect transistor on a semi-insulating GaAs single crystal substrate 1. A single crystal film 5 is formed on the semi-insulating GaAs base plate and the transfer plate on which the n active layer 4n+ source region 2 and n+ drain region 3 are formed by ion implantation (FIG. 1(a)), and then the high 13-oxidation S at a relatively low temperature of 400 to 600℃ by the method
i Oxidize the single crystal film. At this time, as shown in FIG. 1(b), the 5iQ2 film 6 is prevented from reaching the surface of the GaAs substrate. Next, the Si layer 5i02 is removed leaving the gate insulating film portion 7, and the source electrode 8. Drain electrode9. Gate electrode′
10 (FIG. 1(C)).
実施例２］第３図はＧａＡｓＭ ＯＳ型電界効果トラン
ジスタをＳｉ単結晶基板上に形成されたＧａＡｓ単結晶
膜上に作製する工程を示している。５ｉＱｉ結晶基板１
１上にＶ（バナジウム）やＣｒなどをドーピングした半
絶縁性ＧａＡｓ単結晶膜１２を成良し、次にノン・ドー
プＧａＡｓ単結晶膜１３を成長する（第３図（ａ））。Embodiment 2] FIG. 3 shows the process of manufacturing a GaAsM OS type field effect transistor on a GaAs single crystal film formed on a Si single crystal substrate. 5iQi crystal substrate 1
A semi-insulating GaAs single crystal film 12 doped with V (vanadium), Cr, etc. is grown on the semiconductor substrate 1, and then a non-doped GaAs single crystal film 13 is grown (FIG. 3(a)).
次に実施例１と同様にしてＭＯＳ型電界効果トランジス
タを構成する（第３図（ｂ））。Next, a MOS field effect transistor is constructed in the same manner as in Example 1 (FIG. 3(b)).
実施例３］５１ＭＯＳ型電界効果トランジスタ・バイポ
ーラトランジスタが形成されたＳｉ単結晶基板上に実施
例２を施こし、ＳｉデバイスとＧａＡｓＭ Ｏ８型電界
効果トランジスタを混載する。Example 3] Example 2 is carried out on a Si single crystal substrate on which a 51 MOS type field effect transistor/bipolar transistor is formed, and a Si device and a GaAsM O8 type field effect transistor are mounted together.
〔発明の効果］
本発明は、化合物半導体との表面準位が少ない３ｉｔｉ
結晶膜を用いているので、従来実現し得ながったＭＯＳ
型電界効果トランジスタを作製することができる。これ
により従来ＨＥＳ型では小さがった動作範囲を大きくす
ることができた。[Effects of the Invention] The present invention provides 3iti
Since it uses a crystal film, it is possible to create a MOS that could not be realized before.
type field effect transistor can be fabricated. This made it possible to increase the operating range, which was previously small in the HES type.
第１図（ａ） 〜（Ｃ）と第３図（ａ） 、 （ｂ）
Ｇｅｔ本発明の実施例の工程を説明するための断面図、
第２図は従来技術であるＧａＡｓＭ Ｅ Ｓ型電界効果
トランジスタの断面図である。
１・・・半絶縁性ＧａＡｓ単結晶基板
５・・・Ｓｉ単結晶薄膜
７・・・ゲート絶縁膜
１１・・・Ｓｉ単結晶基板
１２・・・半絶縁性ＧａＡｓ単結晶膜
１３・・・ノン・ドープＧａＡｓ単結晶膜（他１名）Figures 1 (a) to (C) and Figures 3 (a) and (b)
GetCross-sectional diagram for explaining the process of the embodiment of the present invention,
FIG. 2 is a cross-sectional view of a conventional GaAsM E S type field effect transistor. 1...Semi-insulating GaAs single crystal substrate 5...Si single crystal thin film 7...Gate insulating film 11...Si single crystal substrate 12...Semi-insulating GaAs single crystal film 13...Non・Doped GaAs single crystal film (1 other person)
Claims (5)
１工程と、このＳｉ単結晶薄膜を酸化してゲート絶縁膜
とする第２工程を含むことを特徴とするＭＯＳ型電界効
果トランジスタの製造方法。(1) Manufacturing a MOS field effect transistor characterized by including a first step of forming a Si single crystal thin film on a compound semiconductor substrate and a second step of oxidizing the Si single crystal thin film to form a gate insulating film. Method.
Ｓｉ単結晶薄膜よりも薄い特許請求の範囲第１項記載の
ＭＯＳ型電界効果トランジスタの製造方法。(2) The method for manufacturing a MOS field effect transistor according to claim 1, wherein the oxidized gate insulating film in the second step is thinner than the Si single crystal thin film.
である特許請求の範囲第１項記載のＭＯＳ型電界効果ト
ランジスタの製造方法。(3) The method for manufacturing a MOS field effect transistor according to claim 1, wherein the compound semiconductor substrate is a semi-insulating GaAs single crystal substrate.
体膜を設けた基板である特許請求の範囲１項記載のＭＯ
Ｓ型電界効果トランジスタの製造方法。(4) The MO according to claim 1, wherein the compound semiconductor substrate is a substrate formed by providing a compound semiconductor film on a Si single crystal substrate.
A method for manufacturing an S-type field effect transistor.
膜とから構成される特許請求の範囲第４項記載のＭＯＳ
型電界効果トランジスタの製造方法。(5) The MOS according to claim 4, wherein the compound semiconductor film is composed of a semi-insulating film and a non-doped film.
Method of manufacturing type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7101987A JPS63237475A (en) | 1987-03-25 | 1987-03-25 | Manufacture of mos type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7101987A JPS63237475A (en) | 1987-03-25 | 1987-03-25 | Manufacture of mos type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63237475A true JPS63237475A (en) | 1988-10-03 |
Family
ID=13448387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7101987A Pending JPS63237475A (en) | 1987-03-25 | 1987-03-25 | Manufacture of mos type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63237475A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58102561A (en) * | 1981-12-14 | 1983-06-18 | Nec Corp | Semiconductor device |
| JPS59231865A (en) * | 1983-06-14 | 1984-12-26 | Seiko Epson Corp | Semiconductor device |
-
1987
- 1987-03-25 JP JP7101987A patent/JPS63237475A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58102561A (en) * | 1981-12-14 | 1983-06-18 | Nec Corp | Semiconductor device |
| JPS59231865A (en) * | 1983-06-14 | 1984-12-26 | Seiko Epson Corp | Semiconductor device |
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