JPS606104B2 - MIS semiconductor device - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a skin S semiconductor device, and particularly to an MIS semiconductor device such as a high voltage MS transistor, a high voltage MISIC, and a high voltage CM ISIC. Conventionally, high-voltage MIS semiconductor devices have an offset gate structure, a stacked gate structure, and a drain layer with a high impurity concentration surrounded by a diffusion layer with a lower impurity concentration (a diffusion layer of the same conductivity type as the drain layer). There are various structures such as a double diffusion type drain layer structure. However, although the plate S semiconductor devices of the various structures described above have a high breakdown voltage, the manufacturing process is complicated due to their structure and has the drawback that the work steps are large. Moreover, in the high-voltage S semiconductor device having the above-described structure, in order to satisfy high-performance characteristics such as higher speed and lower power consumption, the threshold voltage of the element is lowered and the semiconductor substrate is lowered to reduce the value voltage Vth. When using a material with impurity concentration, it is necessary to provide a channel stopper to prevent parasitic MOS transistors under the field insulating film and to prevent the channel, which increases the number of man-hours, reduces manufacturing yield, and increases manufacturing costs. The disadvantage was that it was expensive. Therefore, an object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a high-voltage MIS semiconductor device that is easy to manufacture, has high performance, and has a simple structure. In order to achieve this purpose, in a preferred embodiment of the high-voltage S semiconductor device according to the present invention, an oxide film thicker than the gate insulating film is provided on the substrate surface at an intermediate position of the drain layer. It is characterized in that a layer having the same conductivity type as the drain layer and having a lower impurity concentration than the drain layer is provided below. Hereinafter, the present invention will be specifically explained using examples. FIG. 1 to FIG. 6 show LOCO, which is an embodiment of the present invention.
1A and 1B are cross-sectional views illustrating an S-structure high voltage MOSIC and a method for manufacturing the same in order of steps. The high breakdown voltage MOSIC and the manufacturing method thereof according to the present invention will be explained in detail in the order of steps using the same figure.

[A] Silicon nitride (Si
3N4) Form film 2 (FIG. 1). {o} Si3N4 in the area where the field oxide film will be formed
Etch-off the Si3N4 film 2 at an intermediate position between the film 2 and the drain layer in the region where the drain layer is to be formed (Fig. 2).
A donor impurity such as phosphorus (P) is ion-implanted through the window in the region where the drain layer is to be formed (FIG. 3). After removing photoresistor 3, place it in humid oxygen.
Selective oxidation silicon (Si) oxidizes at high temperatures and has a LOCOS structure.
02) Form a film 585a (Figure 1). At this time, "Si
No silicon oxide (Si02) film is formed due to the masking effect of the 3N4 film 2 on oxygen. After removing the O 2 Si3N4 film 2, a clean gate oxide film 6 is grown.
Subsequently, a polycrystalline silicon layer 7 is formed on the upper surface of the substrate 1, and portions other than the gate electrode are etched off by photoetching.
This remaining polycrystalline silicon layer? The gate oxide film 7 corresponding to the source and drain regions is removed by etching again using the . (Fig. 6) In order to insulate the polycrystalline silicon layer 7 for the gate electrode G, etc., a silicon oxide (Si02) film 10 is grown on the upper surface of the T-substrate 1 by thermal decomposition of silane (Fig. 7). ). After opening the N contact window, vacuum evaporate aluminum (mountain) and photo-etch to form the necessary aluminum acid wire, electrode S, and drain electrode D (Figure 7). Drain electrode D is LOCO
It is assumed that it is provided on the N0 type drain layer 8 facing the gate electrode G for the thick Si02 film of the S structure. (G) This concludes the wafer processing process, and the device is completed by cutting it into chips as usual and then going through the assembly process. High breakdown voltage M of LOCOS structure applied to
OSIC has the following features. {1} As shown in FIG. 7, the MOS transistor incorporated in the MOSIC according to the present invention Underneath this selective oxide film 6a, there is an N-type diffusion layer 4 (ion-implanted) which is connected to the positive type drain layer 8 and has a lower impurity concentration than this selective oxide film 5a. formed by law)
Moreover, since the ohmic contact electrode of this drain layer 8, that is, the drain electrode D is provided on the drain layer 8 in a region facing the gate electrode G with respect to the selective oxide film 5a. , the N-type diffusion layer 4' acts as a resistor in the drain layer 8. That is, the MOS transistor according to the present invention acts as a resistor in the drain layer 8.
The circuit diagram of the transistor is as shown in FIG. 8, and the above-mentioned N-type diffusion layer 4 acts as a saturation type resistor similarly to the conventional high-voltage MOS transistor with an offset gate structure. At point F shown in ``drain electrode D'
The applied drain voltage is N as this resistor.
This will keep the pinch-off voltage Vp of the type diffusion layer 4 or lower. Therefore, the breakdown voltage of the drain layer 8 can be set to be higher than the surface breakdown voltage of the PN circular junction between the N-type drain layer 8 and the substrate 1, and the breakdown voltage of the drain layer 8 can be set to be higher than the surface breakdown voltage of the PN circular junction between the N-type drain layer 8 and the substrate 1. It is possible to increase the internal breakdown voltage of the junction.Therefore, the M according to the present invention
The withstand voltage of the OS transistor can be made as high as possible, so that the MOS transistor according to the present invention, that is, the MOSIC incorporating these elements has a very high withstand voltage. Even though it has a simple structure as shown in Figure 1, its manufacturing method and manufacturing process are extremely easy as described above. To,
The method and process for manufacturing a high voltage MOSIC according to the present invention can be carried out by utilizing the manufacturing process for manufacturing a conventional LOOOS structure MOSIC. Therefore, high-voltage MOS can be manufactured with extremely few man-hours.
ICs can be obtained, and high manufacturing yields and low manufacturing costs can be achieved. [31] The present invention is not limited to the above-mentioned embodiments, but is applicable to “P-channel MOS”.
It can be applied to E/DMOSICC MOS ICs, day-screte MOS transistors, and semiconductor devices using various types of gate electrodes and gate insulating films. Further, in the present invention, the manufacturing process of the channel stopper for preventing parasitic MOS transistors and channels is the same as the manufacturing process of the diffusion layer (resistor) under the thick selective oxide film in the drain layer, which is a component of the present invention. Since they can be formed in combination, there is no need to increase the number of man-hours. Furthermore, ``the present invention essentially has a structure in which the threshold value voltage Vth of the semiconductor substrate surface in the field region can be determined irrespective of the setting of the threshold value voltage Vth of the element active region. Therefore, the MIS semiconductor device according to the present invention is easy to manufacture and has high performance (no parasitic effects, high speed operation, low consumption). It is a high-voltage device with a simple structure and high reliability (no malfunctions when using electricity).

[BRIEF DESCRIPTION OF THE DRAWINGS] Figures 1 to 7 are cross-sectional views showing the LOCOS structure high voltage MOSIC according to the present invention and its manufacturing method in order of process. It is a diagram showing a circuit diagram of a high voltage MOS transistor. 1... P-type silicon substrate, 2... Si3N4 film, 3... photoresistor, 4... phosphorus (P) impurity layer or N-type diffusion layer, 5, 5a... selective oxidation. Film, 6... Gate oxide film, 7... Polycrystalline silicon layer or gate electrode G, 8... N+ type drain layer, 9... N+ type source layer, 1
0...Si02 film, D...drain electrode, S...source electrode.
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, a gate electrode provided through a thin gate insulating film in a region on the main surface of the semiconductor substrate where a channel is to be formed, and a phase in the region where the channel is to be formed. In the MIS semiconductor device, the MIS semiconductor device includes the semiconductor substrate formed to define opposing ends, and a pair of highly impurity concentration first semiconductor regions of opposite conductivity type, wherein one of the pair of first semiconductor regions and A second semiconductor region having a high impurity concentration is provided at a predetermined interval, and is thicker than the gate insulating film on the surface of the semiconductor substrate between one of the first semiconductor regions and the second semiconductor region. An oxide film is provided under the thick oxide film, and the impurity content is the same as that of the pair of semiconductor regions connecting one of the first semiconductor regions and the second semiconductor region and that is lower in impurity than the pair of semiconductor regions. A MIS semiconductor device characterized in that a concentration region is provided.