JPS5931224B2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device formed on an insulating substrate containing aluminum oxide as a main component.

There are many examples of manufacturing semiconductor devices such as transistors, diodes, and insulated gate field effect transistors by forming a semiconductor single crystal on an insulating substrate by an epitaxial growth method and using the semiconductor single crystal.

Here, an insulated gate field effect transistor will be explained as an example. Conventionally, an insulated gate field effect transistor has a source formed near the surface of a semiconductor substrate of a certain conductivity type with a channel region sandwiched therebetween. It consists of a gate formed through an insulating film, and the current flowing between the resource and the drain is controlled by the voltage applied between the gate and the substrate.

However, in the insulated gate field effect transistor having such a structure, the operating frequency cannot be increased because the PN junction capacitance between the drain and the semiconductor substrate is large. In order to reduce this PN junction capacitance between the drain and the substrate, a semiconductor single crystal layer (hereinafter referred to as the semiconductor layer) is formed by epitaxial growth on the insulating substrate, and the drain region is extended from the surface of the semiconductor layer to the insulating substrate to form an insulated gate. A type field effect transistor is formed. For example, in the P-channel insulated gate field effect transistor shown in FIG. 1, an N-type semiconductor layer 2 with a low impurity concentration is formed on an insulating substrate 1 such as a sapphire substrate made of aluminum oxide or a spinel substrate. It is obtained by forming a drain region 4 and a source region 5 with high impurity concentration extending to an insulating substrate, and then forming a gate insulating film 6, a gate electrode 7, a drain electrode 8, and a source electrode 9.

It is true that in this P-channel insulated gate field effect transistor, the PN junction area between the drain region 3 and the semiconductor layer 2 is significantly reduced, the load capacitance of the insulated gate field effect transistor is reduced, and the operating frequency can be increased. However, in this structure, the channel region 10 is N-type and has a low impurity concentration, and on the other hand, the sapphire substrate or spinel substrate used as the insulating substrate 1 is made of aluminum oxide, so it is subjected to high-temperature heat treatment, for example, forced diffusion at 1200°C for 1 hour or more. When these steps are carried out, aluminum is diffused from the insulating substrate 1 into the channel region 10.

Therefore, in many cases, aluminum is diffused into the region of the channel region 10 in contact with the insulating substrate 1, and a P-type region 11, which is the opposite conductivity type to the channel region 10, is formed. When a P-type inversion region 11 is formed near the insulating substrate 1 in the channel region 11, the drain region 4 and the source region 5
There is a drawback that conduction occurs between the source and drain, causing a large leakage current to flow between the source and drain. Incidentally, when a P-type semiconductor layer is formed on the insulating substrate 1 and an element is formed on this semiconductor layer, there are few problems because no inversion region is formed. The present invention aims to eliminate these drawbacks and provide a semiconductor device with low leakage current and good frequency characteristics.

That is, in the present invention, when a semiconductor single crystal is formed by an epitaxial growth method on an insulating substrate mainly composed of aluminum oxide, and a semiconductor device is formed using the semiconductor single crystal, the impurity concentration in a region exhibiting N-type conductivity is reduced. The present invention proposes a semiconductor device having a structure in which the maximum value is near the interface with the insulating substrate and decreases as the distance from the interface increases.According to the present invention, the N-type semiconductor layer and the insulating substrate By forming an N-type region with a sufficiently high impurity concentration near the interface, even if aluminum is diffused from the insulating substrate, the N-type impurity concentration can be made sufficiently higher than the aluminum concentration. A P-type inversion region does not occur in the N-type semiconductor layer near the insulating substrate, and therefore, the present invention provides a semiconductor device with low leakage current.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be described below in detail with reference to the drawings, using an example of a P-channel insulated gate field effect transistor and its manufacturing method.

As shown in FIG. 2A, the insulating substrate 1 such as a sapphire substrate or a spinel substrate exhibits N type conductivity, and the impurity concentration is, for example, 1014 to 1017c! n-3 and thickness 0.5-1
．． A 0μ semiconductor layer 2 is formed.

Next, as shown in FIG. 2B, the entire surface of the semiconductor layer 2 has a thickness of 0.5 to 1.5 mm, which is obtained by vapor phase growth or thermal oxidation.
A silicon oxide film 3 with a thickness of 0 μm is formed, and a window is opened in the silicon oxide film 3.

Next, as shown in FIG. 2C, a drain region 4 and a source region 5 of a conductivity type opposite to that of the semiconductor layer 2, that is, P type, are formed by thermal diffusion, ion implantation, or the like.

Next, as shown in FIG. 2D, the drain region 4 and the source region 5 are
Then, the silicon oxide film on the semiconductor layer 2 is removed and an impurity, for example, phosphorus ions, which gives N-type conductivity is added to both the source and drain regions.
An amount of 1015 cm-2 is implanted into the vicinity of the interface between the semiconductor layer 2 and the insulating substrate 1 by ion implantation, followed by heat treatment to form an N-type 1016-1021c! A high impurity concentration layer 13 of RL-3 is formed. When impurities are implanted by ion implantation, a photoresist film 12 is formed in areas where implantation is not required, and serves as a protective film against the ion implantation. Next, as shown in FIG. 2E, a gate insulating film 6 is formed of a silicon oxide film, a silicon nitride film, or the like.

Next, as shown in FIG. 2F, after opening a window in the silicon oxide film on the surface of each of the source region 4 and drain region 5, a gate electrode 7, a drain electrode 8, and a source electrode 9 are formed.

According to the thus obtained semiconductor device according to the present invention, that is, the P-channel insulated gate field effect transistor as in this example, a high impurity concentration is added near the interface between the semiconductor layer 2 and the insulating substrate 1 by ion implantation. Since an N-type region 13 is formed and there is almost no change in impurity concentration inside the semiconductor layer near the surface, even if aluminum is diffused from the insulating substrate 1 into the semiconductor layer 2, a P-type inversion region is formed. Therefore, a good field effect transistor having a desired threshold voltage can be obtained without causing any leakage current.

Another method of manufacturing the device of the present invention is to form a semiconductor layer 2 on an insulating substrate 1 by epitaxial growth as shown in FIG. 21 For example 1016-1018 cT
rL-3, then lower the impurity concentration to 1014-1
The structure is such that the low impurity concentration layer 22 is 017cTrL-3.

Next, as shown in FIG. 3B, a manufacturing method is adopted in which a drain head region 4, a source region 5, a gate insulating film 6, and each electrode 7, 8, 9 are formed to obtain a P-channel insulated gate transistor. obtain. In the manufacturing method explained in FIG. 2, the N-type high concentration layer 13 was formed across the source region 4 and the drain region 5, but as shown in FIG.
The same effect can be obtained by forming a heavily doped layer 13' in a part of the N-type region between the drain region 5 and the drain region 5.

As explained above, according to the present invention, since an N-type highly impurity region is formed in the semiconductor layer near the insulating substrate, a P-type inversion layer that increases leakage current and deteriorates characteristics is removed from the insulating substrate 1. A product with very good properties can be obtained without being formed by diffusion. In the above description, a P-channel insulated gate field-effect transistor has been described as an example, but the application is not limited to a P-channel insulated-gate field-effect transistor, but can also be applied to bipolar transistors and diodes, and can also be applied to one element of an integrated circuit. It's easy to understand what you can do.

[Brief explanation of drawings]

Figure 1 is a sectional view to explain the drawbacks of the conventional technology, Figure 2A
-F is a sectional view showing an example of the manufacturing method of this invention device, FIGS. 3A and B are sectional views showing another example of the manufacturing method of this invention device, and FIG. 4 is a sectional view showing another embodiment of this invention device. FIG. 1: Insulating substrate mainly composed of aluminum oxide, 2: N
type semiconductor substrate, 13, 13', 21: N type impurity concentration region.

Claims (1)

[Claims] 1. In a semiconductor device in which an N-type semiconductor layer is formed on an insulating substrate containing aluminum oxide, and a semiconductor element having a P-type region is formed in the N-type semiconductor layer, the P-type region reaches the insulating substrate. A highly concentrated N-type impurity region is formed in the N-type semiconductor layer which is surrounded by the N-type semiconductor layer on its side and is included in the semiconductor element near the interface between the N-type semiconductor layer and the insulating substrate. A semiconductor device characterized by: