JP2708525B2 - MOS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a MOS device characterized by being operated at a low temperature, especially at a liquid nitrogen temperature, and is more excellent in hot carrier resistance than conventional and capable of high-speed operation. Related to LDD structure MOS devices.

[Conventional technology]

Conventional MOS transistors have a high breakdown voltage structure
EEE, Journal of Solid State Circuits, SC15 (1980), 424-432
Page (IEEE J. of Solid-State Circuits, SC-15,424,198
Lightly Doped Drain structure as discussed in (0), LDD for short
There was a structure. In this structure, a low impurity concentration layer (LDD layer) is formed in a region of the source / drain diffusion layer which is in contact with the case electrode to reduce the electric field near the drain. The optimum value of the phosphorus ion implantation amount of the LDD layer at room temperature is described in 1984 IEDM Technical Digest, pages 774 to 777 (1984 IEDM, Tech.Dig.p.7).
As shown in 74), 10 ¹³ cm ^-2 , which is a value in the vicinity.

[Problems to be solved by the invention]

However, the above-mentioned LDD MOS transistor is not considered for low-temperature operation, and when it is operated at liquid nitrogen temperature, the resistance value of the low impurity concentration layer (LDD layer) increases due to the carrier freeze-out effect and the operating current value decreases. At the same time, there is a problem that the hot carrier deterioration inherent to the LDD structure MOS transistor is increased. Japanese Patent Application Laid-Open No. Sho 62-69559 discloses an example of increasing the speed of an LDD structure MOS by operating at a low temperature. The present invention has been made by further experiments.

An object of the present invention is to solve the above-described problem of performance degradation due to an increase in LDD resistance at a low temperature, and to enable a highly reliable operation of an LDD structure MOS transistor at a liquid nitrogen temperature.

[Means for solving the problem]

The above purpose is to adjust the phosphorus ion implantation amount of the LDD layer to 1.5 × 10 ¹³ cm.
Achieved by taking an amount not less than ^{-2 and not} more than 2.5 × 10 ¹⁴ cm ^-2 . More accurate optimization is achieved by setting the LDD layer phosphorous implant to a value at or near 10 ¹⁴ cm ⁻² .

[Action]

The operation of the present invention will be described using newly obtained experimental effects. FIG. 2 shows a DC stress experiment result of the LDD structure nMOS transistor. The drain voltage applied as DC stress is 5 V, and the gate voltage is set to a value that maximizes the substrate current. The vertical axis shows the rate of degradation of transconductance Gm in the unsaturated region after applying stress for 10,000 seconds, and the horizontal axis shows the amount of implanted phosphorus ions (cm
^-2 ). FIG. 2 shows the relationship between the Gm degradation rate due to hot carriers and the amount of phosphorus ions implanted in the LDD portion under both the temperature conditions of 0 ° C. (ice water) and 77K. At 0 ° C, close to room temperature,
In the same manner as in the results shown in 1984 IEDM Technical Digest, pp. 774 to 777, the amount of deterioration was minimized when the driving amount was 10 ¹³ cm ⁻² . However, at liquid nitrogen temperature, ion implantation amount 10 ¹³ cm ^-2
The conventional device has a large Gm degradation of about 10 ^-1 at a stress time of 10,000 seconds. This is because the LDD layer resistance increases due to the carrier freeze-out effect. On the other hand, if the ion implantation amount is 1.5 × 10 ¹³ or more and 2.5 × 10 ¹⁴ cm ^-2 or less, the above-mentioned carrier freeze-out effect can be weakened, and the liquid nitrogen temperature (77 K) can be lower than that of the conventional device. Deterioration rate can be reduced. In addition, the 77K deterioration rate at this time can be reduced to within 7 times the room temperature deterioration rate (about 10 ^-2 ), and industrial practicality is secured. 2.1 × 10 ¹⁴ c with ion implantation amount of 3 × 10 ¹³ or more
If the amount is not more than m ^{-2, the} reliability with industrial practical value of less than 5 times the room temperature deterioration rate is secured at 77K. further,
If the ion implantation amount is 5 × 10 ¹³ or more and 1.8 × 10 ¹⁴ cm ⁻² or less, the reliability of industrial practical value of not more than three times the room temperature deterioration rate is secured at 77K.

As an even more precise optimization, the ion implantation amount 10 ¹⁴
By setting the value to cm ⁻² or a value close to the value, the deterioration rate of Gm due to the hot carrier at 77 K can be suppressed to almost the same value as the room temperature value.

Even when the phosphorus ion implantation amount of the LDD layer is set to 10 ¹³ cm ^-2 or less, L
Although the effect of relaxing the electric field in the DD section is strong, the degradation rate at 77K can be reduced, but the operating current decreases, which increases the parasitic resistance.

FIG. 3 shows the measurement results of the parasitic resistance of the LDD structure nMOS transistor. As shown in the characteristic curve (a) of the parasitic resistance versus the gate voltage when the LDD layer has a phosphorus ion implantation amount of 0.4 × 10 ¹³ cm ^{−2 and} the characteristic curve (b) when the ion implantation amount is 10 ¹³ cm ^−2. ,
If the amount of implanted phosphorus ions is less than 10 ¹³ cm ^-2 , the parasitic resistance at 77K becomes conspicuous and increases. This increase in parasitic resistance causes a large decrease in operating current. As in the present invention, the LDD layer implantation amount is 1.5 × 10 ¹³ or more and 2.5 × 10 ¹⁴ or less, or 3 × 10 ¹³ or more and 2.1 × 10 ¹⁴ or less, or 5 × 10 ¹³ or more and 1.8 × 10 ¹³ or more. When the amount is 10 ¹⁴ or less, and the value is 10 ¹⁴ cm ^-2 or a value close to 10 ¹⁴ cm ^-2 , the parasitic resistance at 77K is almost the same as the conventional room temperature value as shown by the curves (c), (d) and (e). (Curve (f)). As described above, the present invention can significantly reduce the hot carrier degradation rate at 77K than before without increasing the parasitic resistance at 77K.

〔Example〕

Hereinafter, the present invention will be described with reference to examples. FIG. 1 shows a first embodiment according to the present invention. Figure 1 shows the LDD structure n
This is a channel MOS transistor, and the LDD layer phosphorus ion implantation amount is set to 10 ¹⁴ cm ⁻² . 1 is a p-type Si substrate, 6 is a SiO ₂ film,
Reference numeral 7 denotes a gate electrode made of polysilicon. Reference numerals 4 and 5 denote low-impurity-concentration drain and source (n ⁻ ) layers.
It is formed by implanting an amount of 10 ¹⁴ cm ^-2 below KeV. The junction depth (Xj) is 0.3 μm or less, and the surface impurity concentration is 10 μm.
¹⁸ to 10 ²⁰ cm ^-3 . Reference numeral 8 denotes a spacer oxide film formed on the side wall of the gate electrode.
ture-Low Pressure Deposition) method. After molding the spacer 8, the arsenic (As) ions
This is a high-concentration n-type region formed by ion implantation of ¹⁵ to 10 ¹⁶ cm ⁻² and serves as a drain and a source of the nMOS transistor.

The parasitic resistance at the liquid nitrogen temperature (77 K) measured in this embodiment is about 100 at a gate voltage of 5 V as shown in FIG.
Ω, the conventional device (LDD layer phosphorus ion implantation amount: 10 ¹³ c
m- ² ), which was almost equal to the room temperature parasitic resistance. According to the present embodiment, the Gm degradation rate at 77K can be reduced to 10 ^-2 in the off-word mode and 4 × 10 ^-2 in the reverse mode as shown in FIG. ² , and the hot carrier reliability at 77K can be reduced. Could be improved.

In the present embodiment, the LDD layer phosphorus ion implantation amount was set to 10 ¹⁴ cm ^-2 , but if the implantation amount is set to 1.5 × 10 ¹³ or more and 2.5 × 10 ¹⁴ cm ^-2 or less, the 77K deterioration rate becomes room temperature value. Industrial practicality can be ensured within 7 times of the above. 3 × 10 ¹³ or more and 2.1 × 10 ¹⁴ cm
^-2 or less and 1.8 × 10 ¹⁴ cm or more and 5 × 10 ¹³ or more and the amount of ^-2 or less.
Industrial practicability can be ensured with a value within a factor of three and a value within a factor of three.

 FIG. 4 shows a second embodiment of the present invention.

This embodiment is an example of the invention of an asymmetric low-concentration drain (LDD) type n-channel MOS transistor. This embodiment is different from the first embodiment in that the low impurity concentration source and the fifth embodiment of the first embodiment are used. In that an n-type impurity region 9 having a high impurity concentration is formed. The low concentration drain 4 is the first
In the same manner as in Example 1, phosphorus is implanted at 50 KeV or less in an amount of 10 ¹⁴ cm ^-2 . In this embodiment, since there is no low concentration diffusion layer formed adjacent to the source 3 in the first embodiment, the photocarrier breakdown voltage can be increased without lowering the effective gate voltage viewed from the external terminal. By optimizing the low-concentration drain concentration, the device deterioration at 77K can be reduced by about one digit as compared with the conventional device.

〔The invention's effect〕

In the present invention, the amount of phosphorus ions implanted in the low-concentration drain portion of the LDD MOS transistor is set to an amount of 1.5 × 10 ¹³ cm ⁻² or more and 2.5 × 10 ¹⁴ cm ⁻² or less, whereby the hot carrier deterioration rate at 77 K is reduced. It was able to be reduced from the device value.

Further, in the present invention, the phosphorus ion implantation amount was set to 10 ¹⁴ cm ^-2 or a value in the vicinity thereof, whereby the deterioration rate at 77K could be minimized, and the room temperature value and the conventional device could be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing the hot carrier reliability of the device of the present invention, FIG. 3 is a diagram showing the results of the parasitic resistance of the device of the present invention, and FIG. FIG. 6 is a diagram showing a second embodiment of the present invention. 1 ... p-type Si substrate, 2 ... drain, 3 ... source, 4 ... lightly doped drain, 5 ... low concentration source, 6 ... SiO ₂ film, 7 ... gate electrode, 8 ... spacer.

Claims (4)

(57) [Claims] At least one of a drain region and a source region has an impurity concentration lower than that of another drain / source region on a surface portion adjacent to a gate electrode.
An n-channel MOS transistor having a p-type impurity region, wherein the low-concentration n-type impurity region contains 1.5 × 10
A semiconductor device characterized by being formed by being implanted in an amount of ¹³ cm ^-2 or more and 2.5 × 10 ¹⁴ cm ^-2 or less, and operating the device at a temperature of liquid nitrogen or a temperature range near the temperature. A semiconductor device comprising: 2. The low-concentration n-type impurity region contains phosphorous ions of 3 ×
Claim 1 characterized by being formed by being driven in an amount of 10 ¹³ cm ^-2 or more and 2.1 × 10 ¹⁴ cm ^-2 or less.
13. The semiconductor device according to item 9. 3. The low-concentration n-type impurity region contains 5 × phosphorus ions.
Claim 1 characterized by being formed by being driven in an amount of not less than 10 ¹³ cm ^{-2 and not} more than 1.8 × 10 ¹⁴ cm ^-2 .
13. The semiconductor device according to item 9. 4. The low-concentration n-type impurity region contains 10 ¹⁴
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by being implanted by an amount of cm ^-2 or an amount in the vicinity thereof.