JPH02214123A - Mos-type semiconductor device - Google Patents
Mos-type semiconductor deviceInfo
- Publication number
- JPH02214123A JPH02214123A JP3357589A JP3357589A JPH02214123A JP H02214123 A JPH02214123 A JP H02214123A JP 3357589 A JP3357589 A JP 3357589A JP 3357589 A JP3357589 A JP 3357589A JP H02214123 A JPH02214123 A JP H02214123A
- Authority
- JP
- Japan
- Prior art keywords
- amount
- semiconductor device
- ldd
- type impurity
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 10
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 21
- 239000011574 phosphorus Substances 0.000 claims abstract description 21
- 239000012535 impurity Substances 0.000 claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 16
- -1 phosphorus ions Chemical class 0.000 claims abstract description 15
- 239000007788 liquid Substances 0.000 claims abstract description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 8
- 238000001816 cooling Methods 0.000 claims abstract 2
- 230000006866 deterioration Effects 0.000 abstract description 23
- 239000000969 carrier Substances 0.000 abstract description 4
- 238000002513 implantation Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000005457 ice water Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は低温、特に液体窒素温度で動作させることを特
徴とするＭＯＳデバイスに係り、従来よりもホットキャ
リア耐性に優れ、かつ高速動作が可能なＬＤＤ構造ＭＯ
Ｓデバイスに関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS device that is characterized by being operated at low temperatures, particularly at liquid nitrogen temperatures, and which has superior hot carrier resistance than conventional devices and is capable of high-speed operation. LDD structure MO
Regarding S devices.
Ｃ従来の技術〕 従来ＭｏＳトランジスタの高耐圧構造としては。C. Conventional technology] As for the high voltage structure of conventional MoS transistors.
アイ・イー・イー・イー、ジャーナル オブソリッドス
テートサーキツツ、ニス シー１５ （１９８０年）、
第４２４頁から４３２頁（ＩＥＥＥ Ｊ。I.E.E., Journal of Solid State Circuits, Nisshi 15 (1980),
pp. 424-432 (IEEE J.
ｏｆ ５ｏｌｉｄ−５ｔａｔｅ Ｃ１ｒｃｕｉｔｓ、Ｓ
Ｃ−１５，４２４。of 5olid-5tate C1rcuits,S
C-15,424.
１９８０）において論じられているようなライトリ−・
ドープト・ドレイン（ＬｉｇｈｔｌｙＤｏｐｅｄ Ｄｒ
ａｉｎ）構造、略してＬＤＤ構造があった０本構造はソ
ース・ドレイン拡散層のゲート電極に接する領域に低不
純物濃度層（ＬＤＤ層）を形成してドレイン近傍の電界
を緩和することにしたものである。そして、ＬＤＤ層の
燐イオン打込量の室温での最適値は、１９８４年アイ・
イー・デー・エム テクニカルダイジェスト、第７７４
頁から第７７７頁（１９８４Ｉ ＥＤＭ、 Ｔｅｃｈ、
Ｄｉｇ、 ｐ、 ７７４）において示されているよう
に、１０１δ（！−″！、もしくはその近傍の値である
。Lightly, as discussed in (1980)
LightlyDoped Dr
ain) structure, abbreviated as LDD structure, is one in which a low impurity concentration layer (LDD layer) is formed in the region of the source/drain diffusion layer in contact with the gate electrode to alleviate the electric field near the drain. It is. The optimal value for the amount of phosphorus ion implanted into the LDD layer at room temperature was determined by the 1984 I.
EDM Technical Digest, No. 774
Pages 777 (1984I EDM, Tech,
Dig, p, 774), it is 101δ (!-''!, or a value close to it).
しかし、上記ＬＤＤ構造ＭＯＳトランジスタは低温動作
について配慮されておらず、これを液体窒素温度で動作
させると低不純物濃度層（Ｌ Ｄ Ｄ層）の抵抗値がキ
ャリアフリーズアウト効果で増大し動作電流値が減少す
るとともに、ＬＤＤ構造ＭＯＳトランジスタに固有のホ
ットキャリア劣化が増大するとの問題があった。However, the LDD structure MOS transistor described above does not take into account low temperature operation, and when it is operated at liquid nitrogen temperature, the resistance value of the low impurity concentration layer (LDD layer) increases due to the carrier freeze-out effect, and the operating current value decreases. There is a problem in that as the amount of hot carriers decreases, hot carrier deterioration inherent to LDD structure MOS transistors increases.
本発明の目的は上記の低温でのＬＤＤ抵抗増大による性
能劣化の問題を解決し、ＬＤＤ構造ＭＯＳトランジスタ
の液体窒素温度での高信頼度動作を可能とすることにあ
る。An object of the present invention is to solve the problem of performance deterioration due to an increase in LDD resistance at low temperatures, and to enable highly reliable operation of an LDD structure MOS transistor at liquid nitrogen temperature.
上記目的は、ＬＤＤ層の燐イオン打込み量を１．５ Ｘ
１０１１Ｓｃｓ″″” 以上テ、２．５ Ｘ １０”
ｃｍ−２以下の量とすることにより達成される。より正
確な最適化はＬＤＤ層の燐イオン打込み量を１０１４ａ
１″″！、またはその近傍の値とすることにより達成さ
れる。The above purpose is to increase the amount of phosphorus ions implanted into the LDD layer by 1.5
1011Scs″″” or more, 2.5 x 10”
This is achieved by setting the amount to less than cm-2. A more accurate optimization is to increase the phosphorus ion implantation amount of the LDD layer to 1014a.
1″″! , or a value near it.
本発明の作用を新たに得た実験効果を用いて説明する。 The effect of the present invention will be explained using newly obtained experimental results.
第２図はＬＤＤ構造ｎＭＯＳトランジスタのＤＣストレ
ス実験結果を示したものである。FIG. 2 shows the results of a DC stress experiment on an LDD structure nMOS transistor.
ＤＣストレスとして印加したドレイン電圧は５ｖであり
、ゲート電圧は基板電流が最大となる値に設定している
。縦軸はストレスを１００００秒印加した後の非飽和領
域のトランスコンダクタンスＧｍの劣化率を示しており
、横軸はＬＤＤ層の燐イオン打込量（ａｍ−”）を示し
ている。第２図には、０℃（氷水）と７７にの面温度条
件でのホットキャリアによるＧｍ劣化率対しＤＤ部燐イ
オン打込量の関係を示した。室温に近い０℃では、従来
１９８４年アイ・イー・デー・エム テクニカルダイジ
ェスト、第７７４頁から７７７頁において示されている
結果と同様に、打込量１０ ”ｃｍ−”において劣化量
が最小となった。しかし液体窒素温度では、イオン打込
量１０工８ＧＷ″″２の従来デバイスはストレス時間１
００００秒で、約１０″′ｌの大きなＧｍ劣化を生じて
いる。これはＬＤＤ層抵抗がキャリアフリーズアウト効
果で増大するためである。これに対しイオン打込量を１
．５Ｘ１０１δ以上で２．５Ｘ１０”■−２以下の量と
すれば上記キャリアフリーズアウト効果を弱めることが
出来、従来デバイスよりも液体窒素温度（７７Ｋ）での
劣化率を低減できる。またこの時の７７に劣化率は室温
劣化率（約１Ｏ−２）の７倍以内に低減でき、産業的実
用性が確保される。イオン打込量を３×１０１８以上で
２．ｌＸ１０”（！１″″２以下の量とすれば室温劣化
率の５倍以内という産業的実用価値の有る信頼度が７７
にで確保される。さらに、イオン打込量を５×１０１３
以上テ１．８ Ｘ １０”ａ＋＋−２以下の量とすれば
、室温劣化率の３倍以内という産業的実用価値の有る信
頼度が７７ Ｋで確保される。The drain voltage applied as DC stress was 5V, and the gate voltage was set to a value that maximized the substrate current. The vertical axis shows the deterioration rate of the transconductance Gm in the non-saturated region after applying stress for 10,000 seconds, and the horizontal axis shows the amount of phosphorus ion implantation (am-'') in the LDD layer. Fig. 2 showed the relationship between the Gm deterioration rate due to hot carriers and the amount of phosphorus ion implanted in the DD under surface temperature conditions of 0°C (ice water) and 77°C.・Similar to the results shown in D.M. Technical Digest, pages 774 to 777, the amount of deterioration was the minimum at an implantation amount of 10 "cm-".However, at liquid nitrogen temperature, the amount of ion implantation decreased. Conventional device of 10 hours 8 GW″″2 has stress time of 1
0000 seconds, a large Gm deterioration of about 10''l occurs. This is because the LDD layer resistance increases due to the carrier freeze-out effect. In contrast, when the ion implantation amount is reduced to 1
．． If the amount is 5X101δ or more and 2.5X10"■-2 or less, the above carrier freeze-out effect can be weakened, and the deterioration rate at liquid nitrogen temperature (77K) can be reduced compared to conventional devices. Also, at this time 77 The deterioration rate can be reduced to within 7 times the room temperature deterioration rate (approximately 1O-2), ensuring industrial practicability.If the ion implantation amount is 3×1018 or more, If the following amount is used, the reliability level, which has industrial practical value within 5 times the room temperature deterioration rate, is 77.
Secured by. Furthermore, the ion implantation amount was increased to 5×1013
If the amount is less than 1.8 x 10''a++-2, reliability with industrial practical value of within three times the room temperature deterioration rate can be ensured at 77 K.
さらにより正確な最適化として、イオン打込量を１０１
４ａｓ−”またはその近傍の値とすることにより、７７
にでのホットキャリアによるＧｍ劣化率をほぼ室温値並
に抑えることが出来る。Furthermore, as a more accurate optimization, the ion implantation amount was increased to 101
By setting the value to 4as-” or its vicinity, 77
It is possible to suppress the Gm deterioration rate due to hot carriers to almost the room temperature value.
ＬＤＤ層の燐イオン打込量を１０１８ａｎ−２以下とし
たときもＬＤＤ部での電界緩和効果が強く効いて７７に
での劣化率を低減できるが、一方寄生抵抗増大になる動
作電流低下が問題となる。Even when the amount of phosphorus ions implanted into the LDD layer is set to 1018an-2 or less, the electric field relaxation effect in the LDD part is strong and the deterioration rate at 77 can be reduced, but on the other hand, the problem is that the operating current decreases due to an increase in parasitic resistance. becomes.
第３図にはＬＤＤ構造ｎＭＯＳトランジスタの寄生抵抗
測定結果を示す、ＬＤＤ層の燐イオン打込量が０．４
Ｘ Ｉ Ｏ”（！１−”の寄生抵抗対ゲート電圧特性カ
ーブ（ａ）および、同イオン打込量が１０”ａ１″″２
の特性カーブ（ｂ）が示すように、燐イオン打込み量が
１０”ｃｍ−”を下回ると７７にでの寄生抵抗が目立っ
て大きくなってしまう、この寄生抵抗増大は動作電流の
大きな低下を生じる。Figure 3 shows the parasitic resistance measurement results of an LDD structure nMOS transistor.The amount of phosphorus ion implanted into the LDD layer is 0.4.
Parasitic resistance vs. gate voltage characteristic curve (a) of
As shown in the characteristic curve (b), when the phosphorus ion implantation amount is less than 10"cm-", the parasitic resistance at 77 becomes noticeably large.This increase in parasitic resistance causes a large decrease in the operating current. .
本発明のようにＬＤＤ層打込量を１．５×１０１３以上
で２．５Ｘ１０２以下の量、または３Ｘ１０”８以上で
２．ｌＸ１０２以下の量、または５×１０１３以上で１
．８ Ｘ １０１’以下の量、さらに１０”（！ｌ−”
またはその近傍の値とした時は、カーブ（Ｃ）。As in the present invention, the LDD layer implantation amount is 1.5×1013 or more and 2.5×102 or less, or 3×10”8 or more and 2.1×102 or less, or 5×1013 or more and 1
．． 8 x 101' or less, plus 10"(!l-"
or a value close to it, curve (C).
（ｄ）、（ｅ）が示すように７７にでの寄生抵抗はほぼ
従来型室温値並の値（カーブ（ｆ））を示すことが明ら
かである。このように本発明は７７にでの寄生抵抗を増
すことなく、７７にでのホットキャリア劣化率を従来よ
りも大幅に低減できる。As shown in (d) and (e), it is clear that the parasitic resistance at 77 has a value (curve (f)) that is almost the same as the conventional room temperature value. In this manner, the present invention can significantly reduce the hot carrier deterioration rate at 77 compared to the conventional method without increasing the parasitic resistance at 77.
以下本発明の説明を実施例を用いて行なう０本発明によ
る第１の実施例を第１図に示す、第１図はＬＤＤ構造ｎ
チャネルＭＯＳトランジスタであり、ＬＤＤ層燐イオン
打込量を１０”３−”としている、１はｐ型Ｓｉ基板、
６はＳｉＯ工膜、７はポリシリコンからなるゲート電極
である。４，５は低不純物濃度のドレイン、ソース（ｎ
″″）層であり、燐を５０ＫａＶ以下で１Ｑ１４０−２
の量打ち込んで形成する。その接合深さ（Ｘ ｊ ）は
０．３μｍ以下であり、表面不純物濃度は１０１６〜１
０ｓ。The present invention will be explained below using examples. A first example according to the present invention is shown in FIG. 1.
It is a channel MOS transistor, and the amount of phosphorus ion implanted in the LDD layer is 10"3-", 1 is a p-type Si substrate,
6 is a SiO film, and 7 is a gate electrode made of polysilicon. 4 and 5 are low impurity concentration drain and source (n
"") layer, phosphorus is 1Q140-2 at 50KaV or less
Form by punching in the amount of The junction depth (X j ) is 0.3 μm or less, and the surface impurity concentration is 1016 to 1
0s.
３″″Ｓである。８はゲート電極側壁部に形成したスペ
ーサ酸化膜であり、ＬＤＤ層形成後ＨＬＤ（Ｈｉｇｈ
Ｔｅｍｐｅｒａｔｕｒｅ−Ｌｏｗ Ｐｒｅｓｓｕｒｅ
Ｄｅｐｏｓｉｔｉｏｎ）法で堆積したものである。２，
３はスペーサ８を形成後、砒素（Ａ＠）イオンを１０
”〜１０１ｓａａ−”イオン打釘みして形成した高濃度
ｎ型領域であり、ｎＭＯＳトランジスタのドレイン・ソ
ースとなる。It is 3″″S. 8 is a spacer oxide film formed on the side wall of the gate electrode, and after forming the LDD layer, the HLD (High
Temperature-Low Pressure
The film was deposited by a method (deposition). 2,
3, after forming the spacer 8, 10 arsenic (A@) ions are added.
"~101saa-" This is a high concentration n-type region formed by ion hammering, and becomes the drain and source of the nMOS transistor.
本実施例において実測した液体窒素温度（７７Ｋ）での
寄生抵抗値は第３図に示すようにゲート電圧５ｖで約１
００Ωであり、従来デバイス（ＬＤＤ層燐イオン打込量
； １０１８ａｍ−”）の室温寄生抵抗値にほぼ等しい
値となった。また本実施例によればその７７にでのＧｍ
劣化率は、第２図に示すようにフォアワードモードで１
０−２ リバースモードで４×１０″″２に低減出来、
７７にでのホットキャリア信頼性を改善することができ
た。The parasitic resistance value actually measured in this example at the liquid nitrogen temperature (77K) was approximately 1 at a gate voltage of 5V, as shown in Figure 3.
00Ω, which is almost equal to the room temperature parasitic resistance value of the conventional device (LDD layer phosphorus ion implantation amount: 1018 am-”). Also, according to this example, the Gm at 77
The deterioration rate is 1 in forward mode as shown in Figure 2.
0-2 Can be reduced to 4 x 10''2 in reverse mode,
We were able to improve the hot carrier reliability at 77.
本実施例ではＬＤＤ層燐イオン打込量を１０１４ｄｌｌ
″″！としたが、打込量を１．５ Ｘ １０”以上で２
．５ Ｘ １０”ｍ−” 以下（１）量トスレば７７に
劣化率を室温値の７倍以内におさえて産業的実用性が確
保できる。また３×１０１３以上で２．ｌＸ１０１番０
１１″″！以下の量、および５Ｘ１０”８以上で１．８
×１０”（！１″″２以下の量としても、７７に劣化率
をそれぞれ従来型室温値の５倍以内の値および３倍以内
の値におさえて産業的実用性を確保できる。In this example, the amount of phosphorus ion implanted in the LDD layer was 1014 dll.
″″! However, if the driving amount is 1.5 x 10” or more, 2
．． 5 x 10"m-" or less (1) If the amount of strain is 77, the deterioration rate can be suppressed to within 7 times the room temperature value and industrial practicability can be ensured. Also, 2.3×1013 or more. lX101 No. 0
11″″! 1.8 in the following amounts and 5X10”8 or more
Even if the amount is less than 10"(!1""2), industrial practicability can be ensured by suppressing the deterioration rate to within 5 times and within 3 times the conventional room temperature value, respectively.
本発明の第２の実施例を第４図に示す。A second embodiment of the invention is shown in FIG.
本実施例は非対称低濃度ドレイン（ＬＤＤ）型判
７チヤネルＭｏＳトランジスタの発明例であり、本実施
例が第１の実施例と異なるところは、第１の実施例の低
不純物濃度ソース、５の代わりに。This example is an invention example of an asymmetric low concentration drain (LDD) type 7-channel MoS transistor, and the difference between this example and the first example is that the low impurity concentration source of the first example, instead.
不純物濃度の高いｎ型不純物領域９を形成している点に
ある。低濃度ドレイン４は第１の実施例と同様に燐を５
０ＫｅＶ以下で１０”０１″″工の量、打外部端子から
見た実効ゲート電圧を低下させることなく、ホットキャ
リア耐圧を増加で肴る。そして低濃度ドレイン濃度の最
適化で７７にでの素子劣化を従来デバイスに比べて約１
桁低減できる。The point is that an n-type impurity region 9 with a high impurity concentration is formed. The low concentration drain 4 contains 5 phosphorus as in the first embodiment.
At 0 KeV or less, the hot carrier breakdown voltage can be increased without reducing the effective gate voltage seen from the external terminal with the amount of 10"01" processing.Then, by optimizing the low concentration drain concentration, the element in 77. Deterioration is reduced by approximately 1 compared to conventional devices.
It can be reduced by orders of magnitude.
本発明はＬＤＤ構成ＭＯＳトランジスタの低濃度ドレイ
ン部燐イオン打込み量を１．５Ｘ１０”δ１−１以上２
．５Ｘ１０”Ｃ１１−２以下の量としたもので、これに
より７７にでのホットキャリア劣化率を従来デバイス値
よりも低減できた。In the present invention, the amount of phosphorus ion implanted in the low concentration drain portion of an LDD configuration MOS transistor is 1.5×10”δ1−1 or more2
．． The amount was set to 5×10”C11-2 or less, which made it possible to reduce the hot carrier deterioration rate at 77 mm compared to the conventional device value.
また本発明は上記燐イオン打込量を１０”（１ｍ−”ま
たはその近傍の値としたもので、これにより７７にでの
劣化率を最小化でき従来デバイスの室温値並に低減でき
た。Further, in the present invention, the amount of phosphorus ion implanted is set to 10'' (1 m-'') or a value in the vicinity thereof, thereby minimizing the deterioration rate at 77°C and reducing it to the same level as the room temperature value of conventional devices.
第１図は本発明の第１の実施例を示す図、第２図は本発
明デバイスのホットキャリア信頼性を示す図、第３図は
本発明デバイスの寄生抵抗結果を示す図、第４図は本発
明の第２の実施例を示す図である。
１・・・ｐ型Ｓｉ基板、
２・・・ドレイン、
３・・・ソース、
４・・・低濃度ドレイン、
５・・・低濃度ソース、
６・・・
第
図
図FIG. 1 is a diagram showing the first embodiment of the present invention, FIG. 2 is a diagram showing the hot carrier reliability of the device of the present invention, FIG. 3 is a diagram showing the parasitic resistance results of the device of the present invention, and FIG. FIG. 2 is a diagram showing a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2...drain, 3...source, 4...low concentration drain, 5...low concentration source, 6...Fig.
Claims (1)
ゲート電極に隣接する表面部分に、不純物濃度が他のド
レイン・ソース領域の不純物濃度よりも低いｎ型不純物
領域を有するｎチャネルＭＯＳトランジスタを有し、前
記の低濃度ｎ型不純物領域が燐イオンを１．５×１０＾
１＾３以上で２．５×１０＾１＾４ｃｍ＾−＾２以下の
量だけ打込んで形成されていることを特徴とする半導体
装置であり、かつ該装置を１５０以下の動作温度に冷却
するための冷却手段を具備した半導体装置。 ２、該低濃度ｎ型不純物領域が燐イオンを３×１０＾１
＾３以上で２．１×１０＾１＾４ｃｍ＾−＾２以下の量
だけ打込んで形成されていることを特徴とする特許請求
の範囲第１項記載の半導体装置。 ３、該低濃度ｎ型不純物領域が燐イオンを５×１０＾１
＾８以上で１．８×１０＾１＾４ｃｍ＾−＾２以下の量
だけ打込んで形成されていることを特徴とする特許請求
の範囲第１項記載の半導体装置。 ４、該低濃度ｎ型不純物領域が燐イオンを１０＾１＾４
ｃｍ＾−＾２の量またはその近傍の量だけ打込んで形成
されていることを特徴とする特許請求の範囲第１項記載
の半導体装置。 ５、液体窒素温度、またはその近傍の温度範囲で動作さ
せることを特徴とする特許請求の範囲第１項、第２項、
第３項および第４項のいずれかに記載の半導体装置。[Claims] 1. An n-channel MOS having an n-type impurity region in a surface portion of at least one of the drain and source regions adjacent to the gate electrode, the impurity concentration of which is lower than that of the other drain and source regions. It has a transistor, and the low concentration n-type impurity region absorbs phosphorus ions at 1.5×10^
A semiconductor device characterized in that it is formed by implanting an amount of 1^3 or more and 2.5 x 10^1^4 cm^-^2 or less, and the device is cooled to an operating temperature of 150 or less. A semiconductor device equipped with a cooling means for 2. The low concentration n-type impurity region absorbs 3×10^1 phosphorus ions.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by implanting an amount equal to or larger than ^3 and equal to or less than 2.1 x 10^1^4 cm^-^2. 3. The low concentration n-type impurity region absorbs 5×10^1 phosphorus ions.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by implanting an amount equal to or larger than ^8 and equal to or less than 1.8 x 10^1^4 cm^-^2. 4. The low concentration n-type impurity region absorbs phosphorus ions by 10^1^4
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by implanting an amount of .cm^-^2 or an amount in the vicinity thereof. 5. Claims 1 and 2, characterized in that the device is operated at liquid nitrogen temperature or a temperature range in the vicinity thereof.
The semiconductor device according to any one of Items 3 and 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3357589A JP2708525B2 (en) | 1989-02-15 | 1989-02-15 | MOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3357589A JP2708525B2 (en) | 1989-02-15 | 1989-02-15 | MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02214123A true JPH02214123A (en) | 1990-08-27 |
| JP2708525B2 JP2708525B2 (en) | 1998-02-04 |
Family
ID=12390331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3357589A Expired - Fee Related JP2708525B2 (en) | 1989-02-15 | 1989-02-15 | MOS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2708525B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925914A (en) * | 1997-10-06 | 1999-07-20 | Advanced Micro Devices | Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance |
-
1989
- 1989-02-15 JP JP3357589A patent/JP2708525B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5925914A (en) * | 1997-10-06 | 1999-07-20 | Advanced Micro Devices | Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2708525B2 (en) | 1998-02-04 |
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