JPS6298779A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the characteristics of a GaAs.MES.FET, by constructing an impurity introduction layer such that it has different depths from the surface and different impurity concentrations at different positions. CONSTITUTION:A source region 5 and a drain region 6 consist of N<+> type layers extended below a source electrode 1 and a drain electrode 2, respectively. A channel layer 7 extended below a gate electrode 3 and between the source and drain regions 5 and 6 has the bottom inclined such that the depth (thickness) thereof is progressively decreased from the source electrode 1 toward the drain electrode 2. The impurity concentration of the channel layer 7 is also inclined such that the impurity concentration is progressively decreased from the source electrode 1 toward the drain electrode 2. Accordingly, the parasitic resistance RS and the channel resistance R can be decreased and the mutual conductance gm and the noise factor NF can be increased. Further, the drain dielectric strength VDSX can be increased.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a structure in which the depth and impurity concentration of a diffusion layer formed in a semiconductor substrate are different in each portion (position), and its manufacturing method. Regarding the manufacturing method.

〔Technical field〕

A gallium arsenide field effect transistor (abbreviated as GaΔS-MES-FET), which is formed based on a substrate with a zincblende crystal structure, is a microwave transistor with features such as low noise, high cutoff frequency, and high output. widely known. Also, as one of these GaAs-MES-FETs, a Schottky barrier gate field effect transistor (S
It is abbreviated as BG・FET. )It has been known. SBG-F
ET consists of a source/train electrode with an ohmic contact structure provided on the main surface of the n-conductivity type active region, and one or two gate electrodes with a Schottky junction structure provided in between. It constitutes a gate structure.

For example, as an example of a GaAs-MES FET, there is one described in "Electronic Materials J, August 1975 issue, August 1, 1975, published by Kogyo Research Association, pages 65 to 69. There is.

By the way, the cutoff frequency of GaAs-MES-FET (
The high frequency characteristics such as f, ) and noise figure (NF) depend on the mutual conductance (gl), as shown by the following equation, and the higher g is, the better they are.

C9゜Here, f is the measurement frequency, R3 is the parasitic resistance, Ro
is the gate resistance, C, is the gate-source capacitance.

Moreover, gl is given by the following formula.

Note that here, gmo: intrinsic mutual conductance.

Therefore, in order to increase the mutual conductance, it can be seen from the above equation (3) that the parasitic resistance should be reduced. In order to reduce the parasitic resistance, the impurity concentration in the channel layer may be increased, but if this impurity concentration is made too high, the withstand voltage on the drain side becomes low, making it difficult to set it.

For this reason, the present inventor has developed the above-mentioned GaAsME
In the case of S-FETs, I realized that it is sufficient to make the channel layer deep and have a high impurity concentration on the source side, and to make the channel layer shallow (and have a low impurity concentration) on the source side. The present invention has been accomplished.

[Purpose of the invention]

An object of the present invention is to provide a technique that can improve the characteristics of a GaAs-MES-FET.

Another object of the present invention is to provide a technique that can improve the characteristics of field effect transistors made of silicon, GaAs, or the like.

Another object of the present invention is to provide a technique for manufacturing a diffusion layer in which each part of the diffusion layer has a different thickness and impurity concentration.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, according to the present invention, when ions are implanted into the main surface of a GaAs substrate to form a channel layer of a GaAs-MES-FET, the thickness of the main surface of the GaAs substrate gradually increases from the source side to the drain side. After forming a through film made of a thicker insulating film, ions are implanted toward the surface of this through film, and the source side is thicker and has a higher impurity concentration, while the drain side is thinner and has a higher impurity concentration. By forming a channel layer with a thin sloped bottom structure and a sloped concentration structure, parasitic resistance on the source electrode side is reduced, and mutual conductance is increased by increasing the withstand voltage on the drain side.
This improves high frequency characteristics such as cutoff frequency and noise figure.

〔Example〕

FIG. 1 shows a QaAs-MES according to an embodiment of the present invention.
Schematic diagram showing the expansion state of the depletion layer in FET, Part 2
The figure is also a new view showing the outline of C; aAs-MEs-FET chip, Figure 3 is a cross-sectional view of the state in which an n-domain layer is formed on the main surface of a wafer in chip manufacturing, and Figure 4 is the same. A cross-sectional view of a wafer with an auxiliary film formed on the main surface of the wafer to form a through film with an inclined cross-sectional structure, FIG. 5 is a cross-sectional view of a wafer with a through film formed thereon, and FIG. FIG. 7 is a cross-sectional view of a wafer with a sloped structure diffusion layer formed thereon whose impurity concentration gradually changes in the direction of its extension; FIG. 7 is a cross-sectional view of the wafer with a source electrode and a drain electrode formed; FIG. 8 is a cross-sectional view of the wafer with gate electrodes formed thereon, and FIG.
The figure is also a cross-sectional view of the wafer with bonding pads formed, and Figure 14 is a conventional GaAs-MES-FE.
FIG. 3 is a schematic diagram showing the spread state of a depletion layer at T.

This embodiment shows an example in which the present invention is applied to the manufacturing technology of a GaAs Schottky barrier gate field effect transistor (GaAsMES-FET). Ga As ME
As shown in FIGS. 1 and 2, an S-FET chip (hereinafter simply referred to as a chip) has a part of the gate electrode (S) between a source electrode (S) 1 and a drain electrode (D) 2. G)
It has a single gate structure with 3 gates.

A characteristic feature of the chip 4 of this embodiment is that the chip 4 extends below the gate electrode 3, and has a source electrode 1 and a drain electrode 2.
Source regions 5 each consisting of an n-domain layer extending below
．． a channel layer 7 extending between the drain region 6 and the drain region 6;
is different from the conventional structure. In other words, the channel layer 7 has a sloped bottom structure in which the depth (depth and thickness) gradually becomes shallower as it goes from the source electrode 1 side to the drain electrode 2 side, and the impurity concentration also decreases as it goes from the source electrode 1 to the drain electrode 2 side. It has a gradient concentration structure that gradually becomes thinner (lower).

As a result, the GaAs-MES-FET of the present invention is different from the conventional Qa, As-MES-FET as shown in FIG.
Compared to a structure in which the thickness and depth of the channel layer 7 and the impurity concentration are constant, such as in a FET, as shown in FIG. is large and the impurity concentration is high, so the parasitic resistance R5 and the channel resistance R can be reduced, so as can be seen from equations (1) and (3) above, the mutual conductance g and the noise figure NF can be increased. I can do it. In addition, in the channel N7 according to the present invention, since the impurity concentration gradually decreases from the source electrode 1 to the drain electrode 2, the depletion layer 8 can have a sufficient thickness. Breakdown voltage ■, sX becomes higher. Furthermore, since the impurity concentration on the drain electrode side is low, the pinch-off voltage is low, and the dark value voltage is low.

Although not particularly limited, for example, the length of the channel layer 7 is about 5 μm, and the length of the source electrode 1 is about 5 μm.
The thickness (depth) on the drain electrode 2 side is 200 μm, and the thickness (depth) on the drain electrode 2 side is 500 μm. Also,
As shown in FIG. 1, a source electrode 1. Drain electrode 2. A portion of the gate electrode 3 is covered with an insulating pansivation film 9. Further, one end of a wire 11 extending between the bonding panode 10 of each electrode exposed from the burnishing film 9 and a portion to be an external terminal is connected.

Next, a method for manufacturing such a chip 4 will be explained. The chip 4 is manufactured through the steps shown in FIGS. 3 to 9, and becomes the chip 4 as shown in FIG. 2.

First, as shown in FIG. 3, a compound semiconductor thin plate (wafer) 12 that will become a semiconductor substrate is prepared. This wafer 12 consists of a semi-insulating GaAs substrate 13. Further, on this GaAs substrate 13, a source region 5 and a drain region 6 made of an n-type layer are formed to a thickness of several μm by ion implantation using the insulating film 14 already partially provided on the main surface. It is formed.

Next, the insulating film 14 is removed. Thereafter, as shown in FIG. 4, an insulating film 15 is provided on the drain region 6 side in order to form a through film with an inclined structure. One edge of this insulating film 15 is located approximately on the edge of the drain region 6 facing the source region 5. This insulating film 14 has a thickness of, for example, about 1 μm, although it is not particularly limited.

As shown in FIG. 5, a through hole 16 made of an insulating film or the like is formed over the entire main surface of the wafer 12 to a thickness of about 1 μm, for example, by CVD. As a result, the through film 16 at the step portion at the end of the insulating film 15 has a gently sloped structure (slanted through film 17).

Next, as shown in FIG. 6, a mask 18 made of an insulating film is formed on the through film 16.

This mask 18 is not provided in the region corresponding to the region where the gate is formed, but is provided in the source region 5 and drain region 6.
It covers other areas including. Ions are implanted into the entire main surface of such a wafer 12. In the region where the through film 16 and the mask 18 covering the through film 16 are provided, the ions are cut and are not implanted into the surface layer of the main surface of the GaAs substrate 13. However, in the region where only the through film 16 is present, the through film 16 is implanted to form a channel layer 7 made of an n-type layer. In this case, since the exposed through film 16 portion is the inclined through film 17,
The amount of ions passing through each portion of the inclined through film 17 is approximately inversely proportional to the thickness of the inclined through film 17. - As a result, the channel layer 7 implanted into the surface layer of the GaAs substrate 13 is deep (thick) and has a high impurity concentration on the source electrode 1 side, but shallow (thin) on the drain electrode 2 side.
Moreover, the impurity concentration is also lowered (thinner), and the bottom of the channel layer 7 has a sloped structure. In the channel layer 7 having such a sloped bottom structure and a sloped concentration structure, the channel resistance R becomes low, and the parasitic resistance R8 on the source electrode 1 side becomes small. Furthermore, since the channel layer 7 is thinner and has a lower concentration on the drain electrode 2 side, the drain withstand voltage VO58 increases and the pinch-off voltage decreases. Further, it is also possible to improve the train conductance gd.

Next, the insulating film 15. Through membrane 16. Mask 18 is removed. Thereafter, as shown in FIG. 7, the main surface of the wafer 12 is made of Si, except for the regions where the source electrode 1 and the drain electrode 2 are to be formed, by conventional photolithography.
An insulating film 19 such as an O□ film is provided, and an Au-Ge film with a thickness of about 1 μm is deposited on the formation regions of the source electrode 1 and drain electrode 2, respectively, by vapor deposition and lift-off methods.
A source electrode 1 and a drain electrode 2 made of /N i /A u are formed.

Next, as shown in FIG. 8, gate electrodes 3 are formed again on the main surface of the wafer 12 by conventional photolithography.
An insulating film 20 is formed in the region excluding the region where the insulating film 20 is formed, and a channel layer consisting of an n shadow region is formed using the insulating film 20 and the photoresist film (not shown) remaining on the insulating film 20 as a mask. 7 is etched to a desired depth to form a groove (recess) 21. Further, on the photoresist film, for example, although not particularly limited, aluminum is vapor deposited, and the gate electrode 3 is formed by removing the photoresist film (lift-off method).

Next, after the insulating films 19 and 20 are removed, as shown in FIG.
At the same time, the portions of the insulation film 9 where the bonding pads are to be formed are removed by common photolithography, and the bonding pads 10 of each electrode are formed. Further, the evaporator 12 is divided into a lattice shape (9th
It is divided at a dividing line 22, which is a chain double-dashed line in the figure. ), a chip 4 as shown in FIG. 2 is manufactured.

Such a chip 4 is fixed to a support plate, and each of the bonding pads 6 and the inner end of a lead or the like serving as an external terminal is connected by a wire 11, and is further sealed in a resin package or a ceramic package to produce an electric field effect. Used as a single transistor.

〔effect〕

(1) In the GaAs MESFET of the present invention, the channel layer has a sloped bottom structure in which the bottom gradually rises from the source electrode to the drain electrode, and
Since the impurity concentration is also high on the source electrode side and low on the drain electrode side, both the channel resistance and the parasitic resistance on the source electrode side are reduced, resulting in the effect of increasing mutual conductance.

(2) From the above (1), the GaAs-MES of the present invention
-FET has a thin channel layer on the drain electrode side and a low impurity concentration, so that the pinch-off voltage is lowered and the characteristics of drain breakdown voltage and drain conductance are improved.

(3) From (2) above, the GaAs-MES-F of the present invention
Since the pinch-off voltage is reduced in ET, the effect that the dark value voltage VIH is reduced can be obtained.

(4) According to (1) to (3) above, the GaAs-
MES-FET has improved cut-off frequency,
A synergistic effect of improving high frequency characteristics such as noise figure and power gain can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say, for example, the material forming the inclined through film may be photoresist, polyimide resin, or the like. In addition, as a method for forming the inclined through film, it is also possible to form a film on the main surface of a wafer having an insulating film on a part thereof using a spinner, or to form the inclined through film on the step part with the insulating film. can. In this case, it is necessary to set the rotational speed of the spinner and the viscosity of the liquid such as photoresist to a desired level to form a tilted through film having a desired slope.

Further, as another method for forming an insulating film inclined through film, for example, as shown in FIG.
A photoresist film 24 is partially formed on 3, and then
As shown in FIG. 13, dry etching is performed from an oblique direction to the main surface of the CaAs substrate 13,
Even with a method of forming inclined through films having different thicknesses, the same effects as in the above embodiment can be obtained.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the manufacturing technology of QaAs Schottky barrier gate type field effect transistors, which is the field of application that formed the background of the invention, but the invention is not limited thereto. For example, as shown in FIG. 12, a silicon substrate 25 is used and a gate electrode 3 is placed on a gate insulating film 23.
As shown in FIG. 13, a junction FET (J
-FET) can be similarly applied to obtain the same effect as the above embodiment.

The present invention is applicable to at least semiconductor device manufacturing technology.

[Brief explanation of drawings]

FIG. 1 shows a GaAs-MES- according to an embodiment of the present invention.
A schematic diagram showing the expansion state of the depletion layer in a FET, Figure 2 is a cross-sectional view showing the outline of the same <GaAs-MES-FET chip, and Figure 3 is a diagram showing the formation of an n-domain layer on the main surface of a wafer during chip manufacturing. Figure 4 is a cross-sectional view of the wafer with an auxiliary film formed on the main surface of the wafer to form a through film with an inclined cross-sectional structure, and Figure 5 is a cross-sectional view of the wafer with a through film formed on the main surface of the wafer. FIG. 6 is a cross-sectional view of a wafer in which a sloped diffusion layer whose depth and impurity concentration gradually change in the direction of its extension is formed, and FIG. FIG. 8 is a cross-sectional view of the wafer with gate electrodes formed. FIG. 9 is a cross-sectional view of the wafer with bonding pads formed. FIG. 10 is a cross-sectional view of the wafer with electrodes formed. A sectional view of a wafer showing a film forming state in through film formation according to another embodiment of the present invention, FIG. 13 is a cross-sectional view showing the main parts of a JIFET according to another embodiment of the present invention; FIG. 14 is a schematic diagram showing the spread state of the depletion layer in a conventional GaAs-MES-FET. It is a diagram. DESCRIPTION OF SYMBOLS 1... Source 'Jffi (S), 2---Drain electrode (D), 3... Gate electrode, 4... Element (chip), 5... Source region, 6... Drain region ,7
... Channel layer, 8... Depletion layer, 9... Passivation film, 10... Bonding by, 12...
・Compound semiconductor thin plate (wafer), 13...GaAs substrate, 14.15-...insulating film, 16...through film, 1
7... Slanted through film, 18... Mask, 19.20
... Insulation, 21 ... Groove (recess), 22 ... Parting line, 23 ... Insulating film, 24 ... Photoresist film, 2
5. . . . silicon base, 26. . . gate insulating film, 27 . . . gate I region, 28 . . . pn junction.

Claims (1)

[Scope of Claims] 1. A semiconductor device in which a channel is formed by providing an impurity-introduced layer on a substrate, wherein the impurity-introduced layer has a different depth from the surface and its impurity concentration at each position. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the channel layer in the field effect transistor has a depth from the surface and an impurity concentration that gradually become shallower and thinner as it goes from the source to the drain. . 3. A method for manufacturing a semiconductor device in which a channel is formed by forming an impurity-introduced layer on a substrate, the step of forming a through film having a thickness different in each part on the main surface of the substrate; A method for manufacturing a semiconductor device, comprising the step of implanting ions into the main surface of the substrate by implanting ions into the through film surface to form an impurity-introduced layer having a different depth and impurity concentration in each part.