JP3038720B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a compound semiconductor field-effect transistor, and more particularly, to a method for manufacturing a GaAs Schottky barrier field-effect transistor.

〔Overview〕

The present invention relates to a method for manufacturing a field-effect transistor including an operation layer formed on a semiconductor substrate and a gate electrode provided on the operation layer, wherein the operation layer has two high-concentration layers in a direction deeper than the substrate surface. Performing ion implantation so as to have an impurity concentration distribution having a low concentration between these two high-concentration regions, and providing the gate electrode at a portion where the operation layer is removed from the surface to the depth of the low-concentration region. Reduces parasitic resistance while maintaining high withstand voltage and low interelectrode capacitance.
This is for higher performance.

[Conventional technology]

Field effect transistors, in particular, GaAs Schottky barrier gate type field effect transistors (hereinafter, referred to as Ga) using an n-type GaAs layer formed by ion implantation into a semi-insulating GaAs substrate.
As MESFET. ) Has been developed as an ultra-high-speed and ultra-high-frequency device that breaks the limits of Si bipolar transistors, and has been put to practical use. In order to improve the performance of such GaAs MESFET, (1) improvement of transconductance (gm) by reducing source resistance (Rs), and (2) breakdown voltage between source and gate and between drain and gate (BV _GS , BV _GD ) (3) It is necessary to reduce the gate-source capacitance and the gate-drain capacitance (C _GS , C _GD ).

FIG. 4 is a schematic vertical sectional view showing an example of a conventionally used GaAs MESFET. In FIG. 4, 1 is a gate electrode, 2 is a source electrode, 3 is a drain electrode, 4 is a GaAs operation layer, and 5 is a semi-insulating GaAs substrate.

FIG. 5 shows an example of the impurity concentration distribution in the depth direction of the GaAs operation layer 4 obtained by one ion implantation which is conventionally used. Implanted ions are Si and implantation energy is 200 KeV
It is.

[Problems to be solved by the invention]

When the gate electrode 1 having the Schottky barrier property is formed on the surface of the GaAs operation layer 4 having the impurity concentration distribution shown in FIG.
Although characteristics of high V _GS and BV _{GD and} low C _GS and C _GD can be obtained, there is a problem that Rs is not sufficiently reduced and the characteristics of gm are low.

An object of the present invention is to provide a method for manufacturing a field-effect transistor having high BV _GS and BV _GD , low C _GS and C _GD , and low Rs and high gm by solving the above problems. is there.

[Means for solving the problem]

The present invention is a step of selectively performing deep ion implantation and shallow ion implantation on a semi-insulating GaAs substrate to form an operation layer having two peaks in impurity concentration in the depth direction from the substrate surface, Forming a recess by etching from the surface of the operation layer to a portion where the impurity concentration becomes substantially minimum between the two peaks; and forming a gate electrode on the bottom surface of the recess.

[Action]

According to the present invention, after forming a GaAs active layer twice, for example, deep implantation and shallow implantation at different acceleration voltages, the gate region is etched with a low concentration between the deep implantation and the shallow implantation high concentration region. It goes to the depth, where the gate electrode is provided.

Therefore, a high BV _GD , BV _GS and a small C _GS , C _GD can be obtained by lowering the GaAs surface concentration in contact with the gate electrode, and a high concentration region outside the gate region can be obtained by a shallow implantation effect. Rs is sufficiently reduced to obtain a high gm.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic longitudinal sectional view showing one embodiment of the present invention. And FIG. 2 is an impurity concentration distribution diagram of the GaAs operation layer.

In the present embodiment, a GaAs operation layer 4 formed on a semi-insulating GaAs substrate 5, a gate electrode 1 provided on the GaAs operation layer 4, a source electrode 2 and a drain electrode 3 are provided.
In the As MESFET, as shown in FIG. 2, the GaAs operation layer 4, which is a feature of the present invention, has two high-concentration regions in the depth direction from the substrate surface, and the two high-concentration regions The gate electrode 1 has an impurity distribution that becomes a low concentration region, and the gate electrode 1 is provided in a portion where the GaAs operation layer 4 is removed from the surface to the depth of the low concentration region by etching.

Next, the manufacturing method of this embodiment will be described with reference to FIG.
A description will be given with reference to schematic cross-sectional views of the embodiment in the main steps shown in FIGS.

First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 5 is selectively applied to 200 KeV, 4 × 10 ¹² cm ⁻² and 30 Ke.
After implanting Si ions under two conditions of V and 5 × 10 ¹² cm ⁻² , heat treatment is performed at 800 ° C. for 20 minutes using SiO ₂ as a protective film to form an n-type GaAs active layer 4. . At this time, as shown in FIG. 2, the impurity concentration distribution in the depth direction from the substrate surface has two high concentration regions in the depth direction from the substrate surface, and a low concentration region exists between these two high concentration regions. The impurity concentration distribution becomes a region.

Next, as shown in FIG. 3 (b), for example, H ₂ SO ₄ : H ₂
The GaAs surface near the gate region is etched to a depth of 700 ° using an etchant of O ₂ : H ₂ O = 50: 1: 15. As can be seen from FIG. 2, this depth is a low density area between the two high density areas.

Finally, as shown in FIG. 1 (c), a Schottky barrier gate electrode 1 made of aluminum (Al) is provided in the etched gate region, and gold / germanium and nickel (Ni / Ni) are provided on both sides of the gate electrode. By forming the ohmic source electrode 2 and the drain electrode 3 made of AuGe), the manufacture of the GaAs MESFET is completed.

As a result of measuring the cutoff frequency (gain bandwidth product) fT (gm / 2πC _GS ) of this example and the conventional example shown in FIG.
The present embodiment is 30 GHz, which is 1.5 times that of 0 GHz.

Further, in the above-described manufacturing method, Si ions are implanted twice to form the GaAs active layer 4, but deep ion implantation is performed by Si and shallow ion implantation is performed by tin (S
n) was also fabricated. In the case of Sn, since the mass is larger than that of Si, the ion-implanted layer can be formed only on the very surface of GaAs, so that the effect of the present invention can be further enhanced.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain a field-effect transistor having a high BV _GD , a high BV _GS , a small C _GS , a small C _GD , and a small Rs and a large gm, and the effect is large. .

[Brief description of the drawings]

FIG. 1 is a schematic longitudinal sectional view showing one embodiment of the present invention. FIG. 2 is an impurity concentration distribution diagram in the depth direction from the surface of the GaAs operation layer. 3 (a) to 3 (c) are schematic longitudinal sectional views in main manufacturing steps. FIG. 4 is a schematic longitudinal sectional view showing a conventional example. FIG. 5 is an impurity concentration distribution diagram in the depth direction from the surface of the GaAs operation layer. 1 ... gate electrode, 2 ... source electrode, 3 ... drain electrode, 4 ... GaAs operation layer, 5 ... semi-insulating GaAs substrate.

Claims (1)

(57) [Claims] A step of selectively performing deep ion implantation and shallow ion implantation on a semi-insulating GaAs substrate to form an operation layer having two peaks in impurity concentration in a depth direction from the substrate surface; Forming a recess by etching from the surface of the operation layer to a portion where the impurity concentration is substantially minimum between the two peaks; and forming a gate electrode on the bottom surface of the recess. Method for manufacturing effect transistor.