JPS6146984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a short channel MIS field effect transistor with high breakdown voltage between source and drain.

Recently, it has become increasingly important to increase the integration density of ICs, improve the mutual conductance g _n of MIS field-effect transistors (FETs), and shorten the channel length or gate length between the source and drain in order to increase the switching speed. This is a general trend. However, if the gate length is simply shortened, the depletion layer from the drain easily reaches the source.
The drain breakdown voltage will decrease. One way to avoid this is to increase the substrate concentration to make it difficult for the depletion layer to expand, thereby increasing the short-circuit breakdown (punch-through) breakdown voltage. However, a drawback of this method is that the depletion layer becomes narrower, so that the junction capacitance between the source and drain increases and the high frequency characteristics deteriorate. Therefore, channel doping technology was proposed as another method that takes these into consideration. This is to suppress the junction capacitance between the source and drain by using a low concentration substrate, and to increase the punch-through breakdown voltage by doping only the channel region with a high concentration. The common disadvantages of these two methods are that the channel formation region becomes highly doped, which increases the substrate effect of the threshold voltage, that the channel depletion layer becomes shallow, deteriorating the blocking characteristics, and that when impurity atoms or ions are implanted, The field effect mobility decreases due to an increase in the number of defects.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a short channel MIS transistor that can eliminate the above-mentioned drawbacks.

In order to achieve the above object, the method for manufacturing an MIS transistor of the present invention involves removing the insulating oxide from the source, drain and channel portions of a semiconductor substrate on which the insulating oxide is deposited, and forming a gate oxide film by reoxidation. A polycrystalline silicon layer and a first mask layer are sequentially formed on top of the polycrystalline silicon layer, and a photoresist is applied and patterned on top of the polycrystalline silicon layer to leave a gate portion, and the other portions of the first mask layer and the polycrystalline mask layer are formed. After etching away the crystalline silicon layer until the photoresist becomes a canopy, and then forming a second mask layer on the photoresist and on the source and drain regions,
The photoresist and the second mask layer thereon are removed, and ions of the same conductivity type are implanted into the substrate using the first and second mask layers as masks to eliminate the diffusion formed in the source and drain regions. This is characterized in that a high concentration region of the same conductivity type as the substrate is formed at the end of the region opposite to the channel forming region, which is deeper than the depth of diffusion of the source and drain.

The present invention will be described in detail below with reference to examples.

Figure 1 shows a conventional MIS field effect transistor.
This figure shows the structure of a MOS field effect transistor using the aforementioned channel doping technique. In the figure, the oxide film 2 on the source, drain and channel portions of the semiconductor substrate 1 on which the oxide film 2 has been deposited is removed, and a layer of the same conductivity type as the substrate 1 is placed directly under the channel portion between the source and drain diffusion regions 3 and 4. A deep low concentration region 6 and a shallow high concentration channel forming region 5 are provided above the deep low concentration region 6, and a gate oxide film 7 and a polycrystalline silicon layer 8 are formed thereon. After that, the source, drain,
Electrodes for the gate portion are formed.

FIG. 2 is an explanatory diagram showing the configuration of the MIS transistor according to the present invention. In this figure, the difference from FIG. 1 is that the substrate 1 is a low concentration substrate.
The deep low concentration region 6 immediately below the channel is not particularly provided, and the source and drain diffusion regions 3,
High concentration regions 10 and 11 having the same conductivity type as the substrate 1 and deeper than the diffusion depth of the source and drain are provided at the end portions facing the channel forming region 5 of No. 4, respectively.

With such a configuration, the concentration and depth of the channel forming region 5 can be centrally determined by considering only the change in the threshold voltage, so that the above-mentioned problems such as the high concentration of the channel forming region and the depth of the channel can be fixed. Substrate effects caused by the shallowing of the depletion layer and the increase in impurity atoms and defects can be controlled to a minimum. Further, by using a low concentration substrate as the substrate, the junction capacitance between the source and the drain is reduced, which has the effect of alleviating the above-mentioned problems. Further, by providing the narrow and deep high concentration regions 10 and 11, it is possible to prevent a depletion layer from extending between the source and drain diffusion regions 3 and 4 and causing punch-through. Since the source and drain diffusion regions 3 and 4 overlap a part of these high concentration regions 10 and 11, the junction capacitance of that part increases, but since the area is relatively small, it can be ignored compared to the overall junction capacitance. Become. Furthermore, since the channel forming region 5 can be made to have a lower concentration than before, the switching speed can be increased.

Next, such source and drain diffusion regions 3,
In the embodiment of the present invention, narrow and deep high concentration regions 10 and 11 are formed at the boundary between the channel forming region 5 and the channel forming region 5.
A method of manufacturing a MOS transistor will be explained with reference to FIGS. 3a to 3c.

As shown in Figure a, an insulating oxide film (SiO ₂ ) is formed on the surface of a low concentration P-type silicon substrate (concentration 10 ¹³ cm ^-1 ).
2, remove the oxide film 2 on the source, drain and channel parts, and re-oxidize it to a depth of approximately
A gate oxide film 7 of 500 Å is provided. Next, an implantation channel forming region 5 is formed by ion implanting P-type impurity ¹¹ B ⁺ into the entire surface including the gate oxide film at a dose of 3×10 ¹¹ /cm ^-2 and accelerating to about 40 KeV. Next, a polycrystalline silicon growth layer 8 with a thickness of 4000 Å and a vacuum-deposited layer 9 of gold (Au) with a thickness of 2000 Å are sequentially formed using the usual CVD method, and then a photoresist 20 is deposited on top of the layer 8 and then patterned. The gate portion is left and the rest is removed by etching. In this case, the side surface of the gate portion has a constricted bottom shape with the photoresist 20 serving as an eaves, depending on the etching speed. This is what provides the self-alignment effect of the present invention.

Next, apply approximately 1 μm of aluminum (Al) on top of this.
Vertical deposition is performed to a thickness of m, and when the photoresist 20 on the gate part is lifted off, the Al layer on top of it is removed, and the gate part and its surrounding area covered with the photoresist 20 are removed, as shown in FIG. An Al layer 12 is deposited on the source, drain and insulating oxide except for the source, drain and insulating oxide. Therefore, a gap 13 without the Al layer 12 is created around the gate portion. When P-type impurity ³¹ P ^+, which is the same as that of the substrate, is implanted into this surface at a dose of 6×10 ¹² /cm ^-2 and accelerated to about 200 KeV, a narrow and deep P-type height with a peak value at a depth of about 5000 Å is formed. The concentration regions 10 and 11 are formed as a self-alignment effect.

Next, the Al layer and the Au layer 9 on the gate part are removed by etching, and as shown in FIG.
Further, electrodes 14, 15, and 16 are formed on the source, drain, and gate portions, respectively.

As explained above, according to the present invention, a high concentration region of the same conductivity type as the substrate, which is deeper than the depth of the source and drain diffusion, is placed at the boundary between the source and drain diffusion regions and the channel formation region, directly below the channel formation region. By forming a low concentration region,
Short channel with high breakdown voltage between source and drain
It is possible to realize an MIS transistor. Further, according to the manufacturing method of the present invention, the high concentration region can be formed very easily by utilizing the self-alignment effect.

Although the above description has been made using a MOS transistor as an example, the present invention can also be applied to a transistor using a silicon nitride film or the like as a gate insulating film.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the conventional example, Fig. 2 is an explanatory diagram of the configuration of the MIS transistor according to the present invention, and Fig. 3a
-c are explanatory diagrams of a manufacturing method according to an embodiment of the present invention, in which 1 is a substrate, 2 is an insulating oxide film, 3 is a source diffusion region, 4 is a drain diffusion region, 5 is a channel forming region, 7 is a gate oxide film, 8 is a polycrystalline silicon layer, 9 is a gold layer, 10 and 11 are high concentration regions, 12 is an aluminum layer, 13 is a gap around the gate part,
14, 15, 16 are the source, drain,
The gate electrode is shown.

Claims (1)

[Claims] 1. Remove the insulating oxide from the source, drain, and channel portions of the semiconductor substrate on which the insulating oxide has been deposited, form a gate oxide film by reoxidation, and form a polycrystalline silicon layer and a first mask layer thereon. are successively stacked, a photoresist is applied thereon and patterned to leave a gate portion, and other portions of the first mask layer and the polycrystalline silicon layer are removed by etching until the photoresist becomes an eaves shape; Next, after forming a second mask layer on the photoresist and on the source and drain parts, the photoresist and the second mask layer thereon are removed, and the first mask layer is removed.
Then, using the second mask layer as a mask, ions of the same conductivity type are implanted into the substrate, and the depth of the source and drain diffusion is formed at the end of the diffusion region to be formed in the source and drain portions, opposite to the channel forming region. A method for manufacturing an MIS transistor characterized by forming a highly doped region of the same conductivity type as a substrate deeper than the substrate.